1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
42 /* NOTE: most of this should work fine for the Cortex-M1 and
43 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 /* forward declarations */
48 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
49 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
50 static void cortex_m3_enable_watchpoints(struct target
*target
);
51 static int cortex_m3_store_core_reg_u32(struct target
*target
,
52 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
54 #ifdef ARMV7_GDB_HACKS
55 extern uint8_t armv7m_gdb_dummy_cpsr_value
[];
56 extern struct reg armv7m_gdb_dummy_cpsr_reg
;
59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
60 uint32_t *value
, int regnum
)
65 /* because the DCB_DCRDR is used for the emulated dcc channel
66 * we have to save/restore the DCB_DCRDR when used */
68 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
70 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
72 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
73 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
74 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
76 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
77 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
78 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
80 retval
= swjdp_transaction_endcheck(swjdp
);
82 /* restore DCB_DCRDR - this needs to be in a seperate
83 * transaction otherwise the emulated DCC channel breaks */
84 if (retval
== ERROR_OK
)
85 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
91 uint32_t value
, int regnum
)
96 /* because the DCB_DCRDR is used for the emulated dcc channel
97 * we have to save/restore the DCB_DCRDR when used */
99 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
101 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
103 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
104 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
107 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
108 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
109 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
111 retval
= swjdp_transaction_endcheck(swjdp
);
113 /* restore DCB_DCRDR - this needs to be in a seperate
114 * transaction otherwise the emulated DCC channel breaks */
115 if (retval
== ERROR_OK
)
116 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
121 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
122 uint32_t mask_on
, uint32_t mask_off
)
124 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
125 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
127 /* mask off status bits */
128 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
129 /* create new register mask */
130 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
132 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
135 static int cortex_m3_clear_halt(struct target
*target
)
137 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
138 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
140 /* clear step if any */
141 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
143 /* Read Debug Fault Status Register */
144 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
152 static int cortex_m3_single_step_core(struct target
*target
)
154 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
155 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
158 /* backup dhcsr reg */
159 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
161 /* mask interrupts if not done already */
162 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
163 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
164 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
167 /* restore dhcsr reg */
168 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
169 cortex_m3_clear_halt(target
);
174 static int cortex_m3_endreset_event(struct target
*target
)
178 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
179 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
180 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
181 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
183 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
184 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
186 /* this regsiter is used for emulated dcc channel */
187 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
189 /* Enable debug requests */
190 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
191 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
192 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
194 /* clear any interrupt masking */
195 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
197 /* Enable trace and dwt */
198 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
199 /* Monitor bus faults */
200 mem_ap_write_u32(swjdp
, NVIC_SHCSR
, SHCSR_BUSFAULTENA
);
203 target_write_u32(target
, FP_CTRL
, 3);
204 cortex_m3
->fpb_enabled
= 1;
206 /* Restore FPB registers */
207 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
209 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
212 /* Restore DWT registers */
213 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
215 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
217 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
219 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
220 dwt_list
[i
].function
);
222 swjdp_transaction_endcheck(swjdp
);
224 armv7m_invalidate_core_regs(target
);
226 /* make sure we have latest dhcsr flags */
227 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
232 static int cortex_m3_examine_debug_reason(struct target
*target
)
234 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
236 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
237 /* only check the debug reason if we don't know it already */
239 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
240 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
242 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
244 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
245 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
246 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
248 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
249 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
250 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
251 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
252 else /* EXTERNAL, HALTED */
253 target
->debug_reason
= DBG_REASON_UNDEFINED
;
259 static int cortex_m3_examine_exception_reason(struct target
*target
)
261 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
262 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
263 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
265 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
266 switch (armv7m
->exception_number
)
270 case 3: /* Hard Fault */
271 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
272 if (except_sr
& 0x40000000)
274 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
277 case 4: /* Memory Management */
278 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
279 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
281 case 5: /* Bus Fault */
282 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
283 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
285 case 6: /* Usage Fault */
286 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
288 case 11: /* SVCall */
290 case 12: /* Debug Monitor */
291 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
293 case 14: /* PendSV */
295 case 15: /* SysTick */
301 swjdp_transaction_endcheck(swjdp
);
302 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
"", armv7m_exception_string(armv7m
->exception_number
), \
303 shcsr
, except_sr
, cfsr
, except_ar
);
307 static int cortex_m3_debug_entry(struct target
*target
)
312 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
313 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
314 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
318 cortex_m3_clear_halt(target
);
319 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
321 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
324 /* Examine target state and mode */
325 /* First load register acessible through core debug port*/
326 int num_regs
= armv7m
->core_cache
->num_regs
;
328 for (i
= 0; i
< num_regs
; i
++)
330 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
331 armv7m
->read_core_reg(target
, i
);
334 xPSR
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32);
336 #ifdef ARMV7_GDB_HACKS
337 /* copy real xpsr reg for gdb, setting thumb bit */
338 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
339 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
340 armv7m_gdb_dummy_cpsr_reg
.valid
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
341 armv7m_gdb_dummy_cpsr_reg
.dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
;
344 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
347 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
348 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
351 /* Are we in an exception handler */
354 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
355 armv7m
->exception_number
= (xPSR
& 0x1FF);
359 armv7m
->core_mode
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1);
360 armv7m
->exception_number
= 0;
363 if (armv7m
->exception_number
)
365 cortex_m3_examine_exception_reason(target
);
368 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
369 armv7m_mode_strings
[armv7m
->core_mode
],
370 *(uint32_t*)(armv7m
->core_cache
->reg_list
[15].value
),
371 target_state_name(target
));
373 if (armv7m
->post_debug_entry
)
374 armv7m
->post_debug_entry(target
);
379 static int cortex_m3_poll(struct target
*target
)
382 enum target_state prev_target_state
= target
->state
;
383 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
384 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
386 /* Read from Debug Halting Control and Status Register */
387 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
388 if (retval
!= ERROR_OK
)
390 target
->state
= TARGET_UNKNOWN
;
394 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
396 /* check if still in reset */
397 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
399 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
401 target
->state
= TARGET_RESET
;
406 if (target
->state
== TARGET_RESET
)
408 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
409 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
);
410 cortex_m3_endreset_event(target
);
411 target
->state
= TARGET_RUNNING
;
412 prev_target_state
= TARGET_RUNNING
;
415 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
417 target
->state
= TARGET_HALTED
;
419 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
421 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
424 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
426 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
429 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
432 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
436 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
437 * How best to model low power modes?
440 if (target
->state
== TARGET_UNKNOWN
)
442 /* check if processor is retiring instructions */
443 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
445 target
->state
= TARGET_RUNNING
;
453 static int cortex_m3_halt(struct target
*target
)
455 LOG_DEBUG("target->state: %s",
456 target_state_name(target
));
458 if (target
->state
== TARGET_HALTED
)
460 LOG_DEBUG("target was already halted");
464 if (target
->state
== TARGET_UNKNOWN
)
466 LOG_WARNING("target was in unknown state when halt was requested");
469 if (target
->state
== TARGET_RESET
)
471 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
473 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
474 return ERROR_TARGET_FAILURE
;
478 /* we came here in a reset_halt or reset_init sequence
479 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
481 target
->debug_reason
= DBG_REASON_DBGRQ
;
487 /* Write to Debug Halting Control and Status Register */
488 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
490 target
->debug_reason
= DBG_REASON_DBGRQ
;
495 static int cortex_m3_soft_reset_halt(struct target
*target
)
497 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
498 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
499 uint32_t dcb_dhcsr
= 0;
500 int retval
, timeout
= 0;
502 /* Enter debug state on reset, cf. end_reset_event() */
503 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
505 /* Request a reset */
506 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
, AIRCR_VECTKEY
| AIRCR_VECTRESET
);
507 target
->state
= TARGET_RESET
;
509 /* registers are now invalid */
510 armv7m_invalidate_core_regs(target
);
512 while (timeout
< 100)
514 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
515 if (retval
== ERROR_OK
)
517 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
518 if ((dcb_dhcsr
& S_HALT
) && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
520 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32
", nvic_dfsr 0x%" PRIx32
"", dcb_dhcsr
, cortex_m3
->nvic_dfsr
);
521 cortex_m3_poll(target
);
525 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32
", %i ms", dcb_dhcsr
, timeout
);
534 static void cortex_m3_enable_breakpoints(struct target
*target
)
536 struct breakpoint
*breakpoint
= target
->breakpoints
;
538 /* set any pending breakpoints */
541 if (breakpoint
->set
== 0)
542 cortex_m3_set_breakpoint(target
, breakpoint
);
543 breakpoint
= breakpoint
->next
;
547 static int cortex_m3_resume(struct target
*target
, int current
,
548 uint32_t address
, int handle_breakpoints
, int debug_execution
)
550 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
551 struct breakpoint
*breakpoint
= NULL
;
554 if (target
->state
!= TARGET_HALTED
)
556 LOG_WARNING("target not halted");
557 return ERROR_TARGET_NOT_HALTED
;
560 if (!debug_execution
)
562 target_free_all_working_areas(target
);
563 cortex_m3_enable_breakpoints(target
);
564 cortex_m3_enable_watchpoints(target
);
569 /* Disable interrupts */
570 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
571 * This is probably the same issue as Cortex-M3 Errata 377493:
572 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
573 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
574 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
575 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
577 /* Make sure we are in Thumb mode */
578 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
579 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32) | (1 << 24));
580 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
581 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
584 /* current = 1: continue on current pc, otherwise continue at <address> */
587 buf_set_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32, address
);
588 armv7m
->core_cache
->reg_list
[15].dirty
= 1;
589 armv7m
->core_cache
->reg_list
[15].valid
= 1;
592 resume_pc
= buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32);
594 armv7m_restore_context(target
);
596 /* the front-end may request us not to handle breakpoints */
597 if (handle_breakpoints
)
599 /* Single step past breakpoint at current address */
600 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
602 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
604 breakpoint
->unique_id
);
605 cortex_m3_unset_breakpoint(target
, breakpoint
);
606 cortex_m3_single_step_core(target
);
607 cortex_m3_set_breakpoint(target
, breakpoint
);
612 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
614 target
->debug_reason
= DBG_REASON_NOTHALTED
;
616 /* registers are now invalid */
617 armv7m_invalidate_core_regs(target
);
618 if (!debug_execution
)
620 target
->state
= TARGET_RUNNING
;
621 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
622 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
626 target
->state
= TARGET_DEBUG_RUNNING
;
627 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
628 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
634 /* int irqstepcount = 0; */
635 static int cortex_m3_step(struct target
*target
, int current
,
636 uint32_t address
, int handle_breakpoints
)
638 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
639 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
640 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
641 struct breakpoint
*breakpoint
= NULL
;
643 if (target
->state
!= TARGET_HALTED
)
645 LOG_WARNING("target not halted");
646 return ERROR_TARGET_NOT_HALTED
;
649 /* current = 1: continue on current pc, otherwise continue at <address> */
651 buf_set_u32(cortex_m3
->armv7m
.core_cache
->reg_list
[15].value
,
654 /* the front-end may request us not to handle breakpoints */
655 if (handle_breakpoints
) {
656 breakpoint
= breakpoint_find(target
, buf_get_u32(armv7m
657 ->core_cache
->reg_list
[15].value
, 0, 32));
659 cortex_m3_unset_breakpoint(target
, breakpoint
);
662 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
664 armv7m_restore_context(target
);
666 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
668 /* set step and clear halt */
669 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
670 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
672 /* registers are now invalid */
673 armv7m_invalidate_core_regs(target
);
676 cortex_m3_set_breakpoint(target
, breakpoint
);
678 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
680 cortex_m3_debug_entry(target
);
681 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
683 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
687 static int cortex_m3_assert_reset(struct target
*target
)
689 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
690 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
693 LOG_DEBUG("target->state: %s",
694 target_state_name(target
));
696 enum reset_types jtag_reset_config
= jtag_get_reset_config();
699 * We can reset Cortex-M3 targets using just the NVIC without
700 * requiring SRST, getting a SoC reset (or a core-only reset)
701 * instead of a system reset.
703 if (!(jtag_reset_config
& RESET_HAS_SRST
))
706 /* Enable debug requests */
707 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
708 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
709 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
711 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
713 if (!target
->reset_halt
)
715 /* Set/Clear C_MASKINTS in a separate operation */
716 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
717 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
| C_HALT
);
719 /* clear any debug flags before resuming */
720 cortex_m3_clear_halt(target
);
722 /* clear C_HALT in dhcsr reg */
723 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
725 /* Enter debug state on reset, cf. end_reset_event() */
726 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
730 /* Enter debug state on reset, cf. end_reset_event() */
731 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
735 * When nRST is asserted on most Stellaris devices, it clears some of
736 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
737 * and OpenOCD depends on those TRMs. So we won't use SRST on those
738 * chips. (Only power-on reset should affect debug state, beyond a
739 * few specified bits; not the chip's nRST input, wired to SRST.)
741 * REVISIT current errata specs don't seem to cover this issue.
742 * Do we have more details than this email?
743 * https://lists.berlios.de/pipermail
744 * /openocd-development/2008-August/003065.html
746 if (strcmp(target
->variant
, "lm3s") == 0)
748 /* Check for silicon revisions with the issue. */
751 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
753 switch ((did0
>> 16) & 0xff)
756 /* all Sandstorm suffer issue */
762 /* Fury and DustDevil rev A have
763 * this nRST problem. It should
764 * be fixed in rev B silicon.
766 if (((did0
>> 8) & 0xff) == 0)
770 /* Tempest should be fine. */
778 /* default to asserting srst */
779 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
781 jtag_add_reset(1, 1);
785 jtag_add_reset(0, 1);
790 /* Use a standard Cortex-M3 software reset mechanism.
791 * SYSRESETREQ will reset SoC peripherals outside the
792 * core, like watchdog timers, if the SoC wires it up
793 * correctly. Else VECRESET can reset just the core.
795 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
796 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
797 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
800 /* I do not know why this is necessary, but it
801 * fixes strange effects (step/resume cause NMI
802 * after reset) on LM3S6918 -- Michael Schwingen
805 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
809 target
->state
= TARGET_RESET
;
810 jtag_add_sleep(50000);
812 armv7m_invalidate_core_regs(target
);
814 if (target
->reset_halt
)
817 if ((retval
= target_halt(target
)) != ERROR_OK
)
824 static int cortex_m3_deassert_reset(struct target
*target
)
826 LOG_DEBUG("target->state: %s",
827 target_state_name(target
));
829 /* deassert reset lines */
830 jtag_add_reset(0, 0);
836 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
841 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
842 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
846 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
850 if (cortex_m3
->auto_bp_type
)
852 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
855 if (breakpoint
->type
== BKPT_HARD
)
857 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
859 if (fp_num
>= cortex_m3
->fp_num_code
)
861 LOG_ERROR("Can not find free FPB Comparator!");
864 breakpoint
->set
= fp_num
+ 1;
865 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
866 comparator_list
[fp_num
].used
= 1;
867 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
868 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
869 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
870 if (!cortex_m3
->fpb_enabled
)
872 LOG_DEBUG("FPB wasn't enabled, do it now");
873 target_write_u32(target
, FP_CTRL
, 3);
876 else if (breakpoint
->type
== BKPT_SOFT
)
879 buf_set_u32(code
, 0, 32, ARMV7M_T_BKPT(0x11));
880 if ((retval
= target_read_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
884 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, code
)) != ERROR_OK
)
888 breakpoint
->set
= 0x11; /* Any nice value but 0 */
891 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
892 breakpoint
->unique_id
,
893 (int)(breakpoint
->type
),
902 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
905 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
906 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
908 if (!breakpoint
->set
)
910 LOG_WARNING("breakpoint not set");
914 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
915 breakpoint
->unique_id
,
916 (int)(breakpoint
->type
),
921 if (breakpoint
->type
== BKPT_HARD
)
923 int fp_num
= breakpoint
->set
- 1;
924 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
926 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
929 comparator_list
[fp_num
].used
= 0;
930 comparator_list
[fp_num
].fpcr_value
= 0;
931 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
935 /* restore original instruction (kept in target endianness) */
936 if (breakpoint
->length
== 4)
938 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
945 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
957 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
959 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
961 if (cortex_m3
->auto_bp_type
)
963 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
964 #ifdef ARMV7_GDB_HACKS
965 if (breakpoint
->length
!= 2) {
966 /* XXX Hack: Replace all breakpoints with length != 2 with
967 * a hardware breakpoint. */
968 breakpoint
->type
= BKPT_HARD
;
969 breakpoint
->length
= 2;
974 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
976 LOG_INFO("flash patch comparator requested outside code memory region");
977 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
980 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
982 LOG_INFO("soft breakpoint requested in code (flash) memory region");
983 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
986 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
988 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
989 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
992 if ((breakpoint
->length
!= 2))
994 LOG_INFO("only breakpoints of two bytes length supported");
995 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
998 if (breakpoint
->type
== BKPT_HARD
)
999 cortex_m3
->fp_code_available
--;
1000 cortex_m3_set_breakpoint(target
, breakpoint
);
1006 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1008 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1010 /* REVISIT why check? FBP can be updated with core running ... */
1011 if (target
->state
!= TARGET_HALTED
)
1013 LOG_WARNING("target not halted");
1014 return ERROR_TARGET_NOT_HALTED
;
1017 if (cortex_m3
->auto_bp_type
)
1019 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1022 if (breakpoint
->set
)
1024 cortex_m3_unset_breakpoint(target
, breakpoint
);
1027 if (breakpoint
->type
== BKPT_HARD
)
1028 cortex_m3
->fp_code_available
++;
1034 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1037 uint32_t mask
, temp
;
1038 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1040 /* watchpoint params were validated earlier */
1042 temp
= watchpoint
->length
;
1049 /* REVISIT Don't fully trust these "not used" records ... users
1050 * may set up breakpoints by hand, e.g. dual-address data value
1051 * watchpoint using comparator #1; comparator #0 matching cycle
1052 * count; send data trace info through ITM and TPIU; etc
1054 struct cortex_m3_dwt_comparator
*comparator
;
1056 for (comparator
= cortex_m3
->dwt_comparator_list
;
1057 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1058 comparator
++, dwt_num
++)
1060 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1062 LOG_ERROR("Can not find free DWT Comparator");
1065 comparator
->used
= 1;
1066 watchpoint
->set
= dwt_num
+ 1;
1068 comparator
->comp
= watchpoint
->address
;
1069 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1072 comparator
->mask
= mask
;
1073 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1076 switch (watchpoint
->rw
) {
1078 comparator
->function
= 5;
1081 comparator
->function
= 6;
1084 comparator
->function
= 7;
1087 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1088 comparator
->function
);
1090 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1091 watchpoint
->unique_id
, dwt_num
,
1092 (unsigned) comparator
->comp
,
1093 (unsigned) comparator
->mask
,
1094 (unsigned) comparator
->function
);
1099 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1101 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1102 struct cortex_m3_dwt_comparator
*comparator
;
1105 if (!watchpoint
->set
)
1107 LOG_WARNING("watchpoint (wpid: %d) not set",
1108 watchpoint
->unique_id
);
1112 dwt_num
= watchpoint
->set
- 1;
1114 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1115 watchpoint
->unique_id
, dwt_num
,
1116 (unsigned) watchpoint
->address
);
1118 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1120 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1124 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1125 comparator
->used
= 0;
1126 comparator
->function
= 0;
1127 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1128 comparator
->function
);
1130 watchpoint
->set
= 0;
1136 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1138 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1140 /* REVISIT why check? DWT can be updated with core running ... */
1141 if (target
->state
!= TARGET_HALTED
)
1143 LOG_WARNING("target not halted");
1144 return ERROR_TARGET_NOT_HALTED
;
1147 if (cortex_m3
->dwt_comp_available
< 1)
1149 LOG_DEBUG("no comparators?");
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1153 /* hardware doesn't support data value masking */
1154 if (watchpoint
->mask
!= ~(uint32_t)0) {
1155 LOG_DEBUG("watchpoint value masks not supported");
1156 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1159 /* hardware allows address masks of up to 32K */
1162 for (mask
= 0; mask
< 16; mask
++) {
1163 if ((1u << mask
) == watchpoint
->length
)
1167 LOG_DEBUG("unsupported watchpoint length");
1168 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1170 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1171 LOG_DEBUG("watchpoint address is unaligned");
1172 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1175 /* Caller doesn't seem to be able to describe watching for data
1176 * values of zero; that flags "no value".
1178 * REVISIT This DWT may well be able to watch for specific data
1179 * values. Requires comparator #1 to set DATAVMATCH and match
1180 * the data, and another comparator (DATAVADDR0) matching addr.
1182 if (watchpoint
->value
) {
1183 LOG_DEBUG("data value watchpoint not YET supported");
1184 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1187 cortex_m3
->dwt_comp_available
--;
1188 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1194 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1196 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1198 /* REVISIT why check? DWT can be updated with core running ... */
1199 if (target
->state
!= TARGET_HALTED
)
1201 LOG_WARNING("target not halted");
1202 return ERROR_TARGET_NOT_HALTED
;
1205 if (watchpoint
->set
)
1207 cortex_m3_unset_watchpoint(target
, watchpoint
);
1210 cortex_m3
->dwt_comp_available
++;
1211 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1216 static void cortex_m3_enable_watchpoints(struct target
*target
)
1218 struct watchpoint
*watchpoint
= target
->watchpoints
;
1220 /* set any pending watchpoints */
1223 if (watchpoint
->set
== 0)
1224 cortex_m3_set_watchpoint(target
, watchpoint
);
1225 watchpoint
= watchpoint
->next
;
1229 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1230 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1233 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1234 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1236 /* NOTE: we "know" here that the register identifiers used
1237 * in the v7m header match the Cortex-M3 Debug Core Register
1238 * Selector values for R0..R15, xPSR, MSP, and PSP.
1242 /* read a normal core register */
1243 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1245 if (retval
!= ERROR_OK
)
1247 LOG_ERROR("JTAG failure %i",retval
);
1248 return ERROR_JTAG_DEVICE_ERROR
;
1250 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1253 case ARMV7M_PRIMASK
:
1254 case ARMV7M_BASEPRI
:
1255 case ARMV7M_FAULTMASK
:
1256 case ARMV7M_CONTROL
:
1257 /* Cortex-M3 packages these four registers as bitfields
1258 * in one Debug Core register. So say r0 and r2 docs;
1259 * it was removed from r1 docs, but still works.
1261 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1265 case ARMV7M_PRIMASK
:
1266 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1269 case ARMV7M_BASEPRI
:
1270 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1273 case ARMV7M_FAULTMASK
:
1274 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1277 case ARMV7M_CONTROL
:
1278 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1282 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1286 return ERROR_INVALID_ARGUMENTS
;
1292 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1293 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1297 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1298 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1300 #ifdef ARMV7_GDB_HACKS
1301 /* If the LR register is being modified, make sure it will put us
1302 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1303 * hack to deal with the fact that gdb will sometimes "forge"
1304 * return addresses, and doesn't set the LSB correctly (i.e., when
1305 * printing expressions containing function calls, it sets LR = 0.)
1306 * Valid exception return codes have bit 0 set too.
1308 if (num
== ARMV7M_R14
)
1312 /* NOTE: we "know" here that the register identifiers used
1313 * in the v7m header match the Cortex-M3 Debug Core Register
1314 * Selector values for R0..R15, xPSR, MSP, and PSP.
1318 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1319 if (retval
!= ERROR_OK
)
1321 LOG_ERROR("JTAG failure %i", retval
);
1322 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
1323 return ERROR_JTAG_DEVICE_ERROR
;
1325 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1328 case ARMV7M_PRIMASK
:
1329 case ARMV7M_BASEPRI
:
1330 case ARMV7M_FAULTMASK
:
1331 case ARMV7M_CONTROL
:
1332 /* Cortex-M3 packages these four registers as bitfields
1333 * in one Debug Core register. So say r0 and r2 docs;
1334 * it was removed from r1 docs, but still works.
1336 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1340 case ARMV7M_PRIMASK
:
1341 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1344 case ARMV7M_BASEPRI
:
1345 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1348 case ARMV7M_FAULTMASK
:
1349 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1352 case ARMV7M_CONTROL
:
1353 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1357 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1359 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1363 return ERROR_INVALID_ARGUMENTS
;
1369 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1370 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1372 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1373 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1374 int retval
= ERROR_INVALID_ARGUMENTS
;
1376 /* cortex_m3 handles unaligned memory access */
1377 if (count
&& buffer
) {
1380 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1383 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1386 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1394 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1395 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1397 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1398 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1399 int retval
= ERROR_INVALID_ARGUMENTS
;
1401 if (count
&& buffer
) {
1404 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1407 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1410 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1418 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1419 uint32_t count
, uint8_t *buffer
)
1421 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1424 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1425 struct target
*target
)
1427 armv7m_build_reg_cache(target
);
1431 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1432 * on r/w if the core is not running, and clear on resume or reset ... or
1433 * at least, in a post_restore_context() method.
1436 struct dwt_reg_state
{
1437 struct target
*target
;
1439 uint32_t value
; /* scratch/cache */
1442 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1444 struct dwt_reg_state
*state
= reg
->arch_info
;
1446 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1449 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1451 struct dwt_reg_state
*state
= reg
->arch_info
;
1453 return target_write_u32(state
->target
, state
->addr
,
1454 buf_get_u32(buf
, 0, reg
->size
));
1463 static struct dwt_reg dwt_base_regs
[] = {
1464 { DWT_CTRL
, "dwt_ctrl", 32, },
1465 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1466 /* plus some 8 bit counters, useful for profiling with TPIU */
1469 static struct dwt_reg dwt_comp
[] = {
1470 #define DWT_COMPARATOR(i) \
1471 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1472 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1473 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1478 #undef DWT_COMPARATOR
1481 static int dwt_reg_type
= -1;
1484 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1486 struct dwt_reg_state
*state
;
1488 state
= calloc(1, sizeof *state
);
1491 state
->addr
= d
->addr
;
1496 r
->value
= &state
->value
;
1497 r
->arch_info
= state
;
1498 r
->arch_type
= dwt_reg_type
;
1502 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1505 struct reg_cache
*cache
;
1506 struct cortex_m3_dwt_comparator
*comparator
;
1509 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1511 LOG_DEBUG("no DWT");
1515 if (dwt_reg_type
< 0)
1516 dwt_reg_type
= register_reg_arch_type(cortex_m3_dwt_get_reg
,
1517 cortex_m3_dwt_set_reg
);
1519 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1520 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1521 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1522 sizeof(struct cortex_m3_dwt_comparator
));
1523 if (!cm3
->dwt_comparator_list
) {
1525 cm3
->dwt_num_comp
= 0;
1526 LOG_ERROR("out of mem");
1530 cache
= calloc(1, sizeof *cache
);
1533 free(cm3
->dwt_comparator_list
);
1536 cache
->name
= "cortex-m3 dwt registers";
1537 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1538 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1539 if (!cache
->reg_list
) {
1544 for (reg
= 0; reg
< 2; reg
++)
1545 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1546 dwt_base_regs
+ reg
);
1548 comparator
= cm3
->dwt_comparator_list
;
1549 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1552 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1553 for (j
= 0; j
< 3; j
++, reg
++)
1554 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1555 dwt_comp
+ 3 * i
+ j
);
1558 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1559 cm3
->dwt_cache
= cache
;
1561 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1562 dwtcr
, cm3
->dwt_num_comp
,
1563 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1565 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1566 * implement single-address data value watchpoints ... so we
1567 * won't need to check it later, when asked to set one up.
1571 static int cortex_m3_examine(struct target
*target
)
1574 uint32_t cpuid
, fpcr
;
1576 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1577 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1579 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1582 if (!target_was_examined(target
))
1584 target_set_examined(target
);
1586 /* Read from Device Identification Registers */
1587 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1588 if (retval
!= ERROR_OK
)
1591 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1592 LOG_DEBUG("CORTEX-M3 processor detected");
1593 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1595 /* NOTE: FPB and DWT are both optional. */
1598 target_read_u32(target
, FP_CTRL
, &fpcr
);
1599 cortex_m3
->auto_bp_type
= 1;
1600 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1601 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1602 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1603 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1604 cortex_m3
->fpb_enabled
= fpcr
& 1;
1605 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1607 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1608 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1610 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1613 cortex_m3_dwt_setup(cortex_m3
, target
);
1619 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1623 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1624 *ctrl
= (uint8_t)dcrdr
;
1625 *value
= (uint8_t)(dcrdr
>> 8);
1627 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1629 /* write ack back to software dcc register
1630 * signify we have read data */
1631 if (dcrdr
& (1 << 0))
1634 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1640 static int cortex_m3_target_request_data(struct target
*target
,
1641 uint32_t size
, uint8_t *buffer
)
1643 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1644 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1649 for (i
= 0; i
< (size
* 4); i
++)
1651 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1658 static int cortex_m3_handle_target_request(void *priv
)
1660 struct target
*target
= priv
;
1661 if (!target_was_examined(target
))
1663 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1664 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1666 if (!target
->dbg_msg_enabled
)
1669 if (target
->state
== TARGET_RUNNING
)
1674 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1676 /* check if we have data */
1677 if (ctrl
& (1 << 0))
1681 /* we assume target is quick enough */
1683 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1684 request
|= (data
<< 8);
1685 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1686 request
|= (data
<< 16);
1687 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1688 request
|= (data
<< 24);
1689 target_request(target
, request
);
1696 static int cortex_m3_init_arch_info(struct target
*target
,
1697 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1700 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1702 armv7m_init_arch_info(target
, armv7m
);
1704 /* prepare JTAG information for the new target */
1705 cortex_m3
->jtag_info
.tap
= tap
;
1706 cortex_m3
->jtag_info
.scann_size
= 4;
1708 armv7m
->swjdp_info
.dp_select_value
= -1;
1709 armv7m
->swjdp_info
.ap_csw_value
= -1;
1710 armv7m
->swjdp_info
.ap_tar_value
= -1;
1711 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1712 armv7m
->swjdp_info
.memaccess_tck
= 8;
1713 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1715 /* register arch-specific functions */
1716 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1718 armv7m
->post_debug_entry
= NULL
;
1720 armv7m
->pre_restore_context
= NULL
;
1721 armv7m
->post_restore_context
= NULL
;
1723 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1724 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1726 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1728 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1736 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1738 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1740 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1741 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1746 /*--------------------------------------------------------------------------*/
1748 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1749 struct cortex_m3_common
*cm3
)
1751 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1752 command_print(cmd_ctx
, "target is not a Cortex-M3");
1753 return ERROR_TARGET_INVALID
;
1759 * Only stuff below this line should need to verify that its target
1760 * is a Cortex-M3. Everything else should have indirected through the
1761 * cortexm3_target structure, which is only used with CM3 targets.
1765 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1766 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1767 * that *only* Thumb2 disassembly matters. There are also some small
1768 * additions to Thumb2 that are specific to ARMv7-M.
1770 COMMAND_HANDLER(handle_cortex_m3_disassemble_command
)
1773 struct target
*target
= get_current_target(cmd_ctx
);
1774 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1776 unsigned long count
= 1;
1777 struct arm_instruction cur_instruction
;
1779 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1780 if (retval
!= ERROR_OK
)
1786 COMMAND_PARSE_NUMBER(ulong
, args
[1], count
);
1789 COMMAND_PARSE_NUMBER(u32
, args
[0], address
);
1792 command_print(cmd_ctx
,
1793 "usage: cortex_m3 disassemble <address> [<count>]");
1798 retval
= thumb2_opcode(target
, address
, &cur_instruction
);
1799 if (retval
!= ERROR_OK
)
1801 command_print(cmd_ctx
, "%s", cur_instruction
.text
);
1802 address
+= cur_instruction
.instruction_size
;
1808 static const struct {
1812 { "hard_err", VC_HARDERR
, },
1813 { "int_err", VC_INTERR
, },
1814 { "bus_err", VC_BUSERR
, },
1815 { "state_err", VC_STATERR
, },
1816 { "chk_err", VC_CHKERR
, },
1817 { "nocp_err", VC_NOCPERR
, },
1818 { "mm_err", VC_MMERR
, },
1819 { "reset", VC_CORERESET
, },
1822 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1824 struct target
*target
= get_current_target(cmd_ctx
);
1825 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1826 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1827 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1830 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1831 if (retval
!= ERROR_OK
)
1834 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1840 if (strcmp(args
[0], "all") == 0) {
1841 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1842 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1843 | VC_MMERR
| VC_CORERESET
;
1845 } else if (strcmp(args
[0], "none") == 0) {
1849 while (argc
-- > 0) {
1851 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1852 if (strcmp(args
[argc
], vec_ids
[i
].name
) != 0)
1854 catch |= vec_ids
[i
].mask
;
1857 if (i
== ARRAY_SIZE(vec_ids
)) {
1858 LOG_ERROR("No CM3 vector '%s'", args
[argc
]);
1859 return ERROR_INVALID_ARGUMENTS
;
1866 /* write, but don't assume it stuck */
1867 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1868 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1871 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1872 command_print(cmd_ctx
, "%9s: %s", vec_ids
[i
].name
,
1873 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1878 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1880 struct target
*target
= get_current_target(cmd_ctx
);
1881 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1884 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1885 if (retval
!= ERROR_OK
)
1888 if (target
->state
!= TARGET_HALTED
)
1890 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", CMD_NAME
);
1896 if (!strcmp(args
[0], "on"))
1898 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
1900 else if (!strcmp(args
[0], "off"))
1902 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
1906 command_print(cmd_ctx
, "usage: cortex_m3 maskisr ['on'|'off']");
1910 command_print(cmd_ctx
, "cortex_m3 interrupt mask %s",
1911 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
1916 static int cortex_m3_register_commands(struct command_context
*cmd_ctx
)
1919 struct command
*cortex_m3_cmd
;
1921 retval
= armv7m_register_commands(cmd_ctx
);
1923 cortex_m3_cmd
= register_command(cmd_ctx
, NULL
, "cortex_m3",
1924 NULL
, COMMAND_ANY
, "cortex_m3 specific commands");
1926 register_command(cmd_ctx
, cortex_m3_cmd
, "disassemble",
1927 handle_cortex_m3_disassemble_command
, COMMAND_EXEC
,
1928 "disassemble Thumb2 instructions <address> [<count>]");
1929 register_command(cmd_ctx
, cortex_m3_cmd
, "maskisr",
1930 handle_cortex_m3_mask_interrupts_command
, COMMAND_EXEC
,
1931 "mask cortex_m3 interrupts ['on'|'off']");
1932 register_command(cmd_ctx
, cortex_m3_cmd
, "vector_catch",
1933 handle_cortex_m3_vector_catch_command
, COMMAND_EXEC
,
1934 "catch hardware vectors ['all'|'none'|<list>]");
1939 struct target_type cortexm3_target
=
1941 .name
= "cortex_m3",
1943 .poll
= cortex_m3_poll
,
1944 .arch_state
= armv7m_arch_state
,
1946 .target_request_data
= cortex_m3_target_request_data
,
1948 .halt
= cortex_m3_halt
,
1949 .resume
= cortex_m3_resume
,
1950 .step
= cortex_m3_step
,
1952 .assert_reset
= cortex_m3_assert_reset
,
1953 .deassert_reset
= cortex_m3_deassert_reset
,
1954 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
1956 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
1958 .read_memory
= cortex_m3_read_memory
,
1959 .write_memory
= cortex_m3_write_memory
,
1960 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
1961 .checksum_memory
= armv7m_checksum_memory
,
1962 .blank_check_memory
= armv7m_blank_check_memory
,
1964 .run_algorithm
= armv7m_run_algorithm
,
1966 .add_breakpoint
= cortex_m3_add_breakpoint
,
1967 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
1968 .add_watchpoint
= cortex_m3_add_watchpoint
,
1969 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
1971 .register_commands
= cortex_m3_register_commands
,
1972 .target_create
= cortex_m3_target_create
,
1973 .init_target
= cortex_m3_init_target
,
1974 .examine
= cortex_m3_examine
,