src/target/mips32.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "mips32.h"
  30 #include "register.h"
  31
  32
  33 char* mips32_core_reg_list[] =
  34 {
  35         "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
  36         "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
  37         "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
  38         "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
  39         "status", "lo", "hi", "badvaddr", "cause", "pc"
  40 };
  41
  42 struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
  43 {
  44         {0, NULL, NULL},
  45         {1, NULL, NULL},
  46         {2, NULL, NULL},
  47         {3, NULL, NULL},
  48         {4, NULL, NULL},
  49         {5, NULL, NULL},
  50         {6, NULL, NULL},
  51         {7, NULL, NULL},
  52         {8, NULL, NULL},
  53         {9, NULL, NULL},
  54         {10, NULL, NULL},
  55         {11, NULL, NULL},
  56         {12, NULL, NULL},
  57         {13, NULL, NULL},
  58         {14, NULL, NULL},
  59         {15, NULL, NULL},
  60         {16, NULL, NULL},
  61         {17, NULL, NULL},
  62         {18, NULL, NULL},
  63         {19, NULL, NULL},
  64         {20, NULL, NULL},
  65         {21, NULL, NULL},
  66         {22, NULL, NULL},
  67         {23, NULL, NULL},
  68         {24, NULL, NULL},
  69         {25, NULL, NULL},
  70         {26, NULL, NULL},
  71         {27, NULL, NULL},
  72         {28, NULL, NULL},
  73         {29, NULL, NULL},
  74         {30, NULL, NULL},
  75         {31, NULL, NULL},
  76
  77         {32, NULL, NULL},
  78         {33, NULL, NULL},
  79         {34, NULL, NULL},
  80         {35, NULL, NULL},
  81         {36, NULL, NULL},
  82         {37, NULL, NULL},
  83 };
  84
  85 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
  86  * we also add 18 unknown registers to handle gdb requests */
  87
  88 #define MIPS32NUMFPREGS 34 + 18
  89
  90 uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
  91
  92 struct reg mips32_gdb_dummy_fp_reg =
  93 {
  94         .name = "GDB dummy floating-point register",
  95         .value = mips32_gdb_dummy_fp_value,
  96         .dirty = 0,
  97         .valid = 1,
  98         .size = 32,
  99         .arch_info = NULL,
 100         .arch_type = 0,
 101 };
 102
 103 int mips32_core_reg_arch_type = -1;
 104
 105 int mips32_get_core_reg(struct reg *reg)
 106 {
 107         int retval;
 108         struct mips32_core_reg *mips32_reg = reg->arch_info;
 109         struct target *target = mips32_reg->target;
 110         struct mips32_common *mips32_target = target->arch_info;
 111
 112         if (target->state != TARGET_HALTED)
 113         {
 114                 return ERROR_TARGET_NOT_HALTED;
 115         }
 116
 117         retval = mips32_target->read_core_reg(target, mips32_reg->num);
 118
 119         return retval;
 120 }
 121
 122 int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 123 {
 124         struct mips32_core_reg *mips32_reg = reg->arch_info;
 125         struct target *target = mips32_reg->target;
 126         uint32_t value = buf_get_u32(buf, 0, 32);
 127
 128         if (target->state != TARGET_HALTED)
 129         {
 130                 return ERROR_TARGET_NOT_HALTED;
 131         }
 132
 133         buf_set_u32(reg->value, 0, 32, value);
 134         reg->dirty = 1;
 135         reg->valid = 1;
 136
 137         return ERROR_OK;
 138 }
 139
 140 int mips32_read_core_reg(struct target *target, int num)
 141 {
 142         uint32_t reg_value;
 143         struct mips32_core_reg *mips_core_reg;
 144
 145         /* get pointers to arch-specific information */
 146         struct mips32_common *mips32 = target->arch_info;
 147
 148         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 149                 return ERROR_INVALID_ARGUMENTS;
 150
 151         mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 152         reg_value = mips32->core_regs[num];
 153         buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
 154         mips32->core_cache->reg_list[num].valid = 1;
 155         mips32->core_cache->reg_list[num].dirty = 0;
 156
 157         return ERROR_OK;
 158 }
 159
 160 int mips32_write_core_reg(struct target *target, int num)
 161 {
 162         uint32_t reg_value;
 163         struct mips32_core_reg *mips_core_reg;
 164
 165         /* get pointers to arch-specific information */
 166         struct mips32_common *mips32 = target->arch_info;
 167
 168         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 169                 return ERROR_INVALID_ARGUMENTS;
 170
 171         reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 172         mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 173         mips32->core_regs[num] = reg_value;
 174         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 175         mips32->core_cache->reg_list[num].valid = 1;
 176         mips32->core_cache->reg_list[num].dirty = 0;
 177
 178         return ERROR_OK;
 179 }
 180
 181 int mips32_invalidate_core_regs(struct target *target)
 182 {
 183         /* get pointers to arch-specific information */
 184         struct mips32_common *mips32 = target->arch_info;
 185         int i;
 186
 187         for (i = 0; i < mips32->core_cache->num_regs; i++)
 188         {
 189                 mips32->core_cache->reg_list[i].valid = 0;
 190                 mips32->core_cache->reg_list[i].dirty = 0;
 191         }
 192
 193         return ERROR_OK;
 194 }
 195
 196 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 197 {
 198         /* get pointers to arch-specific information */
 199         struct mips32_common *mips32 = target->arch_info;
 200         int i;
 201
 202         /* include floating point registers */
 203         *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
 204         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 205
 206         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 207         {
 208                 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
 209         }
 210
 211         /* add dummy floating points regs */
 212         for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
 213         {
 214                 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
 215         }
 216
 217         return ERROR_OK;
 218 }
 219
 220 int mips32_save_context(struct target *target)
 221 {
 222         int i;
 223
 224         /* get pointers to arch-specific information */
 225         struct mips32_common *mips32 = target->arch_info;
 226         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 227
 228         /* read core registers */
 229         mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
 230
 231         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 232         {
 233                 if (!mips32->core_cache->reg_list[i].valid)
 234                 {
 235                         mips32->read_core_reg(target, i);
 236                 }
 237         }
 238
 239         return ERROR_OK;
 240 }
 241
 242 int mips32_restore_context(struct target *target)
 243 {
 244         int i;
 245
 246         /* get pointers to arch-specific information */
 247         struct mips32_common *mips32 = target->arch_info;
 248         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 249
 250         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 251         {
 252                 if (mips32->core_cache->reg_list[i].dirty)
 253                 {
 254                         mips32->write_core_reg(target, i);
 255                 }
 256         }
 257
 258         /* write core regs */
 259         mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
 260
 261         return ERROR_OK;
 262 }
 263
 264 int mips32_arch_state(struct target *target)
 265 {
 266         struct mips32_common *mips32 = target->arch_info;
 267
 268         if (mips32->common_magic != MIPS32_COMMON_MAGIC)
 269         {
 270                 LOG_ERROR("BUG: called for a non-MIPS32 target");
 271                 return ERROR_FAIL;
 272         }
 273
 274         LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
 275                 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 276                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 277
 278         return ERROR_OK;
 279 }
 280
 281 struct reg_cache *mips32_build_reg_cache(struct target *target)
 282 {
 283         /* get pointers to arch-specific information */
 284         struct mips32_common *mips32 = target->arch_info;
 285
 286         int num_regs = MIPS32NUMCOREREGS;
 287         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 288         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 289         struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
 290         struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
 291         int i;
 292
 293         if (mips32_core_reg_arch_type == -1)
 294                 mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
 295
 296         register_init_dummy(&mips32_gdb_dummy_fp_reg);
 297
 298         /* Build the process context cache */
 299         cache->name = "mips32 registers";
 300         cache->next = NULL;
 301         cache->reg_list = reg_list;
 302         cache->num_regs = num_regs;
 303         (*cache_p) = cache;
 304         mips32->core_cache = cache;
 305
 306         for (i = 0; i < num_regs; i++)
 307         {
 308                 arch_info[i] = mips32_core_reg_list_arch_info[i];
 309                 arch_info[i].target = target;
 310                 arch_info[i].mips32_common = mips32;
 311                 reg_list[i].name = mips32_core_reg_list[i];
 312                 reg_list[i].size = 32;
 313                 reg_list[i].value = calloc(1, 4);
 314                 reg_list[i].dirty = 0;
 315                 reg_list[i].valid = 0;
 316                 reg_list[i].arch_type = mips32_core_reg_arch_type;
 317                 reg_list[i].arch_info = &arch_info[i];
 318         }
 319
 320         return cache;
 321 }
 322
 323 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
 324 {
 325         target->arch_info = mips32;
 326         mips32->common_magic = MIPS32_COMMON_MAGIC;
 327
 328         /* has breakpoint/watchpint unit been scanned */
 329         mips32->bp_scanned = 0;
 330         mips32->data_break_list = NULL;
 331
 332         mips32->ejtag_info.tap = tap;
 333         mips32->read_core_reg = mips32_read_core_reg;
 334         mips32->write_core_reg = mips32_write_core_reg;
 335
 336         return ERROR_OK;
 337 }
 338
 339 int mips32_register_commands(struct command_context *cmd_ctx)
 340 {
 341         return ERROR_OK;
 342 }
 343
 344 int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 345 {
 346         /*TODO*/
 347         return ERROR_OK;
 348 }
 349
 350 int mips32_examine(struct target *target)
 351 {
 352         struct mips32_common *mips32 = target->arch_info;
 353
 354         if (!target_was_examined(target))
 355         {
 356                 target_set_examined(target);
 357
 358                 /* we will configure later */
 359                 mips32->bp_scanned = 0;
 360                 mips32->num_inst_bpoints = 0;
 361                 mips32->num_data_bpoints = 0;
 362                 mips32->num_inst_bpoints_avail = 0;
 363                 mips32->num_data_bpoints_avail = 0;
 364         }
 365
 366         return ERROR_OK;
 367 }
 368
 369 int mips32_configure_break_unit(struct target *target)
 370 {
 371         /* get pointers to arch-specific information */
 372         struct mips32_common *mips32 = target->arch_info;
 373         int retval;
 374         uint32_t dcr, bpinfo;
 375         int i;
 376
 377         if (mips32->bp_scanned)
 378                 return ERROR_OK;
 379
 380         /* get info about breakpoint support */
 381         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 382                 return retval;
 383
 384         if (dcr & (1 << 16))
 385         {
 386                 /* get number of inst breakpoints */
 387                 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
 388                         return retval;
 389
 390                 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
 391                 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
 392                 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
 393                 for (i = 0; i < mips32->num_inst_bpoints; i++)
 394                 {
 395                         mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
 396                 }
 397
 398                 /* clear IBIS reg */
 399                 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 400                         return retval;
 401         }
 402
 403         if (dcr & (1 << 17))
 404         {
 405                 /* get number of data breakpoints */
 406                 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
 407                         return retval;
 408
 409                 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
 410                 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
 411                 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
 412                 for (i = 0; i < mips32->num_data_bpoints; i++)
 413                 {
 414                         mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
 415                 }
 416
 417                 /* clear DBIS reg */
 418                 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
 419                         return retval;
 420         }
 421
 422         LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
 423
 424         mips32->bp_scanned = 1;
 425
 426         return ERROR_OK;
 427 }
 428
 429 int mips32_enable_interrupts(struct target *target, int enable)
 430 {
 431         int retval;
 432         int update = 0;
 433         uint32_t dcr;
 434
 435         /* read debug control register */
 436         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 437                 return retval;
 438
 439         if (enable)
 440         {
 441                 if (!(dcr & (1 << 4)))
 442                 {
 443                         /* enable interrupts */
 444                         dcr |= (1 << 4);
 445                         update = 1;
 446                 }
 447         }
 448         else
 449         {
 450                 if (dcr & (1 << 4))
 451                 {
 452                         /* disable interrupts */
 453                         dcr &= ~(1 << 4);
 454                         update = 1;
 455                 }
 456         }
 457
 458         if (update)
 459         {
 460                 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
 461                         return retval;
 462         }
 463
 464         return ERROR_OK;
 465 }