1 # The IMX31PDK eval board has a single IMX31 chip
2 source [find target/imx31.cfg]
3 source [find target/imx.cfg]
4 $_TARGETNAME configure -event reset-init { imx31pdk_init }
6 proc imx31pdk_init { } {
10 # This setup puts RAM at 0x80000000
13 mww 0x53F80000 0x074B0B7D
15 # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
16 #mww 0x53F80004 0xFF871D50
17 #mww 0x53F80010 0x00271C1B
19 # Start 16 bit NorFlash Initialization on CS0
20 mww 0xb8002000 0x0000CC03
21 mww 0xb8002004 0xa0330D01
22 mww 0xb8002008 0x00220800
24 # Configure CPLD on CS4
25 mww 0xb8002040 0x0000DCF6
26 mww 0xb8002044 0x444A4541
27 mww 0xb8002048 0x44443302
44 # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
68 # Initialization script for 32 bit DDR on MX31 ADS
69 mww 0xB8001010 0x00000004
70 mww 0xB8001004 0x006ac73a
71 mww 0xB8001000 0x92100000
72 mww 0x80000f00 0x12344321
73 mww 0xB8001000 0xa2100000
74 mww 0x80000000 0x12344321
75 mww 0x80000000 0x12344321
76 mww 0xB8001000 0xb2100000
79 mww 0xB8001000 0x82226080
80 mww 0x80000000 0xDEADBEEF
81 mww 0xB8001010 0x0000000c