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non-CFI flash code uses data from CFI structures. Make sure that timeouts are filled...
[openocd/openocdswd.git] / src / flash / nor / cfi.c
blob5a35aaef92d024efb4895a74858d8c7774dc7ef7
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "imp.h"
29 #include "cfi.h"
30 #include "non_cfi.h"
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34
35
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
38
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
41
42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
43 {
44 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
45 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
46 };
47
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param);
51 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param);
52 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param);
53
54 /* fixup after reading cmdset 0002 primary query table */
55 static const struct cfi_fixup cfi_0002_fixups[] = {
56 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
61 {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
63 {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
64 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
65 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
66 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
67 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
68 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
69 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
70 {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */
71 {0, 0, NULL, NULL}
72 };
73
74 /* fixup after reading cmdset 0001 primary query table */
75 static const struct cfi_fixup cfi_0001_fixups[] = {
76 {0, 0, NULL, NULL}
77 };
78
79 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
80 {
81 struct cfi_flash_bank *cfi_info = bank->driver_priv;
82 const struct cfi_fixup *f;
83
84 for (f = fixups; f->fixup; f++)
85 {
86 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
87 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
88 {
89 f->fixup(bank, f->param);
90 }
91 }
92 }
93
94 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
95 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
96 {
97 struct cfi_flash_bank *cfi_info = bank->driver_priv;
98
99 if (cfi_info->x16_as_x8) offset *= 2;
100
101 /* while the sector list isn't built, only accesses to sector 0 work */
102 if (sector == 0)
103 return bank->base + offset * bank->bus_width;
104 else
105 {
106 if (!bank->sectors)
107 {
108 LOG_ERROR("BUG: sector list not yet built");
109 exit(-1);
110 }
111 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
112 }
113 }
114
115 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
116 {
117 int i;
118
119 /* clear whole buffer, to ensure bits that exceed the bus_width
120 * are set to zero
121 */
122 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
123 cmd_buf[i] = 0;
124
125 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
126 {
127 for (i = bank->bus_width; i > 0; i--)
128 {
129 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
130 }
131 }
132 else
133 {
134 for (i = 1; i <= bank->bus_width; i++)
135 {
136 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
137 }
138 }
139 }
140
141 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
142 {
143 uint8_t command[CFI_MAX_BUS_WIDTH];
144
145 cfi_command(bank, cmd, command);
146 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
147 }
148
149 /* read unsigned 8-bit value from the bank
150 * flash banks are expected to be made of similar chips
151 * the query result should be the same for all
152 */
153 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
154 {
155 struct target *target = bank->target;
156 uint8_t data[CFI_MAX_BUS_WIDTH];
157
158 int retval;
159 retval = target_read_memory(target, flash_address(bank, sector, offset),
160 bank->bus_width, 1, data);
161 if (retval != ERROR_OK)
162 return retval;
163
164 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
165 *val = data[0];
166 else
167 *val = data[bank->bus_width - 1];
168
169 return ERROR_OK;
170 }
171
172 /* read unsigned 8-bit value from the bank
173 * in case of a bank made of multiple chips,
174 * the individual values are ORed
175 */
176 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
177 {
178 struct target *target = bank->target;
179 uint8_t data[CFI_MAX_BUS_WIDTH];
180 int i;
181
182 int retval;
183 retval = target_read_memory(target, flash_address(bank, sector, offset),
184 bank->bus_width, 1, data);
185 if (retval != ERROR_OK)
186 return retval;
187
188 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
189 {
190 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
191 data[0] |= data[i];
192
193 *val = data[0];
194 }
195 else
196 {
197 uint8_t value = 0;
198 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
199 value |= data[bank->bus_width - 1 - i];
200
201 *val = value;
202 }
203 return ERROR_OK;
204 }
205
206 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
207 {
208 struct target *target = bank->target;
209 struct cfi_flash_bank *cfi_info = bank->driver_priv;
210 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
211 int retval;
212
213 if (cfi_info->x16_as_x8)
214 {
215 uint8_t i;
216 for (i = 0;i < 2;i++)
217 {
218 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
219 bank->bus_width, 1, &data[i * bank->bus_width]);
220 if (retval != ERROR_OK)
221 return retval;
222 }
223 } else
224 {
225 retval = target_read_memory(target, flash_address(bank, sector, offset),
226 bank->bus_width, 2, data);
227 if (retval != ERROR_OK)
228 return retval;
229 }
230
231 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
232 *val = data[0] | data[bank->bus_width] << 8;
233 else
234 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
235
236 return ERROR_OK;
237 }
238
239 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
240 {
241 struct target *target = bank->target;
242 struct cfi_flash_bank *cfi_info = bank->driver_priv;
243 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
244 int retval;
245
246 if (cfi_info->x16_as_x8)
247 {
248 uint8_t i;
249 for (i = 0;i < 4;i++)
250 {
251 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
252 bank->bus_width, 1, &data[i * bank->bus_width]);
253 if (retval != ERROR_OK)
254 return retval;
255 }
256 }
257 else
258 {
259 retval = target_read_memory(target, flash_address(bank, sector, offset),
260 bank->bus_width, 4, data);
261 if (retval != ERROR_OK)
262 return retval;
263 }
264
265 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
266 *val = data[0] | data[bank->bus_width] << 8 |
267 data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
268 else
269 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
270 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
271
272 return ERROR_OK;
273 }
274
275 static int cfi_reset(struct flash_bank *bank)
276 {
277 struct cfi_flash_bank *cfi_info = bank->driver_priv;
278 int retval = ERROR_OK;
279
280 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
281 {
282 return retval;
283 }
284
285 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
286 {
287 return retval;
288 }
289
290 if (cfi_info->manufacturer == 0x20 &&
291 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
292 {
293 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
294 * so we send an extra 0xF0 reset to fix the bug */
295 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
296 {
297 return retval;
298 }
299 }
300
301 return retval;
302 }
303
304 static void cfi_intel_clear_status_register(struct flash_bank *bank)
305 {
306 struct target *target = bank->target;
307
308 if (target->state != TARGET_HALTED)
309 {
310 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
311 exit(-1);
312 }
313
314 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
315 }
316
317 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
318 {
319 uint8_t status;
320
321 int retval = ERROR_OK;
322
323 for (;;)
324 {
325 if (timeout-- < 0)
326 {
327 LOG_ERROR("timeout while waiting for WSM to become ready");
328 return ERROR_FAIL;
329 }
330
331 retval = cfi_get_u8(bank, 0, 0x0, &status);
332 if (retval != ERROR_OK)
333 return retval;
334
335 if (status & 0x80)
336 break;
337
338 alive_sleep(1);
339 }
340
341 /* mask out bit 0 (reserved) */
342 status = status & 0xfe;
343
344 LOG_DEBUG("status: 0x%x", status);
345
346 if (status != 0x80)
347 {
348 LOG_ERROR("status register: 0x%x", status);
349 if (status & 0x2)
350 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
351 if (status & 0x4)
352 LOG_ERROR("Program suspended");
353 if (status & 0x8)
354 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
355 if (status & 0x10)
356 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
357 if (status & 0x20)
358 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
359 if (status & 0x40)
360 LOG_ERROR("Block Erase Suspended");
361
362 cfi_intel_clear_status_register(bank);
363
364 retval = ERROR_FAIL;
365 }
366
367 *val = status;
368 return retval;
369 }
370
371 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
372 {
373 uint8_t status, oldstatus;
374 struct cfi_flash_bank *cfi_info = bank->driver_priv;
375 int retval;
376
377 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
378 if (retval != ERROR_OK)
379 return retval;
380
381 do {
382 retval = cfi_get_u8(bank, 0, 0x0, &status);
383
384 if (retval != ERROR_OK)
385 return retval;
386
387 if ((status ^ oldstatus) & 0x40) {
388 if (status & cfi_info->status_poll_mask & 0x20) {
389 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
390 if (retval != ERROR_OK)
391 return retval;
392 retval = cfi_get_u8(bank, 0, 0x0, &status);
393 if (retval != ERROR_OK)
394 return retval;
395 if ((status ^ oldstatus) & 0x40) {
396 LOG_ERROR("dq5 timeout, status: 0x%x", status);
397 return(ERROR_FLASH_OPERATION_FAILED);
398 } else {
399 LOG_DEBUG("status: 0x%x", status);
400 return(ERROR_OK);
401 }
402 }
403 } else { /* no toggle: finished, OK */
404 LOG_DEBUG("status: 0x%x", status);
405 return(ERROR_OK);
406 }
407
408 oldstatus = status;
409 alive_sleep(1);
410 } while (timeout-- > 0);
411
412 LOG_ERROR("timeout, status: 0x%x", status);
413
414 return(ERROR_FLASH_BUSY);
415 }
416
417 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
418 {
419 int retval;
420 struct cfi_flash_bank *cfi_info = bank->driver_priv;
421 struct cfi_intel_pri_ext *pri_ext;
422
423 if (cfi_info->pri_ext)
424 free(cfi_info->pri_ext);
425
426 pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
427 if (pri_ext == NULL)
428 {
429 LOG_ERROR("Out of memory");
430 return ERROR_FAIL;
431 }
432 cfi_info->pri_ext = pri_ext;
433
434 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
435 if (retval != ERROR_OK)
436 return retval;
437 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
438 if (retval != ERROR_OK)
439 return retval;
440 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
441 if (retval != ERROR_OK)
442 return retval;
443
444 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
445 {
446 if ((retval = cfi_reset(bank)) != ERROR_OK)
447 {
448 return retval;
449 }
450 LOG_ERROR("Could not read bank flash bank information");
451 return ERROR_FLASH_BANK_INVALID;
452 }
453
454 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
455 if (retval != ERROR_OK)
456 return retval;
457 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
458 if (retval != ERROR_OK)
459 return retval;
460
461 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
462 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
463
464 retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
465 if (retval != ERROR_OK)
466 return retval;
467 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
468 if (retval != ERROR_OK)
469 return retval;
470 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
471 if (retval != ERROR_OK)
472 return retval;
473
474 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
475 "0x%x, blk_status_reg_mask: 0x%x",
476 pri_ext->feature_support,
477 pri_ext->suspend_cmd_support,
478 pri_ext->blk_status_reg_mask);
479
480 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
481 if (retval != ERROR_OK)
482 return retval;
483 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
484 if (retval != ERROR_OK)
485 return retval;
486
487 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
488 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
489 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
490
491 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
492 if (retval != ERROR_OK)
493 return retval;
494 if (pri_ext->num_protection_fields != 1)
495 {
496 LOG_WARNING("expected one protection register field, but found %i",
497 pri_ext->num_protection_fields);
498 }
499
500 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
501 if (retval != ERROR_OK)
502 return retval;
503 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
504 if (retval != ERROR_OK)
505 return retval;
506 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
507 if (retval != ERROR_OK)
508 return retval;
509
510 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
511 "factory pre-programmed: %i, user programmable: %i",
512 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
513 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
514
515 return ERROR_OK;
516 }
517
518 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
519 {
520 int retval;
521 struct cfi_flash_bank *cfi_info = bank->driver_priv;
522 struct cfi_spansion_pri_ext *pri_ext;
523
524 if (cfi_info->pri_ext)
525 free(cfi_info->pri_ext);
526
527 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
528 if (pri_ext == NULL)
529 {
530 LOG_ERROR("Out of memory");
531 return ERROR_FAIL;
532 }
533 cfi_info->pri_ext = pri_ext;
534
535 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
536 if (retval != ERROR_OK)
537 return retval;
538 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
539 if (retval != ERROR_OK)
540 return retval;
541 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
542 if (retval != ERROR_OK)
543 return retval;
544
545 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
546 {
547 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
548 {
549 return retval;
550 }
551 LOG_ERROR("Could not read spansion bank information");
552 return ERROR_FLASH_BANK_INVALID;
553 }
554
555 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
556 if (retval != ERROR_OK)
557 return retval;
558 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
559 if (retval != ERROR_OK)
560 return retval;
561
562 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
563 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
564
565 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
566 if (retval != ERROR_OK)
567 return retval;
568 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
569 if (retval != ERROR_OK)
570 return retval;
571 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
572 if (retval != ERROR_OK)
573 return retval;
574 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
575 if (retval != ERROR_OK)
576 return retval;
577 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
578 if (retval != ERROR_OK)
579 return retval;
580 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
581 if (retval != ERROR_OK)
582 return retval;
583 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
584 if (retval != ERROR_OK)
585 return retval;
586 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
587 if (retval != ERROR_OK)
588 return retval;
589 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
590 if (retval != ERROR_OK)
591 return retval;
592 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
593 if (retval != ERROR_OK)
594 return retval;
595 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
596 if (retval != ERROR_OK)
597 return retval;
598
599 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
600 pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
601
602 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
603 "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
604 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
605
606 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
607
608
609 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
610 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
611 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
612
613 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
614
615 /* default values for implementation specific workarounds */
616 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
617 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
618 pri_ext->_reversed_geometry = 0;
619
620 return ERROR_OK;
621 }
622
623 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
624 {
625 int retval;
626 struct cfi_atmel_pri_ext atmel_pri_ext;
627 struct cfi_flash_bank *cfi_info = bank->driver_priv;
628 struct cfi_spansion_pri_ext *pri_ext;
629
630 if (cfi_info->pri_ext)
631 free(cfi_info->pri_ext);
632
633 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
634 if (pri_ext == NULL)
635 {
636 LOG_ERROR("Out of memory");
637 return ERROR_FAIL;
638 }
639
640 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
641 * but a different primary extended query table.
642 * We read the atmel table, and prepare a valid AMD/Spansion query table.
643 */
644
645 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
646
647 cfi_info->pri_ext = pri_ext;
648
649 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
650 if (retval != ERROR_OK)
651 return retval;
652 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
653 if (retval != ERROR_OK)
654 return retval;
655 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
656 if (retval != ERROR_OK)
657 return retval;
658
659 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
660 || (atmel_pri_ext.pri[2] != 'I'))
661 {
662 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
663 {
664 return retval;
665 }
666 LOG_ERROR("Could not read atmel bank information");
667 return ERROR_FLASH_BANK_INVALID;
668 }
669
670 pri_ext->pri[0] = atmel_pri_ext.pri[0];
671 pri_ext->pri[1] = atmel_pri_ext.pri[1];
672 pri_ext->pri[2] = atmel_pri_ext.pri[2];
673
674 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
675 if (retval != ERROR_OK)
676 return retval;
677 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
678 if (retval != ERROR_OK)
679 return retval;
680
681 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
682 atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
683 atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
684
685 pri_ext->major_version = atmel_pri_ext.major_version;
686 pri_ext->minor_version = atmel_pri_ext.minor_version;
687
688 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
689 if (retval != ERROR_OK)
690 return retval;
691 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
692 if (retval != ERROR_OK)
693 return retval;
694 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
695 if (retval != ERROR_OK)
696 return retval;
697 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
698 if (retval != ERROR_OK)
699 return retval;
700
701 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
702 atmel_pri_ext.features, atmel_pri_ext.bottom_boot,
703 atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
704
705 if (atmel_pri_ext.features & 0x02)
706 pri_ext->EraseSuspend = 2;
707
708 if (atmel_pri_ext.bottom_boot)
709 pri_ext->TopBottom = 2;
710 else
711 pri_ext->TopBottom = 3;
712
713 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
714 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
715
716 return ERROR_OK;
717 }
718
719 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
720 {
721 struct cfi_flash_bank *cfi_info = bank->driver_priv;
722
723 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
724 {
725 return cfi_read_atmel_pri_ext(bank);
726 }
727 else
728 {
729 return cfi_read_spansion_pri_ext(bank);
730 }
731 }
732
733 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
734 {
735 int printed;
736 struct cfi_flash_bank *cfi_info = bank->driver_priv;
737 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
738
739 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
740 buf += printed;
741 buf_size -= printed;
742
743 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
744 pri_ext->pri[1], pri_ext->pri[2],
745 pri_ext->major_version, pri_ext->minor_version);
746 buf += printed;
747 buf_size -= printed;
748
749 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
750 (pri_ext->SiliconRevision) >> 2,
751 (pri_ext->SiliconRevision) & 0x03);
752 buf += printed;
753 buf_size -= printed;
754
755 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
756 pri_ext->EraseSuspend,
757 pri_ext->BlkProt);
758 buf += printed;
759 buf_size -= printed;
760
761 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
762 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
763 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
764
765 return ERROR_OK;
766 }
767
768 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
769 {
770 int printed;
771 struct cfi_flash_bank *cfi_info = bank->driver_priv;
772 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
773
774 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
775 buf += printed;
776 buf_size -= printed;
777
778 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
779 pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
780 buf += printed;
781 buf_size -= printed;
782
783 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", "
784 "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
785 pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
786 buf += printed;
787 buf_size -= printed;
788
789 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
790 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
791 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
792 buf += printed;
793 buf_size -= printed;
794
795 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
796 "factory pre-programmed: %i, user programmable: %i\n",
797 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
798 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
799
800 return ERROR_OK;
801 }
802
803 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
804 */
805 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
806 {
807 struct cfi_flash_bank *cfi_info;
808
809 if (CMD_ARGC < 6)
810 {
811 LOG_WARNING("incomplete flash_bank cfi configuration");
812 return ERROR_FLASH_BANK_INVALID;
813 }
814
815 /* both widths must:
816 * - not exceed max value;
817 * - not be null;
818 * - be equal to a power of 2.
819 * bus must be wide enought to hold one chip */
820 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
821 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
822 || (bank->chip_width == 0)
823 || (bank->bus_width == 0)
824 || (bank->chip_width & (bank->chip_width - 1))
825 || (bank->bus_width & (bank->bus_width - 1))
826 || (bank->chip_width > bank->bus_width))
827 {
828 LOG_ERROR("chip and bus width have to specified in bytes");
829 return ERROR_FLASH_BANK_INVALID;
830 }
831
832 cfi_info = malloc(sizeof(struct cfi_flash_bank));
833 cfi_info->probed = 0;
834 cfi_info->erase_region_info = NULL;
835 cfi_info->pri_ext = NULL;
836 bank->driver_priv = cfi_info;
837
838 cfi_info->write_algorithm = NULL;
839
840 cfi_info->x16_as_x8 = 0;
841 cfi_info->jedec_probe = 0;
842 cfi_info->not_cfi = 0;
843
844 for (unsigned i = 6; i < CMD_ARGC; i++)
845 {
846 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
847 {
848 cfi_info->x16_as_x8 = 1;
849 }
850 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
851 {
852 cfi_info->jedec_probe = 1;
853 }
854 }
855
856 cfi_info->write_algorithm = NULL;
857
858 /* bank wasn't probed yet */
859 cfi_info->qry[0] = 0xff;
860
861 return ERROR_OK;
862 }
863
864 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
865 {
866 int retval;
867 struct cfi_flash_bank *cfi_info = bank->driver_priv;
868 int i;
869
870 cfi_intel_clear_status_register(bank);
871
872 for (i = first; i <= last; i++)
873 {
874 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
875 {
876 return retval;
877 }
878
879 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
880 {
881 return retval;
882 }
883
884 uint8_t status;
885 retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
886 if (retval != ERROR_OK)
887 return retval;
888
889 if (status == 0x80)
890 bank->sectors[i].is_erased = 1;
891 else
892 {
893 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
894 {
895 return retval;
896 }
897
898 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
899 return ERROR_FLASH_OPERATION_FAILED;
900 }
901 }
902
903 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
904 }
905
906 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
907 {
908 int retval;
909 struct cfi_flash_bank *cfi_info = bank->driver_priv;
910 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
911 int i;
912
913 for (i = first; i <= last; i++)
914 {
915 if ((retval = cfi_send_command(bank, 0xaa,
916 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
917 {
918 return retval;
919 }
920
921 if ((retval = cfi_send_command(bank, 0x55,
922 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
923 {
924 return retval;
925 }
926
927 if ((retval = cfi_send_command(bank, 0x80,
928 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
929 {
930 return retval;
931 }
932
933 if ((retval = cfi_send_command(bank, 0xaa,
934 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
935 {
936 return retval;
937 }
938
939 if ((retval = cfi_send_command(bank, 0x55,
940 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
941 {
942 return retval;
943 }
944
945 if ((retval = cfi_send_command(bank, 0x30,
946 flash_address(bank, i, 0x0))) != ERROR_OK)
947 {
948 return retval;
949 }
950
951 if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
952 {
953 bank->sectors[i].is_erased = 1;
954 }
955 else
956 {
957 if ((retval = cfi_send_command(bank, 0xf0,
958 flash_address(bank, 0, 0x0))) != ERROR_OK)
959 {
960 return retval;
961 }
962
963 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
964 PRIx32, i, bank->base);
965 return ERROR_FLASH_OPERATION_FAILED;
966 }
967 }
968
969 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
970 }
971
972 static int cfi_erase(struct flash_bank *bank, int first, int last)
973 {
974 struct cfi_flash_bank *cfi_info = bank->driver_priv;
975
976 if (bank->target->state != TARGET_HALTED)
977 {
978 LOG_ERROR("Target not halted");
979 return ERROR_TARGET_NOT_HALTED;
980 }
981
982 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
983 {
984 return ERROR_FLASH_SECTOR_INVALID;
985 }
986
987 if (cfi_info->qry[0] != 'Q')
988 return ERROR_FLASH_BANK_NOT_PROBED;
989
990 switch (cfi_info->pri_id)
991 {
992 case 1:
993 case 3:
994 return cfi_intel_erase(bank, first, last);
995 break;
996 case 2:
997 return cfi_spansion_erase(bank, first, last);
998 break;
999 default:
1000 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1001 break;
1002 }
1003
1004 return ERROR_OK;
1005 }
1006
1007 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
1008 {
1009 int retval;
1010 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1011 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
1012 int retry = 0;
1013 int i;
1014
1015 /* if the device supports neither legacy lock/unlock (bit 3) nor
1016 * instant individual block locking (bit 5).
1017 */
1018 if (!(pri_ext->feature_support & 0x28))
1019 {
1020 LOG_ERROR("lock/unlock not supported on flash");
1021 return ERROR_FLASH_OPERATION_FAILED;
1022 }
1023
1024 cfi_intel_clear_status_register(bank);
1025
1026 for (i = first; i <= last; i++)
1027 {
1028 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1029 {
1030 return retval;
1031 }
1032 if (set)
1033 {
1034 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1035 {
1036 return retval;
1037 }
1038 bank->sectors[i].is_protected = 1;
1039 }
1040 else
1041 {
1042 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1043 {
1044 return retval;
1045 }
1046 bank->sectors[i].is_protected = 0;
1047 }
1048
1049 /* instant individual block locking doesn't require reading of the status register */
1050 if (!(pri_ext->feature_support & 0x20))
1051 {
1052 /* Clear lock bits operation may take up to 1.4s */
1053 uint8_t status;
1054 retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1055 if (retval != ERROR_OK)
1056 return retval;
1057 }
1058 else
1059 {
1060 uint8_t block_status;
1061 /* read block lock bit, to verify status */
1062 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1063 {
1064 return retval;
1065 }
1066 retval = cfi_get_u8(bank, i, 0x2, &block_status);
1067 if (retval != ERROR_OK)
1068 return retval;
1069
1070 if ((block_status & 0x1) != set)
1071 {
1072 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1073 set, block_status);
1074 if ((retval = cfi_send_command(bank, 0x70,
1075 flash_address(bank, 0, 0x55))) != ERROR_OK)
1076 {
1077 return retval;
1078 }
1079 uint8_t status;
1080 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1081 if (retval != ERROR_OK)
1082 return retval;
1083
1084 if (retry > 10)
1085 return ERROR_FLASH_OPERATION_FAILED;
1086 else
1087 {
1088 i--;
1089 retry++;
1090 }
1091 }
1092 }
1093 }
1094
1095 /* if the device doesn't support individual block lock bits set/clear,
1096 * all blocks have been unlocked in parallel, so we set those that should be protected
1097 */
1098 if ((!set) && (!(pri_ext->feature_support & 0x20)))
1099 {
1100 /* FIX!!! this code path is broken!!!
1101 *
1102 * The correct approach is:
1103 *
1104 * 1. read out current protection status
1105 *
1106 * 2. override read out protection status w/unprotected.
1107 *
1108 * 3. re-protect what should be protected.
1109 *
1110 */
1111 for (i = 0; i < bank->num_sectors; i++)
1112 {
1113 if (bank->sectors[i].is_protected == 1)
1114 {
1115 cfi_intel_clear_status_register(bank);
1116
1117 if ((retval = cfi_send_command(bank, 0x60,
1118 flash_address(bank, i, 0x0))) != ERROR_OK)
1119 {
1120 return retval;
1121 }
1122
1123 if ((retval = cfi_send_command(bank, 0x01,
1124 flash_address(bank, i, 0x0))) != ERROR_OK)
1125 {
1126 return retval;
1127 }
1128
1129 uint8_t status;
1130 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1131 if (retval != ERROR_OK)
1132 return retval;
1133 }
1134 }
1135 }
1136
1137 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1138 }
1139
1140 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1141 {
1142 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1143
1144 if (bank->target->state != TARGET_HALTED)
1145 {
1146 LOG_ERROR("Target not halted");
1147 return ERROR_TARGET_NOT_HALTED;
1148 }
1149
1150 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1151 {
1152 LOG_ERROR("Invalid sector range");
1153 return ERROR_FLASH_SECTOR_INVALID;
1154 }
1155
1156 if (cfi_info->qry[0] != 'Q')
1157 return ERROR_FLASH_BANK_NOT_PROBED;
1158
1159 switch (cfi_info->pri_id)
1160 {
1161 case 1:
1162 case 3:
1163 return cfi_intel_protect(bank, set, first, last);
1164 break;
1165 default:
1166 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1167 return ERROR_FAIL;
1168 }
1169 }
1170
1171 /* Convert code image to target endian */
1172 /* FIXME create general block conversion fcts in target.c?) */
1173 static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
1174 const uint32_t *src, uint32_t count)
1175 {
1176 uint32_t i;
1177 for (i = 0; i< count; i++)
1178 {
1179 target_buffer_set_u32(target, dest, *src);
1180 dest += 4;
1181 src++;
1182 }
1183 }
1184
1185 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1186 {
1187 struct target *target = bank->target;
1188
1189 uint8_t buf[CFI_MAX_BUS_WIDTH];
1190 cfi_command(bank, cmd, buf);
1191 switch (bank->bus_width)
1192 {
1193 case 1 :
1194 return buf[0];
1195 break;
1196 case 2 :
1197 return target_buffer_get_u16(target, buf);
1198 break;
1199 case 4 :
1200 return target_buffer_get_u32(target, buf);
1201 break;
1202 default :
1203 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1204 return 0;
1205 }
1206 }
1207
1208 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
1209 uint32_t address, uint32_t count)
1210 {
1211 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1212 struct target *target = bank->target;
1213 struct reg_param reg_params[7];
1214 struct arm_algorithm armv4_5_info;
1215 struct working_area *source;
1216 uint32_t buffer_size = 32768;
1217 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1218
1219 /* algorithm register usage:
1220 * r0: source address (in RAM)
1221 * r1: target address (in Flash)
1222 * r2: count
1223 * r3: flash write command
1224 * r4: status byte (returned to host)
1225 * r5: busy test pattern
1226 * r6: error test pattern
1227 */
1228
1229 /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
1230 static const uint32_t word_32_code[] = {
1231 0xe4904004, /* loop: ldr r4, [r0], #4 */
1232 0xe5813000, /* str r3, [r1] */
1233 0xe5814000, /* str r4, [r1] */
1234 0xe5914000, /* busy: ldr r4, [r1] */
1235 0xe0047005, /* and r7, r4, r5 */
1236 0xe1570005, /* cmp r7, r5 */
1237 0x1afffffb, /* bne busy */
1238 0xe1140006, /* tst r4, r6 */
1239 0x1a000003, /* bne done */
1240 0xe2522001, /* subs r2, r2, #1 */
1241 0x0a000001, /* beq done */
1242 0xe2811004, /* add r1, r1 #4 */
1243 0xeafffff2, /* b loop */
1244 0xeafffffe /* done: b -2 */
1245 };
1246
1247 /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
1248 static const uint32_t word_16_code[] = {
1249 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1250 0xe1c130b0, /* strh r3, [r1] */
1251 0xe1c140b0, /* strh r4, [r1] */
1252 0xe1d140b0, /* busy ldrh r4, [r1] */
1253 0xe0047005, /* and r7, r4, r5 */
1254 0xe1570005, /* cmp r7, r5 */
1255 0x1afffffb, /* bne busy */
1256 0xe1140006, /* tst r4, r6 */
1257 0x1a000003, /* bne done */
1258 0xe2522001, /* subs r2, r2, #1 */
1259 0x0a000001, /* beq done */
1260 0xe2811002, /* add r1, r1 #2 */
1261 0xeafffff2, /* b loop */
1262 0xeafffffe /* done: b -2 */
1263 };
1264
1265 /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
1266 static const uint32_t word_8_code[] = {
1267 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1268 0xe5c13000, /* strb r3, [r1] */
1269 0xe5c14000, /* strb r4, [r1] */
1270 0xe5d14000, /* busy ldrb r4, [r1] */
1271 0xe0047005, /* and r7, r4, r5 */
1272 0xe1570005, /* cmp r7, r5 */
1273 0x1afffffb, /* bne busy */
1274 0xe1140006, /* tst r4, r6 */
1275 0x1a000003, /* bne done */
1276 0xe2522001, /* subs r2, r2, #1 */
1277 0x0a000001, /* beq done */
1278 0xe2811001, /* add r1, r1 #1 */
1279 0xeafffff2, /* b loop */
1280 0xeafffffe /* done: b -2 */
1281 };
1282 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1283 const uint32_t *target_code_src;
1284 uint32_t target_code_size;
1285 int retval = ERROR_OK;
1286
1287
1288 cfi_intel_clear_status_register(bank);
1289
1290 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1291 armv4_5_info.core_mode = ARM_MODE_SVC;
1292 armv4_5_info.core_state = ARM_STATE_ARM;
1293
1294 /* If we are setting up the write_algorith, we need target_code_src */
1295 /* if not we only need target_code_size. */
1296
1297 /* However, we don't want to create multiple code paths, so we */
1298 /* do the unecessary evaluation of target_code_src, which the */
1299 /* compiler will probably nicely optimize away if not needed */
1300
1301 /* prepare algorithm code for target endian */
1302 switch (bank->bus_width)
1303 {
1304 case 1 :
1305 target_code_src = word_8_code;
1306 target_code_size = sizeof(word_8_code);
1307 break;
1308 case 2 :
1309 target_code_src = word_16_code;
1310 target_code_size = sizeof(word_16_code);
1311 break;
1312 case 4 :
1313 target_code_src = word_32_code;
1314 target_code_size = sizeof(word_32_code);
1315 break;
1316 default:
1317 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1318 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1319 }
1320
1321 /* flash write code */
1322 if (!cfi_info->write_algorithm)
1323 {
1324 if (target_code_size > sizeof(target_code))
1325 {
1326 LOG_WARNING("Internal error - target code buffer to small. "
1327 "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1328 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1329 }
1330 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1331
1332 /* Get memory for block write handler */
1333 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1334 if (retval != ERROR_OK)
1335 {
1336 LOG_WARNING("No working area available, can't do block memory writes");
1337 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1338 };
1339
1340 /* write algorithm code to working area */
1341 retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1342 target_code_size, target_code);
1343 if (retval != ERROR_OK)
1344 {
1345 LOG_ERROR("Unable to write block write code to target");
1346 goto cleanup;
1347 }
1348 }
1349
1350 /* Get a workspace buffer for the data to flash starting with 32k size.
1351 Half size until buffer would be smaller 256 Bytem then fail back */
1352 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1353 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1354 {
1355 buffer_size /= 2;
1356 if (buffer_size <= 256)
1357 {
1358 LOG_WARNING("no large enough working area available, can't do block memory writes");
1359 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1360 goto cleanup;
1361 }
1362 };
1363
1364 /* setup algo registers */
1365 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1366 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1367 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1368 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1369 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1370 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1371 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1372
1373 /* prepare command and status register patterns */
1374 write_command_val = cfi_command_val(bank, 0x40);
1375 busy_pattern_val = cfi_command_val(bank, 0x80);
1376 error_pattern_val = cfi_command_val(bank, 0x7e);
1377
1378 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
1379 source->address, buffer_size);
1380
1381 /* Programming main loop */
1382 while (count > 0)
1383 {
1384 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1385 uint32_t wsm_error;
1386
1387 if ((retval = target_write_buffer(target, source->address,
1388 thisrun_count, buffer)) != ERROR_OK)
1389 {
1390 goto cleanup;
1391 }
1392
1393 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1394 buf_set_u32(reg_params[1].value, 0, 32, address);
1395 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1396
1397 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1398 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1399 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1400
1401 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1402
1403 /* Execute algorithm, assume breakpoint for last instruction */
1404 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1405 cfi_info->write_algorithm->address,
1406 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1407 10000, /* 10s should be enough for max. 32k of data */
1408 &armv4_5_info);
1409
1410 /* On failure try a fall back to direct word writes */
1411 if (retval != ERROR_OK)
1412 {
1413 cfi_intel_clear_status_register(bank);
1414 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1415 retval = ERROR_FLASH_OPERATION_FAILED;
1416 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1417 /* FIXME To allow fall back or recovery, we must save the actual status
1418 * somewhere, so that a higher level code can start recovery. */
1419 goto cleanup;
1420 }
1421
1422 /* Check return value from algo code */
1423 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1424 if (wsm_error)
1425 {
1426 /* read status register (outputs debug inforation) */
1427 uint8_t status;
1428 cfi_intel_wait_status_busy(bank, 100, &status);
1429 cfi_intel_clear_status_register(bank);
1430 retval = ERROR_FLASH_OPERATION_FAILED;
1431 goto cleanup;
1432 }
1433
1434 buffer += thisrun_count;
1435 address += thisrun_count;
1436 count -= thisrun_count;
1437
1438 keep_alive();
1439 }
1440
1441 /* free up resources */
1442 cleanup:
1443 if (source)
1444 target_free_working_area(target, source);
1445
1446 if (cfi_info->write_algorithm)
1447 {
1448 target_free_working_area(target, cfi_info->write_algorithm);
1449 cfi_info->write_algorithm = NULL;
1450 }
1451
1452 destroy_reg_param(&reg_params[0]);
1453 destroy_reg_param(&reg_params[1]);
1454 destroy_reg_param(&reg_params[2]);
1455 destroy_reg_param(&reg_params[3]);
1456 destroy_reg_param(&reg_params[4]);
1457 destroy_reg_param(&reg_params[5]);
1458 destroy_reg_param(&reg_params[6]);
1459
1460 return retval;
1461 }
1462
1463 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
1464 uint32_t address, uint32_t count)
1465 {
1466 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1467 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1468 struct target *target = bank->target;
1469 struct reg_param reg_params[10];
1470 struct arm_algorithm armv4_5_info;
1471 struct working_area *source;
1472 uint32_t buffer_size = 32768;
1473 uint32_t status;
1474 int retval = ERROR_OK;
1475
1476 /* input parameters - */
1477 /* R0 = source address */
1478 /* R1 = destination address */
1479 /* R2 = number of writes */
1480 /* R3 = flash write command */
1481 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1482 /* output parameters - */
1483 /* R5 = 0x80 ok 0x00 bad */
1484 /* temp registers - */
1485 /* R6 = value read from flash to test status */
1486 /* R7 = holding register */
1487 /* unlock registers - */
1488 /* R8 = unlock1_addr */
1489 /* R9 = unlock1_cmd */
1490 /* R10 = unlock2_addr */
1491 /* R11 = unlock2_cmd */
1492
1493 /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
1494 static const uint32_t word_32_code[] = {
1495 /* 00008100 <sp_32_code>: */
1496 0xe4905004, /* ldr r5, [r0], #4 */
1497 0xe5889000, /* str r9, [r8] */
1498 0xe58ab000, /* str r11, [r10] */
1499 0xe5883000, /* str r3, [r8] */
1500 0xe5815000, /* str r5, [r1] */
1501 0xe1a00000, /* nop */
1502 /* */
1503 /* 00008110 <sp_32_busy>: */
1504 0xe5916000, /* ldr r6, [r1] */
1505 0xe0257006, /* eor r7, r5, r6 */
1506 0xe0147007, /* ands r7, r4, r7 */
1507 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1508 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1509 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1510 0xe5916000, /* ldr r6, [r1] */
1511 0xe0257006, /* eor r7, r5, r6 */
1512 0xe0147007, /* ands r7, r4, r7 */
1513 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1514 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1515 0x1a000004, /* bne 8154 <sp_32_done> */
1516 /* */
1517 /* 00008140 <sp_32_cont>: */
1518 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1519 0x03a05080, /* moveq r5, #128 ; 0x80 */
1520 0x0a000001, /* beq 8154 <sp_32_done> */
1521 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1522 0xeaffffe8, /* b 8100 <sp_32_code> */
1523 /* */
1524 /* 00008154 <sp_32_done>: */
1525 0xeafffffe /* b 8154 <sp_32_done> */
1526 };
1527
1528 /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
1529 static const uint32_t word_16_code[] = {
1530 /* 00008158 <sp_16_code>: */
1531 0xe0d050b2, /* ldrh r5, [r0], #2 */
1532 0xe1c890b0, /* strh r9, [r8] */
1533 0xe1cab0b0, /* strh r11, [r10] */
1534 0xe1c830b0, /* strh r3, [r8] */
1535 0xe1c150b0, /* strh r5, [r1] */
1536 0xe1a00000, /* nop (mov r0,r0) */
1537 /* */
1538 /* 00008168 <sp_16_busy>: */
1539 0xe1d160b0, /* ldrh r6, [r1] */
1540 0xe0257006, /* eor r7, r5, r6 */
1541 0xe0147007, /* ands r7, r4, r7 */
1542 0x0a000007, /* beq 8198 <sp_16_cont> */
1543 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1544 0x0afffff9, /* beq 8168 <sp_16_busy> */
1545 0xe1d160b0, /* ldrh r6, [r1] */
1546 0xe0257006, /* eor r7, r5, r6 */
1547 0xe0147007, /* ands r7, r4, r7 */
1548 0x0a000001, /* beq 8198 <sp_16_cont> */
1549 0xe3a05000, /* mov r5, #0 ; 0x0 */
1550 0x1a000004, /* bne 81ac <sp_16_done> */
1551 /* */
1552 /* 00008198 <sp_16_cont>: */
1553 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1554 0x03a05080, /* moveq r5, #128 ; 0x80 */
1555 0x0a000001, /* beq 81ac <sp_16_done> */
1556 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1557 0xeaffffe8, /* b 8158 <sp_16_code> */
1558 /* */
1559 /* 000081ac <sp_16_done>: */
1560 0xeafffffe /* b 81ac <sp_16_done> */
1561 };
1562
1563 /* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
1564 static const uint32_t word_16_code_dq7only[] = {
1565 /* <sp_16_code>: */
1566 0xe0d050b2, /* ldrh r5, [r0], #2 */
1567 0xe1c890b0, /* strh r9, [r8] */
1568 0xe1cab0b0, /* strh r11, [r10] */
1569 0xe1c830b0, /* strh r3, [r8] */
1570 0xe1c150b0, /* strh r5, [r1] */
1571 0xe1a00000, /* nop (mov r0,r0) */
1572 /* */
1573 /* <sp_16_busy>: */
1574 0xe1d160b0, /* ldrh r6, [r1] */
1575 0xe0257006, /* eor r7, r5, r6 */
1576 0xe2177080, /* ands r7, #0x80 */
1577 0x1afffffb, /* bne 8168 <sp_16_busy> */
1578 /* */
1579 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1580 0x03a05080, /* moveq r5, #128 ; 0x80 */
1581 0x0a000001, /* beq 81ac <sp_16_done> */
1582 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1583 0xeafffff0, /* b 8158 <sp_16_code> */
1584 /* */
1585 /* 000081ac <sp_16_done>: */
1586 0xeafffffe /* b 81ac <sp_16_done> */
1587 };
1588
1589 /* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
1590 static const uint32_t word_8_code[] = {
1591 /* 000081b0 <sp_16_code_end>: */
1592 0xe4d05001, /* ldrb r5, [r0], #1 */
1593 0xe5c89000, /* strb r9, [r8] */
1594 0xe5cab000, /* strb r11, [r10] */
1595 0xe5c83000, /* strb r3, [r8] */
1596 0xe5c15000, /* strb r5, [r1] */
1597 0xe1a00000, /* nop (mov r0,r0) */
1598 /* */
1599 /* 000081c0 <sp_8_busy>: */
1600 0xe5d16000, /* ldrb r6, [r1] */
1601 0xe0257006, /* eor r7, r5, r6 */
1602 0xe0147007, /* ands r7, r4, r7 */
1603 0x0a000007, /* beq 81f0 <sp_8_cont> */
1604 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1605 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1606 0xe5d16000, /* ldrb r6, [r1] */
1607 0xe0257006, /* eor r7, r5, r6 */
1608 0xe0147007, /* ands r7, r4, r7 */
1609 0x0a000001, /* beq 81f0 <sp_8_cont> */
1610 0xe3a05000, /* mov r5, #0 ; 0x0 */
1611 0x1a000004, /* bne 8204 <sp_8_done> */
1612 /* */
1613 /* 000081f0 <sp_8_cont>: */
1614 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1615 0x03a05080, /* moveq r5, #128 ; 0x80 */
1616 0x0a000001, /* beq 8204 <sp_8_done> */
1617 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1618 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1619 /* */
1620 /* 00008204 <sp_8_done>: */
1621 0xeafffffe /* b 8204 <sp_8_done> */
1622 };
1623
1624 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1625 armv4_5_info.core_mode = ARM_MODE_SVC;
1626 armv4_5_info.core_state = ARM_STATE_ARM;
1627
1628 int target_code_size;
1629 const uint32_t *target_code_src;
1630
1631 switch (bank->bus_width)
1632 {
1633 case 1 :
1634 target_code_src = word_8_code;
1635 target_code_size = sizeof(word_8_code);
1636 break;
1637 case 2 :
1638 /* Check for DQ5 support */
1639 if( cfi_info->status_poll_mask & (1 << 5) )
1640 {
1641 target_code_src = word_16_code;
1642 target_code_size = sizeof(word_16_code);
1643 }
1644 else
1645 {
1646 /* No DQ5 support. Use DQ7 DATA# polling only. */
1647 target_code_src = word_16_code_dq7only;
1648 target_code_size = sizeof(word_16_code_dq7only);
1649 }
1650 break;
1651 case 4 :
1652 target_code_src = word_32_code;
1653 target_code_size = sizeof(word_32_code);
1654 break;
1655 default:
1656 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1657 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1658 }
1659
1660 /* flash write code */
1661 if (!cfi_info->write_algorithm)
1662 {
1663 uint8_t *target_code;
1664
1665 /* convert bus-width dependent algorithm code to correct endiannes */
1666 target_code = malloc(target_code_size);
1667 if (target_code == NULL)
1668 {
1669 LOG_ERROR("Out of memory");
1670 return ERROR_FAIL;
1671 }
1672 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1673
1674 /* allocate working area */
1675 retval = target_alloc_working_area(target, target_code_size,
1676 &cfi_info->write_algorithm);
1677 if (retval != ERROR_OK)
1678 {
1679 free(target_code);
1680 return retval;
1681 }
1682
1683 /* write algorithm code to working area */
1684 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1685 target_code_size, target_code)) != ERROR_OK)
1686 {
1687 free(target_code);
1688 return retval;
1689 }
1690
1691 free(target_code);
1692 }
1693 /* the following code still assumes target code is fixed 24*4 bytes */
1694
1695 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1696 {
1697 buffer_size /= 2;
1698 if (buffer_size <= 256)
1699 {
1700 /* if we already allocated the writing code, but failed to get a
1701 * buffer, free the algorithm */
1702 if (cfi_info->write_algorithm)
1703 target_free_working_area(target, cfi_info->write_algorithm);
1704
1705 LOG_WARNING("not enough working area available, can't do block memory writes");
1706 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1707 }
1708 };
1709
1710 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1711 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1712 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1713 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1714 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1715 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1716 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1717 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1718 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1719 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1720
1721 while (count > 0)
1722 {
1723 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1724
1725 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1726 if (retval != ERROR_OK)
1727 {
1728 break;
1729 }
1730
1731 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1732 buf_set_u32(reg_params[1].value, 0, 32, address);
1733 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1734 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1735 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1736 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1737 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1738 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1739 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1740
1741 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1742 cfi_info->write_algorithm->address,
1743 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1744 10000, &armv4_5_info);
1745 if (retval != ERROR_OK)
1746 {
1747 break;
1748 }
1749
1750 status = buf_get_u32(reg_params[5].value, 0, 32);
1751 if (status != 0x80)
1752 {
1753 LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1754 retval = ERROR_FLASH_OPERATION_FAILED;
1755 break;
1756 }
1757
1758 buffer += thisrun_count;
1759 address += thisrun_count;
1760 count -= thisrun_count;
1761 }
1762
1763 target_free_all_working_areas(target);
1764
1765 destroy_reg_param(&reg_params[0]);
1766 destroy_reg_param(&reg_params[1]);
1767 destroy_reg_param(&reg_params[2]);
1768 destroy_reg_param(&reg_params[3]);
1769 destroy_reg_param(&reg_params[4]);
1770 destroy_reg_param(&reg_params[5]);
1771 destroy_reg_param(&reg_params[6]);
1772 destroy_reg_param(&reg_params[7]);
1773 destroy_reg_param(&reg_params[8]);
1774 destroy_reg_param(&reg_params[9]);
1775
1776 return retval;
1777 }
1778
1779 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1780 {
1781 int retval;
1782 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1783 struct target *target = bank->target;
1784
1785 cfi_intel_clear_status_register(bank);
1786 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1787 {
1788 return retval;
1789 }
1790
1791 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1792 {
1793 return retval;
1794 }
1795
1796 uint8_t status;
1797 retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
1798 if (retval != 0x80)
1799 {
1800 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1801 {
1802 return retval;
1803 }
1804
1805 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
1806 bank->base, address);
1807 return ERROR_FLASH_OPERATION_FAILED;
1808 }
1809
1810 return ERROR_OK;
1811 }
1812
1813 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
1814 uint32_t wordcount, uint32_t address)
1815 {
1816 int retval;
1817 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1818 struct target *target = bank->target;
1819
1820 /* Calculate buffer size and boundary mask */
1821 /* buffersize is (buffer size per chip) * (number of chips) */
1822 /* bufferwsize is buffersize in words */
1823 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1824 uint32_t buffermask = buffersize-1;
1825 uint32_t bufferwsize = buffersize / bank->bus_width;
1826
1827 /* Check for valid range */
1828 if (address & buffermask)
1829 {
1830 LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
1831 " not aligned to 2^%d boundary",
1832 bank->base, address, cfi_info->max_buf_write_size);
1833 return ERROR_FLASH_OPERATION_FAILED;
1834 }
1835
1836 /* Check for valid size */
1837 if (wordcount > bufferwsize)
1838 {
1839 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
1840 wordcount, buffersize);
1841 return ERROR_FLASH_OPERATION_FAILED;
1842 }
1843
1844 /* Write to flash buffer */
1845 cfi_intel_clear_status_register(bank);
1846
1847 /* Initiate buffer operation _*/
1848 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1849 {
1850 return retval;
1851 }
1852 uint8_t status;
1853 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1854 if (retval != ERROR_OK)
1855 return retval;
1856 if (status != 0x80)
1857 {
1858 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1859 {
1860 return retval;
1861 }
1862
1863 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
1864 bank->base, address);
1865 return ERROR_FLASH_OPERATION_FAILED;
1866 }
1867
1868 /* Write buffer wordcount-1 and data words */
1869 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1870 {
1871 return retval;
1872 }
1873
1874 if ((retval = target_write_memory(target,
1875 address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1876 {
1877 return retval;
1878 }
1879
1880 /* Commit write operation */
1881 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1882 {
1883 return retval;
1884 }
1885
1886 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1887 if (retval != ERROR_OK)
1888 return retval;
1889
1890 if (status != 0x80)
1891 {
1892 if ((retval = cfi_send_command(bank, 0xff,
1893 flash_address(bank, 0, 0x0))) != ERROR_OK)
1894 {
1895 return retval;
1896 }
1897
1898 LOG_ERROR("Buffer write at base 0x%" PRIx32
1899 ", address 0x%" PRIx32 " failed.", bank->base, address);
1900 return ERROR_FLASH_OPERATION_FAILED;
1901 }
1902
1903 return ERROR_OK;
1904 }
1905
1906 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1907 {
1908 int retval;
1909 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1910 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1911 struct target *target = bank->target;
1912
1913 if ((retval = cfi_send_command(bank, 0xaa,
1914 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1915 {
1916 return retval;
1917 }
1918
1919 if ((retval = cfi_send_command(bank, 0x55,
1920 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1921 {
1922 return retval;
1923 }
1924
1925 if ((retval = cfi_send_command(bank, 0xa0,
1926 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1927 {
1928 return retval;
1929 }
1930
1931 if ((retval = target_write_memory(target,
1932 address, bank->bus_width, 1, word)) != ERROR_OK)
1933 {
1934 return retval;
1935 }
1936
1937 if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK)
1938 {
1939 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1940 {
1941 return retval;
1942 }
1943
1944 LOG_ERROR("couldn't write word at base 0x%" PRIx32
1945 ", address 0x%" PRIx32 , bank->base, address);
1946 return ERROR_FLASH_OPERATION_FAILED;
1947 }
1948
1949 return ERROR_OK;
1950 }
1951
1952 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
1953 uint32_t wordcount, uint32_t address)
1954 {
1955 int retval;
1956 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1957 struct target *target = bank->target;
1958 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1959
1960 /* Calculate buffer size and boundary mask */
1961 /* buffersize is (buffer size per chip) * (number of chips) */
1962 /* bufferwsize is buffersize in words */
1963 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1964 uint32_t buffermask = buffersize-1;
1965 uint32_t bufferwsize = buffersize / bank->bus_width;
1966
1967 /* Check for valid range */
1968 if (address & buffermask)
1969 {
1970 LOG_ERROR("Write address at base 0x%" PRIx32
1971 ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
1972 bank->base, address, cfi_info->max_buf_write_size);
1973 return ERROR_FLASH_OPERATION_FAILED;
1974 }
1975
1976 /* Check for valid size */
1977 if (wordcount > bufferwsize)
1978 {
1979 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
1980 PRId32, wordcount, buffersize);
1981 return ERROR_FLASH_OPERATION_FAILED;
1982 }
1983
1984 /* Unlock */
1985 if ((retval = cfi_send_command(bank, 0xaa,
1986 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1987 {
1988 return retval;
1989 }
1990
1991 if ((retval = cfi_send_command(bank, 0x55,
1992 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1993 {
1994 return retval;
1995 }
1996
1997 /* Buffer load command */
1998 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1999 {
2000 return retval;
2001 }
2002
2003 /* Write buffer wordcount-1 and data words */
2004 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
2005 {
2006 return retval;
2007 }
2008
2009 if ((retval = target_write_memory(target,
2010 address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
2011 {
2012 return retval;
2013 }
2014
2015 /* Commit write operation */
2016 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
2017 {
2018 return retval;
2019 }
2020
2021 if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK)
2022 {
2023 if ((retval = cfi_send_command(bank, 0xf0,
2024 flash_address(bank, 0, 0x0))) != ERROR_OK)
2025 {
2026 return retval;
2027 }
2028
2029 LOG_ERROR("couldn't write block at base 0x%" PRIx32
2030 ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address, bufferwsize);
2031 return ERROR_FLASH_OPERATION_FAILED;
2032 }
2033
2034 return ERROR_OK;
2035 }
2036
2037 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2038 {
2039 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2040
2041 switch (cfi_info->pri_id)
2042 {
2043 case 1:
2044 case 3:
2045 return cfi_intel_write_word(bank, word, address);
2046 break;
2047 case 2:
2048 return cfi_spansion_write_word(bank, word, address);
2049 break;
2050 default:
2051 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2052 break;
2053 }
2054
2055 return ERROR_FLASH_OPERATION_FAILED;
2056 }
2057
2058 static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
2059 uint32_t wordcount, uint32_t address)
2060 {
2061 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2062
2063 if (cfi_info->buf_write_timeout_typ == 0)
2064 {
2065 /* buffer writes are not supported */
2066 LOG_DEBUG("Buffer Writes Not Supported");
2067 return ERROR_FLASH_OPER_UNSUPPORTED;
2068 }
2069
2070 switch (cfi_info->pri_id)
2071 {
2072 case 1:
2073 case 3:
2074 return cfi_intel_write_words(bank, word, wordcount, address);
2075 break;
2076 case 2:
2077 return cfi_spansion_write_words(bank, word, wordcount, address);
2078 break;
2079 default:
2080 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2081 break;
2082 }
2083
2084 return ERROR_FLASH_OPERATION_FAILED;
2085 }
2086
2087 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2088 {
2089 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2090 struct target *target = bank->target;
2091 uint32_t address = bank->base + offset;
2092 uint32_t read_p;
2093 int align; /* number of unaligned bytes */
2094 uint8_t current_word[CFI_MAX_BUS_WIDTH];
2095 int i;
2096 int retval;
2097
2098 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2099 (int)count, (unsigned)offset);
2100
2101 if (bank->target->state != TARGET_HALTED)
2102 {
2103 LOG_ERROR("Target not halted");
2104 return ERROR_TARGET_NOT_HALTED;
2105 }
2106
2107 if (offset + count > bank->size)
2108 return ERROR_FLASH_DST_OUT_OF_BANK;
2109
2110 if (cfi_info->qry[0] != 'Q')
2111 return ERROR_FLASH_BANK_NOT_PROBED;
2112
2113 /* start at the first byte of the first word (bus_width size) */
2114 read_p = address & ~(bank->bus_width - 1);
2115 if ((align = address - read_p) != 0)
2116 {
2117 LOG_INFO("Fixup %d unaligned read head bytes", align);
2118
2119 /* read a complete word from flash */
2120 if ((retval = target_read_memory(target, read_p,
2121 bank->bus_width, 1, current_word)) != ERROR_OK)
2122 return retval;
2123
2124 /* take only bytes we need */
2125 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2126 *buffer++ = current_word[i];
2127
2128 read_p += bank->bus_width;
2129 }
2130
2131 align = count / bank->bus_width;
2132 if (align)
2133 {
2134 if ((retval = target_read_memory(target, read_p,
2135 bank->bus_width, align, buffer)) != ERROR_OK)
2136 return retval;
2137
2138 read_p += align * bank->bus_width;
2139 buffer += align * bank->bus_width;
2140 count -= align * bank->bus_width;
2141 }
2142
2143 if (count)
2144 {
2145 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2146
2147 /* read a complete word from flash */
2148 if ((retval = target_read_memory(target, read_p,
2149 bank->bus_width, 1, current_word)) != ERROR_OK)
2150 return retval;
2151
2152 /* take only bytes we need */
2153 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2154 *buffer++ = current_word[i];
2155 }
2156
2157 return ERROR_OK;
2158 }
2159
2160 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2161 {
2162 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2163 struct target *target = bank->target;
2164 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2165 uint32_t write_p;
2166 int align; /* number of unaligned bytes */
2167 int blk_count; /* number of bus_width bytes for block copy */
2168 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
2169 int i;
2170 int retval;
2171
2172 if (bank->target->state != TARGET_HALTED)
2173 {
2174 LOG_ERROR("Target not halted");
2175 return ERROR_TARGET_NOT_HALTED;
2176 }
2177
2178 if (offset + count > bank->size)
2179 return ERROR_FLASH_DST_OUT_OF_BANK;
2180
2181 if (cfi_info->qry[0] != 'Q')
2182 return ERROR_FLASH_BANK_NOT_PROBED;
2183
2184 /* start at the first byte of the first word (bus_width size) */
2185 write_p = address & ~(bank->bus_width - 1);
2186 if ((align = address - write_p) != 0)
2187 {
2188 LOG_INFO("Fixup %d unaligned head bytes", align);
2189
2190 /* read a complete word from flash */
2191 if ((retval = target_read_memory(target, write_p,
2192 bank->bus_width, 1, current_word)) != ERROR_OK)
2193 return retval;
2194
2195 /* replace only bytes that must be written */
2196 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2197 current_word[i] = *buffer++;
2198
2199 retval = cfi_write_word(bank, current_word, write_p);
2200 if (retval != ERROR_OK)
2201 return retval;
2202 write_p += bank->bus_width;
2203 }
2204
2205 /* handle blocks of bus_size aligned bytes */
2206 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2207 switch (cfi_info->pri_id)
2208 {
2209 /* try block writes (fails without working area) */
2210 case 1:
2211 case 3:
2212 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2213 break;
2214 case 2:
2215 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2216 break;
2217 default:
2218 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2219 retval = ERROR_FLASH_OPERATION_FAILED;
2220 break;
2221 }
2222 if (retval == ERROR_OK)
2223 {
2224 /* Increment pointers and decrease count on succesful block write */
2225 buffer += blk_count;
2226 write_p += blk_count;
2227 count -= blk_count;
2228 }
2229 else
2230 {
2231 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2232 {
2233 /* Calculate buffer size and boundary mask */
2234 /* buffersize is (buffer size per chip) * (number of chips) */
2235 /* bufferwsize is buffersize in words */
2236 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2237 uint32_t buffermask = buffersize-1;
2238 uint32_t bufferwsize = buffersize / bank->bus_width;
2239
2240 /* fall back to memory writes */
2241 while (count >= (uint32_t)bank->bus_width)
2242 {
2243 int fallback;
2244 if ((write_p & 0xff) == 0)
2245 {
2246 LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
2247 PRIx32 " bytes remaining", write_p, count);
2248 }
2249 fallback = 1;
2250 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2251 {
2252 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2253 if (retval == ERROR_OK)
2254 {
2255 buffer += buffersize;
2256 write_p += buffersize;
2257 count -= buffersize;
2258 fallback = 0;
2259 }
2260 else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
2261 return retval;
2262 }
2263 /* try the slow way? */
2264 if (fallback)
2265 {
2266 for (i = 0; i < bank->bus_width; i++)
2267 current_word[i] = *buffer++;
2268
2269 retval = cfi_write_word(bank, current_word, write_p);
2270 if (retval != ERROR_OK)
2271 return retval;
2272
2273 write_p += bank->bus_width;
2274 count -= bank->bus_width;
2275 }
2276 }
2277 }
2278 else
2279 return retval;
2280 }
2281
2282 /* return to read array mode, so we can read from flash again for padding */
2283 if ((retval = cfi_reset(bank)) != ERROR_OK)
2284 {
2285 return retval;
2286 }
2287
2288 /* handle unaligned tail bytes */
2289 if (count > 0)
2290 {
2291 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2292
2293 /* read a complete word from flash */
2294 if ((retval = target_read_memory(target, write_p,
2295 bank->bus_width, 1, current_word)) != ERROR_OK)
2296 return retval;
2297
2298 /* replace only bytes that must be written */
2299 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2300 current_word[i] = *buffer++;
2301
2302 retval = cfi_write_word(bank, current_word, write_p);
2303 if (retval != ERROR_OK)
2304 return retval;
2305 }
2306
2307 /* return to read array mode */
2308 return cfi_reset(bank);
2309 }
2310
2311 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2312 {
2313 (void) param;
2314 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2315 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2316
2317 pri_ext->_reversed_geometry = 1;
2318 }
2319
2320 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2321 {
2322 int i;
2323 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2324 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2325 (void) param;
2326
2327 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2328 {
2329 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2330
2331 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2332 {
2333 int j = (cfi_info->num_erase_regions - 1) - i;
2334 uint32_t swap;
2335
2336 swap = cfi_info->erase_region_info[i];
2337 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2338 cfi_info->erase_region_info[j] = swap;
2339 }
2340 }
2341 }
2342
2343 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2344 {
2345 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2346 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2347 struct cfi_unlock_addresses *unlock_addresses = param;
2348
2349 pri_ext->_unlock1 = unlock_addresses->unlock1;
2350 pri_ext->_unlock2 = unlock_addresses->unlock2;
2351 }
2352
2353
2354 static int cfi_query_string(struct flash_bank *bank, int address)
2355 {
2356 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2357 int retval;
2358
2359 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2360 {
2361 return retval;
2362 }
2363
2364 retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2365 if (retval != ERROR_OK)
2366 return retval;
2367 retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2368 if (retval != ERROR_OK)
2369 return retval;
2370 retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2371 if (retval != ERROR_OK)
2372 return retval;
2373
2374 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2375 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2376
2377 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2378 {
2379 if ((retval = cfi_reset(bank)) != ERROR_OK)
2380 {
2381 return retval;
2382 }
2383 LOG_ERROR("Could not probe bank: no QRY");
2384 return ERROR_FLASH_BANK_INVALID;
2385 }
2386
2387 return ERROR_OK;
2388 }
2389
2390 static int cfi_probe(struct flash_bank *bank)
2391 {
2392 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2393 struct target *target = bank->target;
2394 int num_sectors = 0;
2395 int i;
2396 int sector = 0;
2397 uint32_t unlock1 = 0x555;
2398 uint32_t unlock2 = 0x2aa;
2399 int retval;
2400 uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2401
2402 if (bank->target->state != TARGET_HALTED)
2403 {
2404 LOG_ERROR("Target not halted");
2405 return ERROR_TARGET_NOT_HALTED;
2406 }
2407
2408 cfi_info->probed = 0;
2409 if (bank->sectors)
2410 {
2411 free(bank->sectors);
2412 bank->sectors = NULL;
2413 }
2414 if(cfi_info->erase_region_info)
2415 {
2416 free(cfi_info->erase_region_info);
2417 cfi_info->erase_region_info = NULL;
2418 }
2419
2420 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2421 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2422 */
2423 if (cfi_info->jedec_probe)
2424 {
2425 unlock1 = 0x5555;
2426 unlock2 = 0x2aaa;
2427 }
2428
2429 /* switch to read identifier codes mode ("AUTOSELECT") */
2430 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2431 {
2432 return retval;
2433 }
2434 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2435 {
2436 return retval;
2437 }
2438 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2439 {
2440 return retval;
2441 }
2442
2443 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00),
2444 bank->bus_width, 1, value_buf0)) != ERROR_OK)
2445 {
2446 return retval;
2447 }
2448 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01),
2449 bank->bus_width, 1, value_buf1)) != ERROR_OK)
2450 {
2451 return retval;
2452 }
2453 switch (bank->chip_width) {
2454 case 1:
2455 cfi_info->manufacturer = *value_buf0;
2456 cfi_info->device_id = *value_buf1;
2457 break;
2458 case 2:
2459 cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2460 cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2461 break;
2462 case 4:
2463 cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2464 cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2465 break;
2466 default:
2467 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2468 return ERROR_FLASH_OPERATION_FAILED;
2469 }
2470
2471 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2472 cfi_info->manufacturer, cfi_info->device_id);
2473 /* switch back to read array mode */
2474 if ((retval = cfi_reset(bank)) != ERROR_OK)
2475 {
2476 return retval;
2477 }
2478
2479 /* check device/manufacturer ID for known non-CFI flashes. */
2480 cfi_fixup_non_cfi(bank);
2481
2482 /* query only if this is a CFI compatible flash,
2483 * otherwise the relevant info has already been filled in
2484 */
2485 if (cfi_info->not_cfi == 0)
2486 {
2487 /* enter CFI query mode
2488 * according to JEDEC Standard No. 68.01,
2489 * a single bus sequence with address = 0x55, data = 0x98 should put
2490 * the device into CFI query mode.
2491 *
2492 * SST flashes clearly violate this, and we will consider them incompatbile for now
2493 */
2494
2495 retval = cfi_query_string(bank, 0x55);
2496 if (retval != ERROR_OK)
2497 {
2498 /*
2499 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2500 * be harmless enough:
2501 *
2502 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2503 */
2504 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2505 retval = cfi_query_string(bank, 0x555);
2506 }
2507 if (retval != ERROR_OK)
2508 return retval;
2509
2510 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2511 if (retval != ERROR_OK)
2512 return retval;
2513 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2514 if (retval != ERROR_OK)
2515 return retval;
2516 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2517 if (retval != ERROR_OK)
2518 return retval;
2519 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2520 if (retval != ERROR_OK)
2521 return retval;
2522
2523 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2524 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
2525 cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
2526 cfi_info->alt_id, cfi_info->alt_addr);
2527
2528 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2529 if (retval != ERROR_OK)
2530 return retval;
2531 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2532 if (retval != ERROR_OK)
2533 return retval;
2534 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2535 if (retval != ERROR_OK)
2536 return retval;
2537 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2538 if (retval != ERROR_OK)
2539 return retval;
2540
2541 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2542 if (retval != ERROR_OK)
2543 return retval;
2544 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2545 if (retval != ERROR_OK)
2546 return retval;
2547 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2548 if (retval != ERROR_OK)
2549 return retval;
2550 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2551 if (retval != ERROR_OK)
2552 return retval;
2553 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2554 if (retval != ERROR_OK)
2555 return retval;
2556 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2557 if (retval != ERROR_OK)
2558 return retval;
2559 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2560 if (retval != ERROR_OK)
2561 return retval;
2562 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2563 if (retval != ERROR_OK)
2564 return retval;
2565
2566 uint8_t data;
2567 retval = cfi_query_u8(bank, 0, 0x27, &data);
2568 if (retval != ERROR_OK)
2569 return retval;
2570 cfi_info->dev_size = 1 << data;
2571
2572 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2573 if (retval != ERROR_OK)
2574 return retval;
2575 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2576 if (retval != ERROR_OK)
2577 return retval;
2578 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2579 if (retval != ERROR_OK)
2580 return retval;
2581
2582 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
2583 cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2584
2585 if (cfi_info->num_erase_regions)
2586 {
2587 cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2588 * cfi_info->num_erase_regions);
2589 for (i = 0; i < cfi_info->num_erase_regions; i++)
2590 {
2591 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2592 if (retval != ERROR_OK)
2593 return retval;
2594 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "", i,
2595 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2596 (cfi_info->erase_region_info[i] >> 16) * 256);
2597 }
2598 }
2599 else
2600 {
2601 cfi_info->erase_region_info = NULL;
2602 }
2603
2604 /* We need to read the primary algorithm extended query table before calculating
2605 * the sector layout to be able to apply fixups
2606 */
2607 switch (cfi_info->pri_id)
2608 {
2609 /* Intel command set (standard and extended) */
2610 case 0x0001:
2611 case 0x0003:
2612 cfi_read_intel_pri_ext(bank);
2613 break;
2614 /* AMD/Spansion, Atmel, ... command set */
2615 case 0x0002:
2616 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2617 cfi_read_0002_pri_ext(bank);
2618 break;
2619 default:
2620 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2621 break;
2622 }
2623
2624 /* return to read array mode
2625 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2626 */
2627 if ((retval = cfi_reset(bank)) != ERROR_OK)
2628 {
2629 return retval;
2630 }
2631 } /* end CFI case */
2632
2633 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2634 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2635 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2636 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2637 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2638
2639 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2640 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2641 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2642 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2643
2644 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2645 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2646 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2647 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2648 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2649 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2650
2651 /* convert timeouts to real values in ms */
2652 cfi_info->word_write_timeout = DIV_ROUND_UP((1L << cfi_info->word_write_timeout_typ) *
2653 (1L << cfi_info->word_write_timeout_max), 1000);
2654 cfi_info->buf_write_timeout = DIV_ROUND_UP((1L << cfi_info->buf_write_timeout_typ) *
2655 (1L << cfi_info->buf_write_timeout_max), 1000);
2656 cfi_info->block_erase_timeout = (1L << cfi_info->block_erase_timeout_typ) *
2657 (1L << cfi_info->block_erase_timeout_max);
2658 cfi_info->chip_erase_timeout = (1L << cfi_info->chip_erase_timeout_typ) *
2659 (1L << cfi_info->chip_erase_timeout_max);
2660
2661 LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
2662 "block erase timeout: %u ms, chip erase timeout: %u ms",
2663 cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
2664 cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
2665
2666 /* apply fixups depending on the primary command set */
2667 switch (cfi_info->pri_id)
2668 {
2669 /* Intel command set (standard and extended) */
2670 case 0x0001:
2671 case 0x0003:
2672 cfi_fixup(bank, cfi_0001_fixups);
2673 break;
2674 /* AMD/Spansion, Atmel, ... command set */
2675 case 0x0002:
2676 cfi_fixup(bank, cfi_0002_fixups);
2677 break;
2678 default:
2679 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2680 break;
2681 }
2682
2683 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2684 {
2685 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
2686 " size flash was found", bank->size, cfi_info->dev_size);
2687 }
2688
2689 if (cfi_info->num_erase_regions == 0)
2690 {
2691 /* a device might have only one erase block, spanning the whole device */
2692 bank->num_sectors = 1;
2693 bank->sectors = malloc(sizeof(struct flash_sector));
2694
2695 bank->sectors[sector].offset = 0x0;
2696 bank->sectors[sector].size = bank->size;
2697 bank->sectors[sector].is_erased = -1;
2698 bank->sectors[sector].is_protected = -1;
2699 }
2700 else
2701 {
2702 uint32_t offset = 0;
2703
2704 for (i = 0; i < cfi_info->num_erase_regions; i++)
2705 {
2706 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2707 }
2708
2709 bank->num_sectors = num_sectors;
2710 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2711
2712 for (i = 0; i < cfi_info->num_erase_regions; i++)
2713 {
2714 uint32_t j;
2715 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2716 {
2717 bank->sectors[sector].offset = offset;
2718 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256)
2719 * bank->bus_width / bank->chip_width;
2720 offset += bank->sectors[sector].size;
2721 bank->sectors[sector].is_erased = -1;
2722 bank->sectors[sector].is_protected = -1;
2723 sector++;
2724 }
2725 }
2726 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2727 {
2728 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2729 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2730 }
2731 }
2732
2733 cfi_info->probed = 1;
2734
2735 return ERROR_OK;
2736 }
2737
2738 static int cfi_auto_probe(struct flash_bank *bank)
2739 {
2740 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2741 if (cfi_info->probed)
2742 return ERROR_OK;
2743 return cfi_probe(bank);
2744 }
2745
2746 static int cfi_intel_protect_check(struct flash_bank *bank)
2747 {
2748 int retval;
2749 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2750 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2751 int i;
2752
2753 /* check if block lock bits are supported on this device */
2754 if (!(pri_ext->blk_status_reg_mask & 0x1))
2755 return ERROR_FLASH_OPERATION_FAILED;
2756
2757 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2758 {
2759 return retval;
2760 }
2761
2762 for (i = 0; i < bank->num_sectors; i++)
2763 {
2764 uint8_t block_status;
2765 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2766 if (retval != ERROR_OK)
2767 return retval;
2768
2769 if (block_status & 1)
2770 bank->sectors[i].is_protected = 1;
2771 else
2772 bank->sectors[i].is_protected = 0;
2773 }
2774
2775 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2776 }
2777
2778 static int cfi_spansion_protect_check(struct flash_bank *bank)
2779 {
2780 int retval;
2781 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2782 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2783 int i;
2784
2785 if ((retval = cfi_send_command(bank, 0xaa,
2786 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2787 {
2788 return retval;
2789 }
2790
2791 if ((retval = cfi_send_command(bank, 0x55,
2792 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2793 {
2794 return retval;
2795 }
2796
2797 if ((retval = cfi_send_command(bank, 0x90,
2798 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2799 {
2800 return retval;
2801 }
2802
2803 for (i = 0; i < bank->num_sectors; i++)
2804 {
2805 uint8_t block_status;
2806 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2807 if (retval != ERROR_OK)
2808 return retval;
2809
2810 if (block_status & 1)
2811 bank->sectors[i].is_protected = 1;
2812 else
2813 bank->sectors[i].is_protected = 0;
2814 }
2815
2816 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2817 }
2818
2819 static int cfi_protect_check(struct flash_bank *bank)
2820 {
2821 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2822
2823 if (bank->target->state != TARGET_HALTED)
2824 {
2825 LOG_ERROR("Target not halted");
2826 return ERROR_TARGET_NOT_HALTED;
2827 }
2828
2829 if (cfi_info->qry[0] != 'Q')
2830 return ERROR_FLASH_BANK_NOT_PROBED;
2831
2832 switch (cfi_info->pri_id)
2833 {
2834 case 1:
2835 case 3:
2836 return cfi_intel_protect_check(bank);
2837 break;
2838 case 2:
2839 return cfi_spansion_protect_check(bank);
2840 break;
2841 default:
2842 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2843 break;
2844 }
2845
2846 return ERROR_OK;
2847 }
2848
2849 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2850 {
2851 int printed;
2852 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2853
2854 if (cfi_info->qry[0] == 0xff)
2855 {
2856 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2857 return ERROR_OK;
2858 }
2859
2860 if (cfi_info->not_cfi == 0)
2861 printed = snprintf(buf, buf_size, "\nCFI flash: ");
2862 else
2863 printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
2864 buf += printed;
2865 buf_size -= printed;
2866
2867 printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
2868 cfi_info->manufacturer, cfi_info->device_id);
2869 buf += printed;
2870 buf_size -= printed;
2871
2872 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2873 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2874 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
2875 cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2876 buf += printed;
2877 buf_size -= printed;
2878
2879 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
2880 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2881 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2882 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2883 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2884 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2885 buf += printed;
2886 buf_size -= printed;
2887
2888 printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
2889 "typ. buf write timeout: %u us, "
2890 "typ. block erase timeout: %u ms, "
2891 "typ. chip erase timeout: %u ms\n",
2892 1 << cfi_info->word_write_timeout_typ,
2893 1 << cfi_info->buf_write_timeout_typ,
2894 1 << cfi_info->block_erase_timeout_typ,
2895 1 << cfi_info->chip_erase_timeout_typ);
2896 buf += printed;
2897 buf_size -= printed;
2898
2899 printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
2900 "max. buf write timeout: %u us, max. "
2901 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
2902 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2903 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2904 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2905 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2906 buf += printed;
2907 buf_size -= printed;
2908
2909 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
2910 "max buffer write size: 0x%x\n",
2911 cfi_info->dev_size,
2912 cfi_info->interface_desc,
2913 1 << cfi_info->max_buf_write_size);
2914 buf += printed;
2915 buf_size -= printed;
2916
2917 switch (cfi_info->pri_id)
2918 {
2919 case 1:
2920 case 3:
2921 cfi_intel_info(bank, buf, buf_size);
2922 break;
2923 case 2:
2924 cfi_spansion_info(bank, buf, buf_size);
2925 break;
2926 default:
2927 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2928 break;
2929 }
2930
2931 return ERROR_OK;
2932 }
2933
2934 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param)
2935 {
2936 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2937
2938 /* disable write buffer for M29W128G */
2939 cfi_info->buf_write_timeout_typ = 0;
2940 }
2941
2942 struct flash_driver cfi_flash = {
2943 .name = "cfi",
2944 .flash_bank_command = cfi_flash_bank_command,
2945 .erase = cfi_erase,
2946 .protect = cfi_protect,
2947 .write = cfi_write,
2948 .read = cfi_read,
2949 .probe = cfi_probe,
2950 .auto_probe = cfi_auto_probe,
2951 /* FIXME: access flash at bus_width size */
2952 .erase_check = default_flash_blank_check,
2953 .protect_check = cfi_protect_check,
2954 .info = get_cfi_info,
2955 };
OpenOCD fork with SWD works