src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 /**
  27  * @file
  28  * This defines formats and data structures used to talk to ADIv5 entities.
  29  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  30  * resources accessed through a MEM-AP.
  31  */
  32
  33 #include "arm_jtag.h"
  34
  35 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
  36  * is no longer JTAG-specific
  37  */
  38 #define JTAG_DP_DPACC           0xA
  39 #define JTAG_DP_APACC           0xB
  40
  41 /* three-bit ACK values for SWD access (sent LSB first) */
  42 #define SWD_ACK_OK              0x4
  43 #define SWD_ACK_WAIT            0x2
  44 #define SWD_ACK_FAULT           0x1
  45
  46 #define DPAP_WRITE              0
  47 #define DPAP_READ               1
  48
  49 /* A[3:0] for DP registers; A[1:0] are always zero.
  50  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  51  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  52  * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  53  */
  54 #define DP_IDCODE               0               /* SWD: read */
  55 #define DP_ABORT                0               /* SWD: write */
  56 #define DP_CTRL_STAT            0x4             /* r/w */
  57 #define DP_WCR                  0x4             /* SWD: r/w (mux CTRLSEL) */
  58 #define DP_RESEND               0x8             /* SWD: read */
  59 #define DP_SELECT               0x8             /* JTAG: r/w; SWD: write */
  60 #define DP_RDBUFF               0xC             /* read-only */
  61
  62 #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8))        /* 1..4 clocks */
  63 #define WCR_TO_PRESCALE(wcr) (7 & ((wcr)))              /* impl defined */
  64
  65 /* Fields of the DP's AP ABORT register */
  66 #define DAPABORT                (1 << 0)
  67 #define STKCMPCLR               (1 << 1)        /* SWD-only */
  68 #define STKERRCLR               (1 << 2)        /* SWD-only */
  69 #define WDERRCLR                (1 << 3)        /* SWD-only */
  70 #define ORUNERRCLR              (1 << 4)        /* SWD-only */
  71
  72 /* Fields of the DP's CTRL/STAT register */
  73 #define CORUNDETECT             (1 << 0)
  74 #define SSTICKYORUN             (1 << 1)
  75 /* 3:2 - transaction mode (e.g. pushed compare) */
  76 #define SSTICKYCMP              (1 << 4)
  77 #define SSTICKYERR              (1 << 5)
  78 #define READOK                  (1 << 6)        /* SWD-only */
  79 #define WDATAERR                (1 << 7)        /* SWD-only */
  80 /* 11:8 - mask lanes for pushed compare or verify ops */
  81 /* 21:12 - transaction counter */
  82 #define CDBGRSTREQ              (1 << 26)
  83 #define CDBGRSTACK              (1 << 27)
  84 #define CDBGPWRUPREQ    (1 << 28)
  85 #define CDBGPWRUPACK    (1 << 29)
  86 #define CSYSPWRUPREQ    (1 << 30)
  87 #define CSYSPWRUPACK    (1 << 31)
  88
  89 /* MEM-AP register addresses */
  90 /* TODO: rename as MEM_AP_REG_* */
  91 #define AP_REG_CSW              0x00
  92 #define AP_REG_TAR              0x04
  93 #define AP_REG_DRW              0x0C
  94 #define AP_REG_BD0              0x10
  95 #define AP_REG_BD1              0x14
  96 #define AP_REG_BD2              0x18
  97 #define AP_REG_BD3              0x1C
  98 #define AP_REG_CFG              0xF4            /* big endian? */
  99 #define AP_REG_BASE             0xF8
 100
 101 /* Generic AP register address */
 102 #define AP_REG_IDR              0xFC
 103
 104 /* Fields of the MEM-AP's CSW register */
 105 #define CSW_8BIT                0
 106 #define CSW_16BIT               1
 107 #define CSW_32BIT               2
 108 #define CSW_ADDRINC_MASK        (3 << 4)
 109 #define CSW_ADDRINC_OFF         0
 110 #define CSW_ADDRINC_SINGLE      (1 << 4)
 111 #define CSW_ADDRINC_PACKED      (2 << 4)
 112 #define CSW_DEVICE_EN           (1 << 6)
 113 #define CSW_TRIN_PROG           (1 << 7)
 114 #define CSW_SPIDEN                      (1 << 23)
 115 /* 30:24 - implementation-defined! */
 116 #define CSW_HPROT                       (1 << 25)               /* ? */
 117 #define CSW_MASTER_DEBUG        (1 << 29)               /* ? */
 118 #define CSW_DBGSWENABLE         (1 << 31)
 119
 120 /**
 121  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 122  * A DAP has two types of component:  one Debug Port (DP), which is a
 123  * transport agent; and at least one Access Port (AP), controlling
 124  * resource access.  Most common is a MEM-AP, for memory access.
 125  *
 126  * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
 127  * Accordingly, this interface is responsible for hiding the transport
 128  * differences so upper layer code can largely ignore them.
 129  *
 130  * When the chip is implemented with JTAG-DP or SW-DP, the transport is
 131  * fixed as JTAG or SWD, respectively.  Chips incorporating SWJ-DP permit
 132  * a choice made at board design time (by only using the SWD pins), or
 133  * as part of setting up a debug session (if all the dual-role JTAG/SWD
 134  * signals are available).
 135  */
 136 struct adiv5_dap
 137 {
 138         const struct dap_ops *ops;
 139
 140         struct arm_jtag *jtag_info;
 141         /* Control config */
 142         uint32_t dp_ctrl_stat;
 143
 144         /**
 145          * Cache for DP_SELECT bits identifying the current AP.  A DAP may
 146          * connect to multiple APs, such as one MEM-AP for general access,
 147          * another reserved for accessing debug modules, and a JTAG-DP.
 148          * "-1" indicates no cached value.
 149          */
 150         uint32_t apsel;
 151
 152         /**
 153          * Cache for DP_SELECT bits identifying the current four-word AP
 154          * register bank.  This caches AP register addresss bits 7:4; JTAG
 155          * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
 156          * "-1" indicates no cached value.
 157          */
 158         uint32_t ap_bank_value;
 159
 160         /**
 161          * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
 162          * configure an access mode, such as autoincrementing AP_REG_TAR during
 163          * word access.  "-1" indicates no cached value.
 164          */
 165         uint32_t ap_csw_value;
 166
 167         /**
 168          * Cache for (MEM-AP) AP_REG_TAR register value This is written to
 169          * configure the address being read or written
 170          * "-1" indicates no cached value.
 171          */
 172         uint32_t ap_tar_value;
 173
 174         /* information about current pending SWjDP-AHBAP transaction */
 175         uint8_t  ack;
 176
 177         /**
 178          * Configures how many extra tck clocks are added after starting a
 179          * MEM-AP access before we try to read its status (and/or result).
 180          */
 181         uint32_t        memaccess_tck;
 182         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 183         uint32_t tar_autoincr_block;
 184 };
 185
 186 /**
 187  * Transport-neutral representation of queued DAP transactions, supporting
 188  * both JTAG and SWD transports.  All submitted transactions are logically
 189  * queued, until the queue is executed by run().  Some implementations might
 190  * execute transactions as soon as they're submitted, but no status is made
 191  * availablue until run().
 192  */
 193 struct dap_ops {
 194         /** If the DAP transport isn't SWD, it must be JTAG.  Upper level
 195          * code may need to care about the difference in some cases.
 196          */
 197         bool    is_swd;
 198
 199         /** Reads the DAP's IDCODe register. */
 200         int (*queue_idcode_read)(struct adiv5_dap *dap,
 201                         uint8_t *ack, uint32_t *data);
 202
 203         /** DP register read. */
 204         int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
 205                         uint32_t *data);
 206         /** DP register write. */
 207         int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 208                         uint32_t data);
 209
 210         /** AP register read. */
 211         int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
 212                         uint32_t *data);
 213         /** AP register write. */
 214         int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 215                         uint32_t data);
 216         /** AP operation abort. */
 217         int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
 218
 219         /** Executes all queued DAP operations. */
 220         int (*run)(struct adiv5_dap *dap);
 221 };
 222
 223 /**
 224  * Queue an IDCODE register read.  This is primarily useful for SWD
 225  * transports, where it is required as part of link initialization.
 226  * (For JTAG, this register is read as part of scan chain setup.)
 227  *
 228  * @param dap The DAP used for reading.
 229  * @param ack Pointer to where transaction status will be stored.
 230  * @param data Pointer saying where to store the IDCODE value.
 231  *
 232  * @return ERROR_OK for success, else a fault code.
 233  */
 234 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
 235                 uint8_t *ack, uint32_t *data)
 236 {
 237         assert(dap->ops != NULL);
 238         return dap->ops->queue_idcode_read(dap, ack, data);
 239 }
 240
 241 /**
 242  * Queue a DP register read.
 243  * Note that not all DP registers are readable; also, that JTAG and SWD
 244  * have slight differences in DP register support.
 245  *
 246  * @param dap The DAP used for reading.
 247  * @param reg The two-bit number of the DP register being read.
 248  * @param data Pointer saying where to store the register's value
 249  *      (in host endianness).
 250  *
 251  * @return ERROR_OK for success, else a fault code.
 252  */
 253 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
 254                 unsigned reg, uint32_t *data)
 255 {
 256         assert(dap->ops != NULL);
 257         return dap->ops->queue_dp_read(dap, reg, data);
 258 }
 259
 260 /**
 261  * Queue a DP register write.
 262  * Note that not all DP registers are writable; also, that JTAG and SWD
 263  * have slight differences in DP register support.
 264  *
 265  * @param dap The DAP used for writing.
 266  * @param reg The two-bit number of the DP register being written.
 267  * @param data Value being written (host endianness)
 268  *
 269  * @return ERROR_OK for success, else a fault code.
 270  */
 271 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
 272                 unsigned reg, uint32_t data)
 273 {
 274         assert(dap->ops != NULL);
 275         return dap->ops->queue_dp_write(dap, reg, data);
 276 }
 277
 278 /**
 279  * Queue an AP register read.
 280  *
 281  * @param dap The DAP used for reading.
 282  * @param reg The number of the AP register being read.
 283  * @param data Pointer saying where to store the register's value
 284  *      (in host endianness).
 285  *
 286  * @return ERROR_OK for success, else a fault code.
 287  */
 288 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
 289                 unsigned reg, uint32_t *data)
 290 {
 291         assert(dap->ops != NULL);
 292         return dap->ops->queue_ap_read(dap, reg, data);
 293 }
 294
 295 /**
 296  * Queue an AP register write.
 297  *
 298  * @param dap The DAP used for writing.
 299  * @param reg The number of the AP register being written.
 300  * @param data Value being written (host endianness)
 301  *
 302  * @return ERROR_OK for success, else a fault code.
 303  */
 304 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
 305                 unsigned reg, uint32_t data)
 306 {
 307         assert(dap->ops != NULL);
 308         return dap->ops->queue_ap_write(dap, reg, data);
 309 }
 310
 311 /**
 312  * Queue an AP abort operation.  The current AP transaction is aborted,
 313  * including any update of the transaction counter.  The AP is left in
 314  * an unknown state (so it must be re-initialized).  For use only after
 315  * the AP has reported WAIT status for an extended period.
 316  *
 317  * @param dap The DAP used for writing.
 318  * @param ack Pointer to where transaction status will be stored.
 319  *
 320  * @return ERROR_OK for success, else a fault code.
 321  */
 322 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 323 {
 324         assert(dap->ops != NULL);
 325         return dap->ops->queue_ap_abort(dap, ack);
 326 }
 327
 328 /**
 329  * Perform all queued DAP operations, and clear any errors posted in the
 330  * CTRL_STAT register when they are done.  Note that if more than one AP
 331  * operation will be queued, one of the first operations in the queue
 332  * should probably enable CORUNDETECT in the CTRL/STAT register.
 333  *
 334  * @param dap The DAP used.
 335  *
 336  * @return ERROR_OK for success, else a fault code.
 337  */
 338 static inline int dap_run(struct adiv5_dap *dap)
 339 {
 340         assert(dap->ops != NULL);
 341         return dap->ops->run(dap);
 342 }
 343
 344 /** Accessor for currently selected DAP-AP number (0..255) */
 345 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 346 {
 347         return (uint8_t)(swjdp ->apsel >> 24);
 348 }
 349
 350 /* AP selection applies to future AP transactions */
 351 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel);
 352
 353 /* Queued AP transactions */
 354 int dap_setup_accessport(struct adiv5_dap *swjdp,
 355                 uint32_t csw, uint32_t tar);
 356
 357 /* Queued MEM-AP memory mapped single word transfers */
 358 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
 359 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
 360
 361 /* Synchronous MEM-AP memory mapped single word transfers */
 362 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
 363                 uint32_t address, uint32_t *value);
 364 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
 365                 uint32_t address, uint32_t value);
 366
 367 /* MEM-AP memory mapped bus block transfers */
 368 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
 369                 uint8_t *buffer, int count, uint32_t address);
 370 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
 371                 uint8_t *buffer, int count, uint32_t address);
 372 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
 373                 uint8_t *buffer, int count, uint32_t address);
 374
 375 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
 376                 uint8_t *buffer, int count, uint32_t address);
 377 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
 378                 uint8_t *buffer, int count, uint32_t address);
 379 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
 380                 uint8_t *buffer, int count, uint32_t address);
 381
 382
 383
 384 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 385 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 386                 uint32_t address, uint32_t *value);
 387 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 388                 uint32_t address, uint32_t value);
 389
 390 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
 391 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 392                 uint32_t address, uint32_t *value);
 393 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 394                 uint32_t address, uint32_t value);
 395
 396 /* MEM-AP memory mapped bus block transfers with selection of ap */
 397 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t apsel,
 398                 uint8_t *buffer, int count, uint32_t address);
 399 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t apsel,
 400                 uint8_t *buffer, int count, uint32_t address);
 401 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 402                 uint8_t *buffer, int count, uint32_t address);
 403
 404 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t apsel,
 405                 uint8_t *buffer, int count, uint32_t address);
 406 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t apsel,
 407                 uint8_t *buffer, int count, uint32_t address);
 408 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t apsel,
 409                 uint8_t *buffer, int count, uint32_t address);
 410
 411
 412
 413 /* Initialisation of the debug system, power domains and registers */
 414 int ahbap_debugport_init(struct adiv5_dap *swjdp);
 415
 416 /* Probe the AP for ROM Table location */
 417 int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
 418                         uint32_t *dbgbase, uint32_t *apid);
 419
 420 /* Lookup CoreSight component */
 421 int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
 422                         uint32_t dbgbase, uint8_t type, uint32_t *addr);
 423
 424 struct target;
 425
 426 /* Put debug link into SWD mode */
 427 int dap_to_swd(struct target *target);
 428
 429 /* Put debug link into JTAG mode */
 430 int dap_to_jtag(struct target *target);
 431
 432 extern const struct command_registration dap_command_handlers[];
 433
 434 #endif