at91: add chip register definition and generic init support
[openocd/openocdswd.git] / tcl / chip / atmel / at91 / rtt.tcl
blob8be6a56b02a2ad47f96442091c525d001aee4fe4
2 set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
3 set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
4 set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
5 set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
6 global RTTC_RTMR
7 global RTTC_RTAR
8 global RTTC_RTVR
9 global RTTC_RTSR
11 proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
12 set rtpres [expr $VAL & 0x0ffff]
13 global BIT16 BIT17
14 if { $rtpres == 0 } {
15 set rtpres 65536;
17 global AT91C_SLOWOSC_FREQ
18 # Nasty hack, make this a float by tacking a .0 on the end
19 # otherwise, jim makes the value an integer
20 set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
21 echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
22 if { $VAL & $BIT16 } {
23 echo "\tBit16 -> Alarm IRQ Enabled"
24 } else {
25 echo "\tBit16 -> Alarm IRQ Disabled"
27 if { $VAL & $BIT17 } {
28 echo "\tBit17 -> RTC Inc IRQ Enabled"
29 } else {
30 echo "\tBit17 -> RTC Inc IRQ Disabled"
32 # Bit 18 is write only.
35 proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
36 global BIT0 BIT1
37 if { $VAL & $BIT0 } {
38 echo "\tBit0 -> ALARM PENDING"
39 } else {
40 echo "\tBit0 -> alarm not pending"
42 if { $VAL & $BIT1 } {
43 echo "\tBit0 -> RTINC PENDING"
44 } else {
45 echo "\tBit0 -> rtinc not pending"
49 proc show_RTTC { } {
51 show_mmr32_reg RTTC_RTMR
52 show_mmr32_reg RTTC_RTAR
53 show_mmr32_reg RTTC_RTVR
54 show_mmr32_reg RTTC_RTSR