NOR/CFI: simplify bufferwsize computation
[openocd/openocdswd.git] / src / flash / nor / cfi.c
blobf2ea947ad3d61b32ae610c8d722650f6c5a57acd
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
27 #include "imp.h"
28 #include "cfi.h"
29 #include "non_cfi.h"
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
35 #define CFI_MAX_BUS_WIDTH 4
36 #define CFI_MAX_CHIP_WIDTH 4
38 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
39 #define CFI_MAX_INTEL_CODESIZE 256
41 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
43 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
44 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
47 /* CFI fixups foward declarations */
48 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
49 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
50 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
52 /* fixup after reading cmdset 0002 primary query table */
53 static const struct cfi_fixup cfi_0002_fixups[] = {
54 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
55 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
60 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
62 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
63 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
64 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
65 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
66 {0, 0, NULL, NULL}
69 /* fixup after reading cmdset 0001 primary query table */
70 static const struct cfi_fixup cfi_0001_fixups[] = {
71 {0, 0, NULL, NULL}
74 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
76 struct cfi_flash_bank *cfi_info = bank->driver_priv;
77 const struct cfi_fixup *f;
79 for (f = fixups; f->fixup; f++)
81 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
82 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
84 f->fixup(bank, f->param);
89 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
90 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
92 struct cfi_flash_bank *cfi_info = bank->driver_priv;
94 if (cfi_info->x16_as_x8) offset *= 2;
96 /* while the sector list isn't built, only accesses to sector 0 work */
97 if (sector == 0)
98 return bank->base + offset * bank->bus_width;
99 else
101 if (!bank->sectors)
103 LOG_ERROR("BUG: sector list not yet built");
104 exit(-1);
106 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
110 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
112 int i;
114 /* clear whole buffer, to ensure bits that exceed the bus_width
115 * are set to zero
117 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
118 cmd_buf[i] = 0;
120 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
122 for (i = bank->bus_width; i > 0; i--)
124 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
127 else
129 for (i = 1; i <= bank->bus_width; i++)
131 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
136 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
138 uint8_t command[CFI_MAX_BUS_WIDTH];
140 cfi_command(bank, cmd, command);
141 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
144 /* read unsigned 8-bit value from the bank
145 * flash banks are expected to be made of similar chips
146 * the query result should be the same for all
148 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
150 struct target *target = bank->target;
151 uint8_t data[CFI_MAX_BUS_WIDTH];
153 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
155 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
156 return data[0];
157 else
158 return data[bank->bus_width - 1];
161 /* read unsigned 8-bit value from the bank
162 * in case of a bank made of multiple chips,
163 * the individual values are ORed
165 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
167 struct target *target = bank->target;
168 uint8_t data[CFI_MAX_BUS_WIDTH];
169 int i;
171 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
173 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
175 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
176 data[0] |= data[i];
178 return data[0];
180 else
182 uint8_t value = 0;
183 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
184 value |= data[bank->bus_width - 1 - i];
186 return value;
190 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
192 struct target *target = bank->target;
193 struct cfi_flash_bank *cfi_info = bank->driver_priv;
194 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
196 if (cfi_info->x16_as_x8)
198 uint8_t i;
199 for (i = 0;i < 2;i++)
200 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
201 &data[i*bank->bus_width]);
203 else
204 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
206 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
207 return data[0] | data[bank->bus_width] << 8;
208 else
209 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
212 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
214 struct target *target = bank->target;
215 struct cfi_flash_bank *cfi_info = bank->driver_priv;
216 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
218 if (cfi_info->x16_as_x8)
220 uint8_t i;
221 for (i = 0;i < 4;i++)
222 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
223 &data[i*bank->bus_width]);
225 else
226 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
228 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
229 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
230 else
231 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
232 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
235 static int cfi_reset(struct flash_bank *bank)
237 struct cfi_flash_bank *cfi_info = bank->driver_priv;
238 int retval = ERROR_OK;
240 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
242 return retval;
245 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
247 return retval;
250 if (cfi_info->manufacturer == 0x20 &&
251 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
253 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
254 * so we send an extra 0xF0 reset to fix the bug */
255 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
257 return retval;
261 return retval;
264 static void cfi_intel_clear_status_register(struct flash_bank *bank)
266 struct target *target = bank->target;
268 if (target->state != TARGET_HALTED)
270 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
271 exit(-1);
274 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
277 static uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
279 uint8_t status;
281 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
283 LOG_DEBUG("status: 0x%x", status);
284 alive_sleep(1);
287 /* mask out bit 0 (reserved) */
288 status = status & 0xfe;
290 LOG_DEBUG("status: 0x%x", status);
292 if ((status & 0x80) != 0x80)
294 LOG_ERROR("timeout while waiting for WSM to become ready");
296 else if (status != 0x80)
298 LOG_ERROR("status register: 0x%x", status);
299 if (status & 0x2)
300 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
301 if (status & 0x4)
302 LOG_ERROR("Program suspended");
303 if (status & 0x8)
304 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
305 if (status & 0x10)
306 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
307 if (status & 0x20)
308 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
309 if (status & 0x40)
310 LOG_ERROR("Block Erase Suspended");
312 cfi_intel_clear_status_register(bank);
315 return status;
318 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
320 uint8_t status, oldstatus;
321 struct cfi_flash_bank *cfi_info = bank->driver_priv;
323 oldstatus = cfi_get_u8(bank, 0, 0x0);
325 do {
326 status = cfi_get_u8(bank, 0, 0x0);
327 if ((status ^ oldstatus) & 0x40) {
328 if (status & cfi_info->status_poll_mask & 0x20) {
329 oldstatus = cfi_get_u8(bank, 0, 0x0);
330 status = cfi_get_u8(bank, 0, 0x0);
331 if ((status ^ oldstatus) & 0x40) {
332 LOG_ERROR("dq5 timeout, status: 0x%x", status);
333 return(ERROR_FLASH_OPERATION_FAILED);
334 } else {
335 LOG_DEBUG("status: 0x%x", status);
336 return(ERROR_OK);
339 } else { /* no toggle: finished, OK */
340 LOG_DEBUG("status: 0x%x", status);
341 return(ERROR_OK);
344 oldstatus = status;
345 alive_sleep(1);
346 } while (timeout-- > 0);
348 LOG_ERROR("timeout, status: 0x%x", status);
350 return(ERROR_FLASH_BUSY);
353 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
355 int retval;
356 struct cfi_flash_bank *cfi_info = bank->driver_priv;
357 struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
359 cfi_info->pri_ext = pri_ext;
361 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
362 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
363 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
365 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
367 if ((retval = cfi_reset(bank)) != ERROR_OK)
369 return retval;
371 LOG_ERROR("Could not read bank flash bank information");
372 return ERROR_FLASH_BANK_INVALID;
375 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
376 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
378 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
380 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
381 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
382 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
384 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
385 pri_ext->feature_support,
386 pri_ext->suspend_cmd_support,
387 pri_ext->blk_status_reg_mask);
389 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
390 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
392 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
393 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
394 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
396 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
397 if (pri_ext->num_protection_fields != 1)
399 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
402 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
403 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
404 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
406 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
408 return ERROR_OK;
411 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
413 int retval;
414 struct cfi_flash_bank *cfi_info = bank->driver_priv;
415 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
417 cfi_info->pri_ext = pri_ext;
419 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
420 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
421 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
423 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
425 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
427 return retval;
429 LOG_ERROR("Could not read spansion bank information");
430 return ERROR_FLASH_BANK_INVALID;
433 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
434 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
436 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
438 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
439 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
440 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
441 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
442 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
443 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
444 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
445 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
446 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
447 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
448 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
450 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
451 pri_ext->EraseSuspend, pri_ext->BlkProt);
453 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
454 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
456 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
459 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
460 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
461 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
463 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
465 /* default values for implementation specific workarounds */
466 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
467 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
468 pri_ext->_reversed_geometry = 0;
470 return ERROR_OK;
473 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
475 int retval;
476 struct cfi_atmel_pri_ext atmel_pri_ext;
477 struct cfi_flash_bank *cfi_info = bank->driver_priv;
478 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
480 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
481 * but a different primary extended query table.
482 * We read the atmel table, and prepare a valid AMD/Spansion query table.
485 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
487 cfi_info->pri_ext = pri_ext;
489 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
490 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
491 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
493 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
495 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
497 return retval;
499 LOG_ERROR("Could not read atmel bank information");
500 return ERROR_FLASH_BANK_INVALID;
503 pri_ext->pri[0] = atmel_pri_ext.pri[0];
504 pri_ext->pri[1] = atmel_pri_ext.pri[1];
505 pri_ext->pri[2] = atmel_pri_ext.pri[2];
507 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
508 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
510 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
512 pri_ext->major_version = atmel_pri_ext.major_version;
513 pri_ext->minor_version = atmel_pri_ext.minor_version;
515 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
516 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
517 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
518 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
520 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
521 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
523 if (atmel_pri_ext.features & 0x02)
524 pri_ext->EraseSuspend = 2;
526 if (atmel_pri_ext.bottom_boot)
527 pri_ext->TopBottom = 2;
528 else
529 pri_ext->TopBottom = 3;
531 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
532 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
534 return ERROR_OK;
537 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
539 struct cfi_flash_bank *cfi_info = bank->driver_priv;
541 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
543 return cfi_read_atmel_pri_ext(bank);
545 else
547 return cfi_read_spansion_pri_ext(bank);
551 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
553 int printed;
554 struct cfi_flash_bank *cfi_info = bank->driver_priv;
555 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
557 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
558 buf += printed;
559 buf_size -= printed;
561 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
562 pri_ext->pri[1], pri_ext->pri[2],
563 pri_ext->major_version, pri_ext->minor_version);
564 buf += printed;
565 buf_size -= printed;
567 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
568 (pri_ext->SiliconRevision) >> 2,
569 (pri_ext->SiliconRevision) & 0x03);
570 buf += printed;
571 buf_size -= printed;
573 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
574 pri_ext->EraseSuspend,
575 pri_ext->BlkProt);
576 buf += printed;
577 buf_size -= printed;
579 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
580 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
581 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
583 return ERROR_OK;
586 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
588 int printed;
589 struct cfi_flash_bank *cfi_info = bank->driver_priv;
590 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
592 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
593 buf += printed;
594 buf_size -= printed;
596 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
597 buf += printed;
598 buf_size -= printed;
600 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
601 buf += printed;
602 buf_size -= printed;
604 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
605 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
606 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
607 buf += printed;
608 buf_size -= printed;
610 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
612 return ERROR_OK;
615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
617 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
619 struct cfi_flash_bank *cfi_info;
621 if (CMD_ARGC < 6)
623 LOG_WARNING("incomplete flash_bank cfi configuration");
624 return ERROR_FLASH_BANK_INVALID;
627 /* both widths must:
628 * - not exceed max value;
629 * - not be null;
630 * - be equal to a power of 2.
631 * bus must be wide enought to hold one chip */
632 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
633 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
634 || (bank->chip_width == 0)
635 || (bank->bus_width == 0)
636 || (bank->chip_width & (bank->chip_width - 1))
637 || (bank->bus_width & (bank->bus_width - 1))
638 || (bank->chip_width > bank->bus_width))
640 LOG_ERROR("chip and bus width have to specified in bytes");
641 return ERROR_FLASH_BANK_INVALID;
644 cfi_info = malloc(sizeof(struct cfi_flash_bank));
645 cfi_info->probed = 0;
646 bank->driver_priv = cfi_info;
648 cfi_info->write_algorithm = NULL;
650 cfi_info->x16_as_x8 = 0;
651 cfi_info->jedec_probe = 0;
652 cfi_info->not_cfi = 0;
654 for (unsigned i = 6; i < CMD_ARGC; i++)
656 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
658 cfi_info->x16_as_x8 = 1;
660 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
662 cfi_info->jedec_probe = 1;
666 cfi_info->write_algorithm = NULL;
668 /* bank wasn't probed yet */
669 cfi_info->qry[0] = -1;
671 return ERROR_OK;
674 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
676 int retval;
677 struct cfi_flash_bank *cfi_info = bank->driver_priv;
678 int i;
680 cfi_intel_clear_status_register(bank);
682 for (i = first; i <= last; i++)
684 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
686 return retval;
689 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
691 return retval;
694 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
695 bank->sectors[i].is_erased = 1;
696 else
698 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
700 return retval;
703 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
704 return ERROR_FLASH_OPERATION_FAILED;
708 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
711 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
713 int retval;
714 struct cfi_flash_bank *cfi_info = bank->driver_priv;
715 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
716 int i;
718 for (i = first; i <= last; i++)
720 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
722 return retval;
725 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
727 return retval;
730 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
732 return retval;
735 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
737 return retval;
740 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
742 return retval;
745 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
747 return retval;
750 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
751 bank->sectors[i].is_erased = 1;
752 else
754 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
756 return retval;
759 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
760 return ERROR_FLASH_OPERATION_FAILED;
764 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
767 static int cfi_erase(struct flash_bank *bank, int first, int last)
769 struct cfi_flash_bank *cfi_info = bank->driver_priv;
771 if (bank->target->state != TARGET_HALTED)
773 LOG_ERROR("Target not halted");
774 return ERROR_TARGET_NOT_HALTED;
777 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
779 return ERROR_FLASH_SECTOR_INVALID;
782 if (cfi_info->qry[0] != 'Q')
783 return ERROR_FLASH_BANK_NOT_PROBED;
785 switch (cfi_info->pri_id)
787 case 1:
788 case 3:
789 return cfi_intel_erase(bank, first, last);
790 break;
791 case 2:
792 return cfi_spansion_erase(bank, first, last);
793 break;
794 default:
795 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
796 break;
799 return ERROR_OK;
802 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
804 int retval;
805 struct cfi_flash_bank *cfi_info = bank->driver_priv;
806 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
807 struct target *target = bank->target; /* FIXME: to be removed */
808 uint8_t command[CFI_MAX_BUS_WIDTH]; /* FIXME: to be removed */
809 int retry = 0;
810 int i;
812 /* if the device supports neither legacy lock/unlock (bit 3) nor
813 * instant individual block locking (bit 5).
815 if (!(pri_ext->feature_support & 0x28))
816 return ERROR_FLASH_OPERATION_FAILED;
818 cfi_intel_clear_status_register(bank);
820 for (i = first; i <= last; i++)
822 cfi_command(bank, 0x60, command); /* FIXME: to be removed */
823 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
824 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
826 return retval;
828 if (set)
830 cfi_command(bank, 0x01, command); /* FIXME: to be removed */
831 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
832 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
834 return retval;
836 bank->sectors[i].is_protected = 1;
838 else
840 cfi_command(bank, 0xd0, command); /* FIXME: to be removed */
841 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
842 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
844 return retval;
846 bank->sectors[i].is_protected = 0;
849 /* instant individual block locking doesn't require reading of the status register */
850 if (!(pri_ext->feature_support & 0x20))
852 /* Clear lock bits operation may take up to 1.4s */
853 cfi_intel_wait_status_busy(bank, 1400);
855 else
857 uint8_t block_status;
858 /* read block lock bit, to verify status */
859 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
861 return retval;
863 block_status = cfi_get_u8(bank, i, 0x2);
865 if ((block_status & 0x1) != set)
867 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
868 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
870 return retval;
872 cfi_intel_wait_status_busy(bank, 10);
874 if (retry > 10)
875 return ERROR_FLASH_OPERATION_FAILED;
876 else
878 i--;
879 retry++;
885 /* if the device doesn't support individual block lock bits set/clear,
886 * all blocks have been unlocked in parallel, so we set those that should be protected
888 if ((!set) && (!(pri_ext->feature_support & 0x20)))
890 /* FIX!!! this code path is broken!!!
892 * The correct approach is:
894 * 1. read out current protection status
896 * 2. override read out protection status w/unprotected.
898 * 3. re-protect what should be protected.
901 for (i = 0; i < bank->num_sectors; i++)
903 if (bank->sectors[i].is_protected == 1)
905 cfi_intel_clear_status_register(bank);
907 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
909 return retval;
912 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
914 return retval;
917 cfi_intel_wait_status_busy(bank, 100);
922 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
925 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
927 struct cfi_flash_bank *cfi_info = bank->driver_priv;
929 if (bank->target->state != TARGET_HALTED)
931 LOG_ERROR("Target not halted");
932 return ERROR_TARGET_NOT_HALTED;
935 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
937 LOG_ERROR("Invalid sector range");
938 return ERROR_FLASH_SECTOR_INVALID;
941 if (cfi_info->qry[0] != 'Q')
942 return ERROR_FLASH_BANK_NOT_PROBED;
944 switch (cfi_info->pri_id)
946 case 1:
947 case 3:
948 return cfi_intel_protect(bank, set, first, last);
949 break;
950 default:
951 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
952 return ERROR_FAIL;
956 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
957 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
959 /* struct target *target = bank->target; */
961 int i;
963 /* NOTE:
964 * The data to flash must not be changed in endian! We write a bytestrem in
965 * target byte order already. Only the control and status byte lane of the flash
966 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
967 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
970 #if 0
971 if (target->endianness == TARGET_LITTLE_ENDIAN)
973 #endif
974 /* shift bytes */
975 for (i = 0; i < bank->bus_width - 1; i++)
976 word[i] = word[i + 1];
977 word[bank->bus_width - 1] = byte;
978 #if 0
980 else
982 /* shift bytes */
983 for (i = bank->bus_width - 1; i > 0; i--)
984 word[i] = word[i - 1];
985 word[0] = byte;
987 #endif
990 /* Convert code image to target endian */
991 /* FIXME create general block conversion fcts in target.c?) */
992 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
994 uint32_t i;
995 for (i = 0; i< count; i++)
997 target_buffer_set_u32(target, dest, *src);
998 dest += 4;
999 src++;
1003 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1005 struct target *target = bank->target;
1007 uint8_t buf[CFI_MAX_BUS_WIDTH];
1008 cfi_command(bank, cmd, buf);
1009 switch (bank->bus_width)
1011 case 1 :
1012 return buf[0];
1013 break;
1014 case 2 :
1015 return target_buffer_get_u16(target, buf);
1016 break;
1017 case 4 :
1018 return target_buffer_get_u32(target, buf);
1019 break;
1020 default :
1021 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1022 return 0;
1026 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1028 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1029 struct target *target = bank->target;
1030 struct reg_param reg_params[7];
1031 struct arm_algorithm armv4_5_info;
1032 struct working_area *source;
1033 uint32_t buffer_size = 32768;
1034 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1036 /* algorithm register usage:
1037 * r0: source address (in RAM)
1038 * r1: target address (in Flash)
1039 * r2: count
1040 * r3: flash write command
1041 * r4: status byte (returned to host)
1042 * r5: busy test pattern
1043 * r6: error test pattern
1046 static const uint32_t word_32_code[] = {
1047 0xe4904004, /* loop: ldr r4, [r0], #4 */
1048 0xe5813000, /* str r3, [r1] */
1049 0xe5814000, /* str r4, [r1] */
1050 0xe5914000, /* busy: ldr r4, [r1] */
1051 0xe0047005, /* and r7, r4, r5 */
1052 0xe1570005, /* cmp r7, r5 */
1053 0x1afffffb, /* bne busy */
1054 0xe1140006, /* tst r4, r6 */
1055 0x1a000003, /* bne done */
1056 0xe2522001, /* subs r2, r2, #1 */
1057 0x0a000001, /* beq done */
1058 0xe2811004, /* add r1, r1 #4 */
1059 0xeafffff2, /* b loop */
1060 0xeafffffe /* done: b -2 */
1063 static const uint32_t word_16_code[] = {
1064 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1065 0xe1c130b0, /* strh r3, [r1] */
1066 0xe1c140b0, /* strh r4, [r1] */
1067 0xe1d140b0, /* busy ldrh r4, [r1] */
1068 0xe0047005, /* and r7, r4, r5 */
1069 0xe1570005, /* cmp r7, r5 */
1070 0x1afffffb, /* bne busy */
1071 0xe1140006, /* tst r4, r6 */
1072 0x1a000003, /* bne done */
1073 0xe2522001, /* subs r2, r2, #1 */
1074 0x0a000001, /* beq done */
1075 0xe2811002, /* add r1, r1 #2 */
1076 0xeafffff2, /* b loop */
1077 0xeafffffe /* done: b -2 */
1080 static const uint32_t word_8_code[] = {
1081 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1082 0xe5c13000, /* strb r3, [r1] */
1083 0xe5c14000, /* strb r4, [r1] */
1084 0xe5d14000, /* busy ldrb r4, [r1] */
1085 0xe0047005, /* and r7, r4, r5 */
1086 0xe1570005, /* cmp r7, r5 */
1087 0x1afffffb, /* bne busy */
1088 0xe1140006, /* tst r4, r6 */
1089 0x1a000003, /* bne done */
1090 0xe2522001, /* subs r2, r2, #1 */
1091 0x0a000001, /* beq done */
1092 0xe2811001, /* add r1, r1 #1 */
1093 0xeafffff2, /* b loop */
1094 0xeafffffe /* done: b -2 */
1096 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1097 const uint32_t *target_code_src;
1098 uint32_t target_code_size;
1099 int retval = ERROR_OK;
1102 cfi_intel_clear_status_register(bank);
1104 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1105 armv4_5_info.core_mode = ARM_MODE_SVC;
1106 armv4_5_info.core_state = ARM_STATE_ARM;
1108 /* If we are setting up the write_algorith, we need target_code_src */
1109 /* if not we only need target_code_size. */
1111 /* However, we don't want to create multiple code paths, so we */
1112 /* do the unecessary evaluation of target_code_src, which the */
1113 /* compiler will probably nicely optimize away if not needed */
1115 /* prepare algorithm code for target endian */
1116 switch (bank->bus_width)
1118 case 1 :
1119 target_code_src = word_8_code;
1120 target_code_size = sizeof(word_8_code);
1121 break;
1122 case 2 :
1123 target_code_src = word_16_code;
1124 target_code_size = sizeof(word_16_code);
1125 break;
1126 case 4 :
1127 target_code_src = word_32_code;
1128 target_code_size = sizeof(word_32_code);
1129 break;
1130 default:
1131 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1132 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1135 /* flash write code */
1136 if (!cfi_info->write_algorithm)
1138 if (target_code_size > sizeof(target_code))
1140 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1141 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1143 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1145 /* Get memory for block write handler */
1146 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1147 if (retval != ERROR_OK)
1149 LOG_WARNING("No working area available, can't do block memory writes");
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1153 /* write algorithm code to working area */
1154 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1155 if (retval != ERROR_OK)
1157 LOG_ERROR("Unable to write block write code to target");
1158 goto cleanup;
1162 /* Get a workspace buffer for the data to flash starting with 32k size.
1163 Half size until buffer would be smaller 256 Bytem then fail back */
1164 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1165 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1167 buffer_size /= 2;
1168 if (buffer_size <= 256)
1170 LOG_WARNING("no large enough working area available, can't do block memory writes");
1171 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1172 goto cleanup;
1176 /* setup algo registers */
1177 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1178 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1179 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1180 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1181 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1182 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1183 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1185 /* prepare command and status register patterns */
1186 write_command_val = cfi_command_val(bank, 0x40);
1187 busy_pattern_val = cfi_command_val(bank, 0x80);
1188 error_pattern_val = cfi_command_val(bank, 0x7e);
1190 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1192 /* Programming main loop */
1193 while (count > 0)
1195 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1196 uint32_t wsm_error;
1198 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1200 goto cleanup;
1203 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1204 buf_set_u32(reg_params[1].value, 0, 32, address);
1205 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1207 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1208 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1209 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1211 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1213 /* Execute algorithm, assume breakpoint for last instruction */
1214 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1215 cfi_info->write_algorithm->address,
1216 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1217 10000, /* 10s should be enough for max. 32k of data */
1218 &armv4_5_info);
1220 /* On failure try a fall back to direct word writes */
1221 if (retval != ERROR_OK)
1223 cfi_intel_clear_status_register(bank);
1224 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1225 retval = ERROR_FLASH_OPERATION_FAILED;
1226 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1227 /* FIXME To allow fall back or recovery, we must save the actual status
1228 somewhere, so that a higher level code can start recovery. */
1229 goto cleanup;
1232 /* Check return value from algo code */
1233 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1234 if (wsm_error)
1236 /* read status register (outputs debug inforation) */
1237 cfi_intel_wait_status_busy(bank, 100);
1238 cfi_intel_clear_status_register(bank);
1239 retval = ERROR_FLASH_OPERATION_FAILED;
1240 goto cleanup;
1243 buffer += thisrun_count;
1244 address += thisrun_count;
1245 count -= thisrun_count;
1248 /* free up resources */
1249 cleanup:
1250 if (source)
1251 target_free_working_area(target, source);
1253 if (cfi_info->write_algorithm)
1255 target_free_working_area(target, cfi_info->write_algorithm);
1256 cfi_info->write_algorithm = NULL;
1259 destroy_reg_param(&reg_params[0]);
1260 destroy_reg_param(&reg_params[1]);
1261 destroy_reg_param(&reg_params[2]);
1262 destroy_reg_param(&reg_params[3]);
1263 destroy_reg_param(&reg_params[4]);
1264 destroy_reg_param(&reg_params[5]);
1265 destroy_reg_param(&reg_params[6]);
1267 return retval;
1270 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1272 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1273 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1274 struct target *target = bank->target;
1275 struct reg_param reg_params[10];
1276 struct arm_algorithm armv4_5_info;
1277 struct working_area *source;
1278 uint32_t buffer_size = 32768;
1279 uint32_t status;
1280 int retval, retvaltemp;
1281 int exit_code = ERROR_OK;
1283 /* input parameters - */
1284 /* R0 = source address */
1285 /* R1 = destination address */
1286 /* R2 = number of writes */
1287 /* R3 = flash write command */
1288 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1289 /* output parameters - */
1290 /* R5 = 0x80 ok 0x00 bad */
1291 /* temp registers - */
1292 /* R6 = value read from flash to test status */
1293 /* R7 = holding register */
1294 /* unlock registers - */
1295 /* R8 = unlock1_addr */
1296 /* R9 = unlock1_cmd */
1297 /* R10 = unlock2_addr */
1298 /* R11 = unlock2_cmd */
1300 static const uint32_t word_32_code[] = {
1301 /* 00008100 <sp_32_code>: */
1302 0xe4905004, /* ldr r5, [r0], #4 */
1303 0xe5889000, /* str r9, [r8] */
1304 0xe58ab000, /* str r11, [r10] */
1305 0xe5883000, /* str r3, [r8] */
1306 0xe5815000, /* str r5, [r1] */
1307 0xe1a00000, /* nop */
1308 /* */
1309 /* 00008110 <sp_32_busy>: */
1310 0xe5916000, /* ldr r6, [r1] */
1311 0xe0257006, /* eor r7, r5, r6 */
1312 0xe0147007, /* ands r7, r4, r7 */
1313 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1314 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1315 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1316 0xe5916000, /* ldr r6, [r1] */
1317 0xe0257006, /* eor r7, r5, r6 */
1318 0xe0147007, /* ands r7, r4, r7 */
1319 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1320 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1321 0x1a000004, /* bne 8154 <sp_32_done> */
1322 /* */
1323 /* 00008140 <sp_32_cont>: */
1324 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1325 0x03a05080, /* moveq r5, #128 ; 0x80 */
1326 0x0a000001, /* beq 8154 <sp_32_done> */
1327 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1328 0xeaffffe8, /* b 8100 <sp_32_code> */
1329 /* */
1330 /* 00008154 <sp_32_done>: */
1331 0xeafffffe /* b 8154 <sp_32_done> */
1334 static const uint32_t word_16_code[] = {
1335 /* 00008158 <sp_16_code>: */
1336 0xe0d050b2, /* ldrh r5, [r0], #2 */
1337 0xe1c890b0, /* strh r9, [r8] */
1338 0xe1cab0b0, /* strh r11, [r10] */
1339 0xe1c830b0, /* strh r3, [r8] */
1340 0xe1c150b0, /* strh r5, [r1] */
1341 0xe1a00000, /* nop (mov r0,r0) */
1342 /* */
1343 /* 00008168 <sp_16_busy>: */
1344 0xe1d160b0, /* ldrh r6, [r1] */
1345 0xe0257006, /* eor r7, r5, r6 */
1346 0xe0147007, /* ands r7, r4, r7 */
1347 0x0a000007, /* beq 8198 <sp_16_cont> */
1348 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1349 0x0afffff9, /* beq 8168 <sp_16_busy> */
1350 0xe1d160b0, /* ldrh r6, [r1] */
1351 0xe0257006, /* eor r7, r5, r6 */
1352 0xe0147007, /* ands r7, r4, r7 */
1353 0x0a000001, /* beq 8198 <sp_16_cont> */
1354 0xe3a05000, /* mov r5, #0 ; 0x0 */
1355 0x1a000004, /* bne 81ac <sp_16_done> */
1356 /* */
1357 /* 00008198 <sp_16_cont>: */
1358 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1359 0x03a05080, /* moveq r5, #128 ; 0x80 */
1360 0x0a000001, /* beq 81ac <sp_16_done> */
1361 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1362 0xeaffffe8, /* b 8158 <sp_16_code> */
1363 /* */
1364 /* 000081ac <sp_16_done>: */
1365 0xeafffffe /* b 81ac <sp_16_done> */
1368 static const uint32_t word_16_code_dq7only[] = {
1369 /* <sp_16_code>: */
1370 0xe0d050b2, /* ldrh r5, [r0], #2 */
1371 0xe1c890b0, /* strh r9, [r8] */
1372 0xe1cab0b0, /* strh r11, [r10] */
1373 0xe1c830b0, /* strh r3, [r8] */
1374 0xe1c150b0, /* strh r5, [r1] */
1375 0xe1a00000, /* nop (mov r0,r0) */
1376 /* */
1377 /* <sp_16_busy>: */
1378 0xe1d160b0, /* ldrh r6, [r1] */
1379 0xe0257006, /* eor r7, r5, r6 */
1380 0xe2177080, /* ands r7, #0x80 */
1381 0x1afffffb, /* bne 8168 <sp_16_busy> */
1382 /* */
1383 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1384 0x03a05080, /* moveq r5, #128 ; 0x80 */
1385 0x0a000001, /* beq 81ac <sp_16_done> */
1386 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1387 0xeafffff0, /* b 8158 <sp_16_code> */
1388 /* */
1389 /* 000081ac <sp_16_done>: */
1390 0xeafffffe /* b 81ac <sp_16_done> */
1393 static const uint32_t word_8_code[] = {
1394 /* 000081b0 <sp_16_code_end>: */
1395 0xe4d05001, /* ldrb r5, [r0], #1 */
1396 0xe5c89000, /* strb r9, [r8] */
1397 0xe5cab000, /* strb r11, [r10] */
1398 0xe5c83000, /* strb r3, [r8] */
1399 0xe5c15000, /* strb r5, [r1] */
1400 0xe1a00000, /* nop (mov r0,r0) */
1401 /* */
1402 /* 000081c0 <sp_8_busy>: */
1403 0xe5d16000, /* ldrb r6, [r1] */
1404 0xe0257006, /* eor r7, r5, r6 */
1405 0xe0147007, /* ands r7, r4, r7 */
1406 0x0a000007, /* beq 81f0 <sp_8_cont> */
1407 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1408 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1409 0xe5d16000, /* ldrb r6, [r1] */
1410 0xe0257006, /* eor r7, r5, r6 */
1411 0xe0147007, /* ands r7, r4, r7 */
1412 0x0a000001, /* beq 81f0 <sp_8_cont> */
1413 0xe3a05000, /* mov r5, #0 ; 0x0 */
1414 0x1a000004, /* bne 8204 <sp_8_done> */
1415 /* */
1416 /* 000081f0 <sp_8_cont>: */
1417 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1418 0x03a05080, /* moveq r5, #128 ; 0x80 */
1419 0x0a000001, /* beq 8204 <sp_8_done> */
1420 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1421 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1422 /* */
1423 /* 00008204 <sp_8_done>: */
1424 0xeafffffe /* b 8204 <sp_8_done> */
1427 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1428 armv4_5_info.core_mode = ARM_MODE_SVC;
1429 armv4_5_info.core_state = ARM_STATE_ARM;
1431 int target_code_size;
1432 const uint32_t *target_code_src;
1434 switch (bank->bus_width)
1436 case 1 :
1437 target_code_src = word_8_code;
1438 target_code_size = sizeof(word_8_code);
1439 break;
1440 case 2 :
1441 /* Check for DQ5 support */
1442 if( cfi_info->status_poll_mask & (1 << 5) )
1444 target_code_src = word_16_code;
1445 target_code_size = sizeof(word_16_code);
1447 else
1449 /* No DQ5 support. Use DQ7 DATA# polling only. */
1450 target_code_src = word_16_code_dq7only;
1451 target_code_size = sizeof(word_16_code_dq7only);
1453 break;
1454 case 4 :
1455 target_code_src = word_32_code;
1456 target_code_size = sizeof(word_32_code);
1457 break;
1458 default:
1459 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1463 /* flash write code */
1464 if (!cfi_info->write_algorithm)
1466 uint8_t *target_code;
1468 /* convert bus-width dependent algorithm code to correct endiannes */
1469 target_code = malloc(target_code_size);
1470 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1472 /* allocate working area */
1473 retval = target_alloc_working_area(target, target_code_size,
1474 &cfi_info->write_algorithm);
1475 if (retval != ERROR_OK)
1477 free(target_code);
1478 return retval;
1481 /* write algorithm code to working area */
1482 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1483 target_code_size, target_code)) != ERROR_OK)
1485 free(target_code);
1486 return retval;
1489 free(target_code);
1491 /* the following code still assumes target code is fixed 24*4 bytes */
1493 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1495 buffer_size /= 2;
1496 if (buffer_size <= 256)
1498 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1499 if (cfi_info->write_algorithm)
1500 target_free_working_area(target, cfi_info->write_algorithm);
1502 LOG_WARNING("not enough working area available, can't do block memory writes");
1503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1507 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1508 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1509 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1510 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1511 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1512 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1513 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1514 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1515 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1516 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1518 while (count > 0)
1520 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1522 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1524 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1525 buf_set_u32(reg_params[1].value, 0, 32, address);
1526 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1527 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1528 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1529 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1530 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1531 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1532 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1534 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1535 cfi_info->write_algorithm->address,
1536 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1537 10000, &armv4_5_info);
1539 status = buf_get_u32(reg_params[5].value, 0, 32);
1541 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1543 LOG_DEBUG("status: 0x%" PRIx32 , status);
1544 exit_code = ERROR_FLASH_OPERATION_FAILED;
1545 break;
1548 buffer += thisrun_count;
1549 address += thisrun_count;
1550 count -= thisrun_count;
1553 target_free_all_working_areas(target);
1555 destroy_reg_param(&reg_params[0]);
1556 destroy_reg_param(&reg_params[1]);
1557 destroy_reg_param(&reg_params[2]);
1558 destroy_reg_param(&reg_params[3]);
1559 destroy_reg_param(&reg_params[4]);
1560 destroy_reg_param(&reg_params[5]);
1561 destroy_reg_param(&reg_params[6]);
1562 destroy_reg_param(&reg_params[7]);
1563 destroy_reg_param(&reg_params[8]);
1564 destroy_reg_param(&reg_params[9]);
1566 return exit_code;
1569 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1571 int retval;
1572 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1573 struct target *target = bank->target;
1575 cfi_intel_clear_status_register(bank);
1576 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1578 return retval;
1581 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1583 return retval;
1586 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1588 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1590 return retval;
1593 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1594 return ERROR_FLASH_OPERATION_FAILED;
1597 return ERROR_OK;
1600 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1602 int retval;
1603 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1604 struct target *target = bank->target;
1606 /* Calculate buffer size and boundary mask */
1607 /* buffersize is (buffer size per chip) * (number of chips) */
1608 /* bufferwsize is buffersize in words */
1609 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1610 uint32_t buffermask = buffersize-1;
1611 uint32_t bufferwsize = buffersize / bank->bus_width;
1613 /* Check for valid range */
1614 if (address & buffermask)
1616 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1617 bank->base, address, cfi_info->max_buf_write_size);
1618 return ERROR_FLASH_OPERATION_FAILED;
1621 /* Check for valid size */
1622 if (wordcount > bufferwsize)
1624 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1625 return ERROR_FLASH_OPERATION_FAILED;
1628 /* Write to flash buffer */
1629 cfi_intel_clear_status_register(bank);
1631 /* Initiate buffer operation _*/
1632 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1634 return retval;
1636 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1638 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1640 return retval;
1643 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1644 return ERROR_FLASH_OPERATION_FAILED;
1647 /* Write buffer wordcount-1 and data words */
1648 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1650 return retval;
1653 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1655 return retval;
1658 /* Commit write operation */
1659 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1661 return retval;
1663 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1665 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1667 return retval;
1670 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1671 return ERROR_FLASH_OPERATION_FAILED;
1674 return ERROR_OK;
1677 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1679 int retval;
1680 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1681 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1682 struct target *target = bank->target;
1684 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1686 return retval;
1689 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1691 return retval;
1694 if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1696 return retval;
1699 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1701 return retval;
1704 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1706 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1708 return retval;
1711 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1712 return ERROR_FLASH_OPERATION_FAILED;
1715 return ERROR_OK;
1718 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1720 int retval;
1721 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1722 struct target *target = bank->target;
1723 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1725 /* Calculate buffer size and boundary mask */
1726 /* buffersize is (buffer size per chip) * (number of chips) */
1727 /* bufferwsize is buffersize in words */
1728 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1729 uint32_t buffermask = buffersize-1;
1730 uint32_t bufferwsize = buffersize / bank->bus_width;
1732 /* Check for valid range */
1733 if (address & buffermask)
1735 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1736 return ERROR_FLASH_OPERATION_FAILED;
1739 /* Check for valid size */
1740 if (wordcount > bufferwsize)
1742 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1743 return ERROR_FLASH_OPERATION_FAILED;
1746 // Unlock
1747 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1749 return retval;
1752 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1754 return retval;
1757 // Buffer load command
1758 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1760 return retval;
1763 /* Write buffer wordcount-1 and data words */
1764 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1766 return retval;
1769 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1771 return retval;
1774 /* Commit write operation */
1775 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1777 return retval;
1780 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1782 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1784 return retval;
1787 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1788 return ERROR_FLASH_OPERATION_FAILED;
1791 return ERROR_OK;
1794 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1796 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1798 switch (cfi_info->pri_id)
1800 case 1:
1801 case 3:
1802 return cfi_intel_write_word(bank, word, address);
1803 break;
1804 case 2:
1805 return cfi_spansion_write_word(bank, word, address);
1806 break;
1807 default:
1808 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1809 break;
1812 return ERROR_FLASH_OPERATION_FAILED;
1815 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1817 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1819 switch (cfi_info->pri_id)
1821 case 1:
1822 case 3:
1823 return cfi_intel_write_words(bank, word, wordcount, address);
1824 break;
1825 case 2:
1826 return cfi_spansion_write_words(bank, word, wordcount, address);
1827 break;
1828 default:
1829 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1830 break;
1833 return ERROR_FLASH_OPERATION_FAILED;
1836 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1838 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1839 struct target *target = bank->target;
1840 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1841 uint32_t write_p, copy_p;
1842 int align; /* number of unaligned bytes */
1843 int blk_count; /* number of bus_width bytes for block copy */
1844 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1845 int i;
1846 int retval;
1848 if (bank->target->state != TARGET_HALTED)
1850 LOG_ERROR("Target not halted");
1851 return ERROR_TARGET_NOT_HALTED;
1854 if (offset + count > bank->size)
1855 return ERROR_FLASH_DST_OUT_OF_BANK;
1857 if (cfi_info->qry[0] != 'Q')
1858 return ERROR_FLASH_BANK_NOT_PROBED;
1860 /* start at the first byte of the first word (bus_width size) */
1861 write_p = address & ~(bank->bus_width - 1);
1862 if ((align = address - write_p) != 0)
1864 LOG_INFO("Fixup %d unaligned head bytes", align);
1866 for (i = 0; i < bank->bus_width; i++)
1867 current_word[i] = 0;
1868 copy_p = write_p;
1870 /* copy bytes before the first write address */
1871 for (i = 0; i < align; ++i, ++copy_p)
1873 uint8_t byte;
1874 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1876 return retval;
1878 cfi_add_byte(bank, current_word, byte);
1881 /* add bytes from the buffer */
1882 for (; (i < bank->bus_width) && (count > 0); i++)
1884 cfi_add_byte(bank, current_word, *buffer++);
1885 count--;
1886 copy_p++;
1889 /* if the buffer is already finished, copy bytes after the last write address */
1890 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1892 uint8_t byte;
1893 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1895 return retval;
1897 cfi_add_byte(bank, current_word, byte);
1900 retval = cfi_write_word(bank, current_word, write_p);
1901 if (retval != ERROR_OK)
1902 return retval;
1903 write_p = copy_p;
1906 /* handle blocks of bus_size aligned bytes */
1907 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1908 switch (cfi_info->pri_id)
1910 /* try block writes (fails without working area) */
1911 case 1:
1912 case 3:
1913 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1914 break;
1915 case 2:
1916 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1917 break;
1918 default:
1919 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1920 retval = ERROR_FLASH_OPERATION_FAILED;
1921 break;
1923 if (retval == ERROR_OK)
1925 /* Increment pointers and decrease count on succesful block write */
1926 buffer += blk_count;
1927 write_p += blk_count;
1928 count -= blk_count;
1930 else
1932 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1934 /* Calculate buffer size and boundary mask */
1935 /* buffersize is (buffer size per chip) * (number of chips) */
1936 /* bufferwsize is buffersize in words */
1937 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1938 uint32_t buffermask = buffersize-1;
1939 uint32_t bufferwsize = buffersize / bank->bus_width;
1941 /* fall back to memory writes */
1942 while (count >= (uint32_t)bank->bus_width)
1944 int fallback;
1945 if ((write_p & 0xff) == 0)
1947 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1949 fallback = 1;
1950 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1952 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1953 if (retval == ERROR_OK)
1955 buffer += buffersize;
1956 write_p += buffersize;
1957 count -= buffersize;
1958 fallback = 0;
1961 /* try the slow way? */
1962 if (fallback)
1964 for (i = 0; i < bank->bus_width; i++)
1965 current_word[i] = 0;
1967 for (i = 0; i < bank->bus_width; i++)
1969 cfi_add_byte(bank, current_word, *buffer++);
1972 retval = cfi_write_word(bank, current_word, write_p);
1973 if (retval != ERROR_OK)
1974 return retval;
1976 write_p += bank->bus_width;
1977 count -= bank->bus_width;
1981 else
1982 return retval;
1985 /* return to read array mode, so we can read from flash again for padding */
1986 if ((retval = cfi_reset(bank)) != ERROR_OK)
1988 return retval;
1991 /* handle unaligned tail bytes */
1992 if (count > 0)
1994 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
1996 copy_p = write_p;
1997 for (i = 0; i < bank->bus_width; i++)
1998 current_word[i] = 0;
2000 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2002 cfi_add_byte(bank, current_word, *buffer++);
2003 count--;
2005 for (; i < bank->bus_width; ++i, ++copy_p)
2007 uint8_t byte;
2008 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2010 return retval;
2012 cfi_add_byte(bank, current_word, byte);
2014 retval = cfi_write_word(bank, current_word, write_p);
2015 if (retval != ERROR_OK)
2016 return retval;
2019 /* return to read array mode */
2020 return cfi_reset(bank);
2023 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2025 (void) param;
2026 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2027 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2029 pri_ext->_reversed_geometry = 1;
2032 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2034 int i;
2035 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2036 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2037 (void) param;
2039 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2041 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2043 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2045 int j = (cfi_info->num_erase_regions - 1) - i;
2046 uint32_t swap;
2048 swap = cfi_info->erase_region_info[i];
2049 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2050 cfi_info->erase_region_info[j] = swap;
2055 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2057 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2058 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2059 struct cfi_unlock_addresses *unlock_addresses = param;
2061 pri_ext->_unlock1 = unlock_addresses->unlock1;
2062 pri_ext->_unlock2 = unlock_addresses->unlock2;
2066 static int cfi_query_string(struct flash_bank *bank, int address)
2068 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2069 int retval;
2071 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2073 return retval;
2076 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2077 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2078 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2080 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2082 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2084 if ((retval = cfi_reset(bank)) != ERROR_OK)
2086 return retval;
2088 LOG_ERROR("Could not probe bank: no QRY");
2089 return ERROR_FLASH_BANK_INVALID;
2092 return ERROR_OK;
2095 static int cfi_probe(struct flash_bank *bank)
2097 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2098 struct target *target = bank->target;
2099 int num_sectors = 0;
2100 int i;
2101 int sector = 0;
2102 uint32_t unlock1 = 0x555;
2103 uint32_t unlock2 = 0x2aa;
2104 int retval;
2106 if (bank->target->state != TARGET_HALTED)
2108 LOG_ERROR("Target not halted");
2109 return ERROR_TARGET_NOT_HALTED;
2112 cfi_info->probed = 0;
2114 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2115 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2117 if (cfi_info->jedec_probe)
2119 unlock1 = 0x5555;
2120 unlock2 = 0x2aaa;
2123 /* switch to read identifier codes mode ("AUTOSELECT") */
2124 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2126 return retval;
2128 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2130 return retval;
2132 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2134 return retval;
2137 if (bank->chip_width == 1)
2139 uint8_t manufacturer, device_id;
2140 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2142 return retval;
2144 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2146 return retval;
2148 cfi_info->manufacturer = manufacturer;
2149 cfi_info->device_id = device_id;
2151 else if (bank->chip_width == 2)
2153 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2155 return retval;
2157 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2159 return retval;
2163 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2164 /* switch back to read array mode */
2165 if ((retval = cfi_reset(bank)) != ERROR_OK)
2167 return retval;
2170 /* check device/manufacturer ID for known non-CFI flashes. */
2171 cfi_fixup_non_cfi(bank);
2173 /* query only if this is a CFI compatible flash,
2174 * otherwise the relevant info has already been filled in
2176 if (cfi_info->not_cfi == 0)
2178 int retval;
2180 /* enter CFI query mode
2181 * according to JEDEC Standard No. 68.01,
2182 * a single bus sequence with address = 0x55, data = 0x98 should put
2183 * the device into CFI query mode.
2185 * SST flashes clearly violate this, and we will consider them incompatbile for now
2188 retval = cfi_query_string(bank, 0x55);
2189 if (retval != ERROR_OK)
2192 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2193 * be harmless enough:
2195 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2197 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2198 retval = cfi_query_string(bank, 0x555);
2200 if (retval != ERROR_OK)
2201 return retval;
2203 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2204 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2205 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2206 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2208 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2210 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2211 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2212 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2213 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2214 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2215 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2216 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2217 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2218 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2219 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2220 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2221 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2223 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2224 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2225 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2226 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2227 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2228 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2229 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2230 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2231 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2232 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2233 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2235 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2236 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2237 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2238 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2240 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2242 if (cfi_info->num_erase_regions)
2244 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2245 for (i = 0; i < cfi_info->num_erase_regions; i++)
2247 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2248 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2250 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2251 (cfi_info->erase_region_info[i] >> 16) * 256);
2254 else
2256 cfi_info->erase_region_info = NULL;
2259 /* We need to read the primary algorithm extended query table before calculating
2260 * the sector layout to be able to apply fixups
2262 switch (cfi_info->pri_id)
2264 /* Intel command set (standard and extended) */
2265 case 0x0001:
2266 case 0x0003:
2267 cfi_read_intel_pri_ext(bank);
2268 break;
2269 /* AMD/Spansion, Atmel, ... command set */
2270 case 0x0002:
2271 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2272 cfi_read_0002_pri_ext(bank);
2273 break;
2274 default:
2275 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2276 break;
2279 /* return to read array mode
2280 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2282 if ((retval = cfi_reset(bank)) != ERROR_OK)
2284 return retval;
2286 } /* end CFI case */
2288 /* apply fixups depending on the primary command set */
2289 switch (cfi_info->pri_id)
2291 /* Intel command set (standard and extended) */
2292 case 0x0001:
2293 case 0x0003:
2294 cfi_fixup(bank, cfi_0001_fixups);
2295 break;
2296 /* AMD/Spansion, Atmel, ... command set */
2297 case 0x0002:
2298 cfi_fixup(bank, cfi_0002_fixups);
2299 break;
2300 default:
2301 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2302 break;
2305 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2307 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2310 if (cfi_info->num_erase_regions == 0)
2312 /* a device might have only one erase block, spanning the whole device */
2313 bank->num_sectors = 1;
2314 bank->sectors = malloc(sizeof(struct flash_sector));
2316 bank->sectors[sector].offset = 0x0;
2317 bank->sectors[sector].size = bank->size;
2318 bank->sectors[sector].is_erased = -1;
2319 bank->sectors[sector].is_protected = -1;
2321 else
2323 uint32_t offset = 0;
2325 for (i = 0; i < cfi_info->num_erase_regions; i++)
2327 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2330 bank->num_sectors = num_sectors;
2331 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2333 for (i = 0; i < cfi_info->num_erase_regions; i++)
2335 uint32_t j;
2336 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2338 bank->sectors[sector].offset = offset;
2339 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2340 offset += bank->sectors[sector].size;
2341 bank->sectors[sector].is_erased = -1;
2342 bank->sectors[sector].is_protected = -1;
2343 sector++;
2346 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2348 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2349 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2353 cfi_info->probed = 1;
2355 return ERROR_OK;
2358 static int cfi_auto_probe(struct flash_bank *bank)
2360 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2361 if (cfi_info->probed)
2362 return ERROR_OK;
2363 return cfi_probe(bank);
2366 static int cfi_intel_protect_check(struct flash_bank *bank)
2368 int retval;
2369 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2370 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2371 int i;
2373 /* check if block lock bits are supported on this device */
2374 if (!(pri_ext->blk_status_reg_mask & 0x1))
2375 return ERROR_FLASH_OPERATION_FAILED;
2377 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2379 return retval;
2382 for (i = 0; i < bank->num_sectors; i++)
2384 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2386 if (block_status & 1)
2387 bank->sectors[i].is_protected = 1;
2388 else
2389 bank->sectors[i].is_protected = 0;
2392 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2395 static int cfi_spansion_protect_check(struct flash_bank *bank)
2397 int retval;
2398 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2399 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2400 int i;
2402 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2404 return retval;
2407 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2409 return retval;
2412 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2414 return retval;
2417 for (i = 0; i < bank->num_sectors; i++)
2419 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2421 if (block_status & 1)
2422 bank->sectors[i].is_protected = 1;
2423 else
2424 bank->sectors[i].is_protected = 0;
2427 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2430 static int cfi_protect_check(struct flash_bank *bank)
2432 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2434 if (bank->target->state != TARGET_HALTED)
2436 LOG_ERROR("Target not halted");
2437 return ERROR_TARGET_NOT_HALTED;
2440 if (cfi_info->qry[0] != 'Q')
2441 return ERROR_FLASH_BANK_NOT_PROBED;
2443 switch (cfi_info->pri_id)
2445 case 1:
2446 case 3:
2447 return cfi_intel_protect_check(bank);
2448 break;
2449 case 2:
2450 return cfi_spansion_protect_check(bank);
2451 break;
2452 default:
2453 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2454 break;
2457 return ERROR_OK;
2460 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2462 int printed;
2463 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2465 if (cfi_info->qry[0] == (char)-1)
2467 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2468 return ERROR_OK;
2471 if (cfi_info->not_cfi == 0)
2472 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2473 else
2474 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2475 buf += printed;
2476 buf_size -= printed;
2478 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2479 cfi_info->manufacturer, cfi_info->device_id);
2480 buf += printed;
2481 buf_size -= printed;
2483 if (cfi_info->not_cfi == 0)
2485 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2486 buf += printed;
2487 buf_size -= printed;
2489 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2490 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2491 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2492 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2493 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2494 buf += printed;
2495 buf_size -= printed;
2497 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2498 1 << cfi_info->word_write_timeout_typ,
2499 1 << cfi_info->buf_write_timeout_typ,
2500 1 << cfi_info->block_erase_timeout_typ,
2501 1 << cfi_info->chip_erase_timeout_typ);
2502 buf += printed;
2503 buf_size -= printed;
2505 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2506 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2507 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2508 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2509 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2510 buf += printed;
2511 buf_size -= printed;
2513 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2514 cfi_info->dev_size,
2515 cfi_info->interface_desc,
2516 1 << cfi_info->max_buf_write_size);
2517 buf += printed;
2518 buf_size -= printed;
2520 switch (cfi_info->pri_id)
2522 case 1:
2523 case 3:
2524 cfi_intel_info(bank, buf, buf_size);
2525 break;
2526 case 2:
2527 cfi_spansion_info(bank, buf, buf_size);
2528 break;
2529 default:
2530 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2531 break;
2535 return ERROR_OK;
2538 struct flash_driver cfi_flash = {
2539 .name = "cfi",
2540 .flash_bank_command = cfi_flash_bank_command,
2541 .erase = cfi_erase,
2542 .protect = cfi_protect,
2543 .write = cfi_write,
2544 .probe = cfi_probe,
2545 .auto_probe = cfi_auto_probe,
2546 .erase_check = default_flash_blank_check,
2547 .protect_check = cfi_protect_check,
2548 .info = cfi_info,