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Luminary-icdi comment update
[openocd/openocdswd.git] / src / target / etm.c
blob9da69550421df9b117ddb76c790dbdf2bee5dbda
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_CTRL_DBGRQ
450 & ~ETM_PORT_CLOCK_MASK)
451 | etm_ctx->control;
452
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
455
456 etm_ctx->control = etm_ctrl_value;
457
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 return retval;
460
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
463 */
464
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
466 {
467 LOG_ERROR("ETM capture driver initialization failed");
468 return retval;
469 }
470 return ERROR_OK;
471 }
472
473 static int etm_get_reg(struct reg *reg)
474 {
475 int retval;
476
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
478 {
479 LOG_ERROR("BUG: error scheduling etm register read");
480 return retval;
481 }
482
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
484 {
485 LOG_ERROR("register read failed");
486 return retval;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
494 {
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
499 int retval;
500
501 if (etm_reg->reg_info->mode == WO) {
502 LOG_ERROR("BUG: can't read write-only register %s", r->name);
503 return ERROR_INVALID_ARGUMENTS;
504 }
505
506 LOG_DEBUG("%s (%u)", r->name, reg_addr);
507
508 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
509 if (retval != ERROR_OK)
510 return retval;
511 retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
512 if (retval != ERROR_OK)
513 return retval;
514
515 fields[0].num_bits = 32;
516 fields[0].out_value = reg->value;
517 fields[0].in_value = NULL;
518 fields[0].check_value = NULL;
519 fields[0].check_mask = NULL;
520
521 fields[1].num_bits = 7;
522 uint8_t temp1;
523 fields[1].out_value = &temp1;
524 buf_set_u32(&temp1, 0, 7, reg_addr);
525 fields[1].in_value = NULL;
526 fields[1].check_value = NULL;
527 fields[1].check_mask = NULL;
528
529 fields[2].num_bits = 1;
530 uint8_t temp2;
531 fields[2].out_value = &temp2;
532 buf_set_u32(&temp2, 0, 1, 0);
533 fields[2].in_value = NULL;
534 fields[2].check_value = NULL;
535 fields[2].check_mask = NULL;
536
537 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
538
539 fields[0].in_value = reg->value;
540 fields[0].check_value = check_value;
541 fields[0].check_mask = check_mask;
542
543 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
544
545 return ERROR_OK;
546 }
547
548 static int etm_set_reg(struct reg *reg, uint32_t value)
549 {
550 int retval;
551
552 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
553 {
554 LOG_ERROR("BUG: error scheduling etm register write");
555 return retval;
556 }
557
558 buf_set_u32(reg->value, 0, reg->size, value);
559 reg->valid = 1;
560 reg->dirty = 0;
561
562 return ERROR_OK;
563 }
564
565 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
566 {
567 int retval;
568
569 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
570
571 if ((retval = jtag_execute_queue()) != ERROR_OK)
572 {
573 LOG_ERROR("register write failed");
574 return retval;
575 }
576 return ERROR_OK;
577 }
578
579 static int etm_write_reg(struct reg *reg, uint32_t value)
580 {
581 struct etm_reg *etm_reg = reg->arch_info;
582 const struct etm_reg_info *r = etm_reg->reg_info;
583 uint8_t reg_addr = r->addr & 0x7f;
584 struct scan_field fields[3];
585 int retval;
586
587 if (etm_reg->reg_info->mode == RO) {
588 LOG_ERROR("BUG: can't write read--only register %s", r->name);
589 return ERROR_INVALID_ARGUMENTS;
590 }
591
592 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
593
594 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
595 if (retval != ERROR_OK)
596 return retval;
597 retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
598 if (retval != ERROR_OK)
599 return retval;
600
601 fields[0].num_bits = 32;
602 uint8_t tmp1[4];
603 fields[0].out_value = tmp1;
604 buf_set_u32(tmp1, 0, 32, value);
605 fields[0].in_value = NULL;
606
607 fields[1].num_bits = 7;
608 uint8_t tmp2;
609 fields[1].out_value = &tmp2;
610 buf_set_u32(&tmp2, 0, 7, reg_addr);
611 fields[1].in_value = NULL;
612
613 fields[2].num_bits = 1;
614 uint8_t tmp3;
615 fields[2].out_value = &tmp3;
616 buf_set_u32(&tmp3, 0, 1, 1);
617 fields[2].in_value = NULL;
618
619 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
620
621 return ERROR_OK;
622 }
623
624
625 /* ETM trace analysis functionality */
626
627 static struct etm_capture_driver *etm_capture_drivers[] =
628 {
629 &etb_capture_driver,
630 &etm_dummy_capture_driver,
631 #if BUILD_OOCD_TRACE == 1
632 &oocd_trace_capture_driver,
633 #endif
634 NULL
635 };
636
637 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
638 {
639 int i;
640 int section = -1;
641 size_t size_read;
642 uint32_t opcode;
643 int retval;
644
645 if (!ctx->image)
646 return ERROR_TRACE_IMAGE_UNAVAILABLE;
647
648 /* search for the section the current instruction belongs to */
649 for (i = 0; i < ctx->image->num_sections; i++)
650 {
651 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
652 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
653 {
654 section = i;
655 break;
656 }
657 }
658
659 if (section == -1)
660 {
661 /* current instruction couldn't be found in the image */
662 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
663 }
664
665 if (ctx->core_state == ARM_STATE_ARM)
666 {
667 uint8_t buf[4];
668 if ((retval = image_read_section(ctx->image, section,
669 ctx->current_pc - ctx->image->sections[section].base_address,
670 4, buf, &size_read)) != ERROR_OK)
671 {
672 LOG_ERROR("error while reading instruction: %i", retval);
673 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
674 }
675 opcode = target_buffer_get_u32(ctx->target, buf);
676 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
677 }
678 else if (ctx->core_state == ARM_STATE_THUMB)
679 {
680 uint8_t buf[2];
681 if ((retval = image_read_section(ctx->image, section,
682 ctx->current_pc - ctx->image->sections[section].base_address,
683 2, buf, &size_read)) != ERROR_OK)
684 {
685 LOG_ERROR("error while reading instruction: %i", retval);
686 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
687 }
688 opcode = target_buffer_get_u16(ctx->target, buf);
689 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
690 }
691 else if (ctx->core_state == ARM_STATE_JAZELLE)
692 {
693 LOG_ERROR("BUG: tracing of jazelle code not supported");
694 return ERROR_FAIL;
695 }
696 else
697 {
698 LOG_ERROR("BUG: unknown core state encountered");
699 return ERROR_FAIL;
700 }
701
702 return ERROR_OK;
703 }
704
705 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
706 {
707 while (ctx->data_index < ctx->trace_depth)
708 {
709 /* if the caller specified an address packet offset, skip until the
710 * we reach the n-th cycle marked with tracesync */
711 if (apo > 0)
712 {
713 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
714 apo--;
715
716 if (apo > 0)
717 {
718 ctx->data_index++;
719 ctx->data_half = 0;
720 }
721 continue;
722 }
723
724 /* no tracedata output during a TD cycle
725 * or in a trigger cycle */
726 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
727 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
728 {
729 ctx->data_index++;
730 ctx->data_half = 0;
731 continue;
732 }
733
734 /* FIXME there are more port widths than these... */
735 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
736 {
737 if (ctx->data_half == 0)
738 {
739 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
740 ctx->data_half = 1;
741 }
742 else
743 {
744 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
745 ctx->data_half = 0;
746 ctx->data_index++;
747 }
748 }
749 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
750 {
751 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
752 ctx->data_index++;
753 }
754 else
755 {
756 /* on a 4-bit port, a packet will be output during two consecutive cycles */
757 if (ctx->data_index > (ctx->trace_depth - 2))
758 return -1;
759
760 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
761 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
762 ctx->data_index += 2;
763 }
764
765 return 0;
766 }
767
768 return -1;
769 }
770
771 static int etmv1_branch_address(struct etm_context *ctx)
772 {
773 int retval;
774 uint8_t packet;
775 int shift = 0;
776 int apo;
777 uint32_t i;
778
779 /* quit analysis if less than two cycles are left in the trace
780 * because we can't extract the APO */
781 if (ctx->data_index > (ctx->trace_depth - 2))
782 return -1;
783
784 /* a BE could be output during an APO cycle, skip the current
785 * and continue with the new one */
786 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
787 return 1;
788 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
789 return 2;
790
791 /* address packet offset encoded in the next two cycles' pipestat bits */
792 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
793 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
794
795 /* count number of tracesync cycles between current pipe_index and data_index
796 * i.e. the number of tracesyncs that data_index already passed by
797 * to subtract them from the APO */
798 for (i = ctx->pipe_index; i < ctx->data_index; i++)
799 {
800 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
801 apo--;
802 }
803
804 /* extract up to four 7-bit packets */
805 do {
806 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
807 return -1;
808 ctx->last_branch &= ~(0x7f << shift);
809 ctx->last_branch |= (packet & 0x7f) << shift;
810 shift += 7;
811 } while ((packet & 0x80) && (shift < 28));
812
813 /* one last packet holding 4 bits of the address, plus the branch reason code */
814 if ((shift == 28) && (packet & 0x80))
815 {
816 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
817 return -1;
818 ctx->last_branch &= 0x0fffffff;
819 ctx->last_branch |= (packet & 0x0f) << 28;
820 ctx->last_branch_reason = (packet & 0x70) >> 4;
821 shift += 4;
822 }
823 else
824 {
825 ctx->last_branch_reason = 0;
826 }
827
828 if (shift == 32)
829 {
830 ctx->pc_ok = 1;
831 }
832
833 /* if a full address was output, we might have branched into Jazelle state */
834 if ((shift == 32) && (packet & 0x80))
835 {
836 ctx->core_state = ARM_STATE_JAZELLE;
837 }
838 else
839 {
840 /* if we didn't branch into Jazelle state, the current processor state is
841 * encoded in bit 0 of the branch target address */
842 if (ctx->last_branch & 0x1)
843 {
844 ctx->core_state = ARM_STATE_THUMB;
845 ctx->last_branch &= ~0x1;
846 }
847 else
848 {
849 ctx->core_state = ARM_STATE_ARM;
850 ctx->last_branch &= ~0x3;
851 }
852 }
853
854 return 0;
855 }
856
857 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
858 {
859 int j;
860 uint8_t buf[4];
861 int retval;
862
863 for (j = 0; j < size; j++)
864 {
865 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
866 return -1;
867 }
868
869 if (size == 8)
870 {
871 LOG_ERROR("TODO: add support for 64-bit values");
872 return -1;
873 }
874 else if (size == 4)
875 *data = target_buffer_get_u32(ctx->target, buf);
876 else if (size == 2)
877 *data = target_buffer_get_u16(ctx->target, buf);
878 else if (size == 1)
879 *data = buf[0];
880 else
881 return -1;
882
883 return 0;
884 }
885
886 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
887 {
888 int retval;
889 struct arm_instruction instruction;
890
891 /* read the trace data if it wasn't read already */
892 if (ctx->trace_depth == 0)
893 ctx->capture_driver->read_trace(ctx);
894
895 if (ctx->trace_depth == 0) {
896 command_print(cmd_ctx, "Trace is empty.");
897 return ERROR_OK;
898 }
899
900 /* start at the beginning of the captured trace */
901 ctx->pipe_index = 0;
902 ctx->data_index = 0;
903 ctx->data_half = 0;
904
905 /* neither the PC nor the data pointer are valid */
906 ctx->pc_ok = 0;
907 ctx->ptr_ok = 0;
908
909 while (ctx->pipe_index < ctx->trace_depth)
910 {
911 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
912 uint32_t next_pc = ctx->current_pc;
913 uint32_t old_data_index = ctx->data_index;
914 uint32_t old_data_half = ctx->data_half;
915 uint32_t old_index = ctx->pipe_index;
916 uint32_t last_instruction = ctx->last_instruction;
917 uint32_t cycles = 0;
918 int current_pc_ok = ctx->pc_ok;
919
920 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
921 {
922 command_print(cmd_ctx, "--- trigger ---");
923 }
924
925 /* instructions execute in IE/D or BE/D cycles */
926 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
927 ctx->last_instruction = ctx->pipe_index;
928
929 /* if we don't have a valid pc skip until we reach an indirect branch */
930 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
931 {
932 ctx->pipe_index++;
933 continue;
934 }
935
936 /* any indirect branch could have interrupted instruction flow
937 * - the branch reason code could indicate a trace discontinuity
938 * - a branch to the exception vectors indicates an exception
939 */
940 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
941 {
942 /* backup current data index, to be able to consume the branch address
943 * before examining data address and values
944 */
945 old_data_index = ctx->data_index;
946 old_data_half = ctx->data_half;
947
948 ctx->last_instruction = ctx->pipe_index;
949
950 if ((retval = etmv1_branch_address(ctx)) != 0)
951 {
952 /* negative return value from etmv1_branch_address means we ran out of packets,
953 * quit analysing the trace */
954 if (retval < 0)
955 break;
956
957 /* a positive return values means the current branch was abandoned,
958 * and a new branch was encountered in cycle ctx->pipe_index + retval;
959 */
960 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
961 ctx->pipe_index += retval;
962 continue;
963 }
964
965 /* skip over APO cycles */
966 ctx->pipe_index += 2;
967
968 switch (ctx->last_branch_reason)
969 {
970 case 0x0: /* normal PC change */
971 next_pc = ctx->last_branch;
972 break;
973 case 0x1: /* tracing enabled */
974 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
975 ctx->current_pc = ctx->last_branch;
976 ctx->pipe_index++;
977 continue;
978 break;
979 case 0x2: /* trace restarted after FIFO overflow */
980 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
981 ctx->current_pc = ctx->last_branch;
982 ctx->pipe_index++;
983 continue;
984 break;
985 case 0x3: /* exit from debug state */
986 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
987 ctx->current_pc = ctx->last_branch;
988 ctx->pipe_index++;
989 continue;
990 break;
991 case 0x4: /* periodic synchronization point */
992 next_pc = ctx->last_branch;
993 /* if we had no valid PC prior to this synchronization point,
994 * we have to move on with the next trace cycle
995 */
996 if (!current_pc_ok)
997 {
998 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
999 ctx->current_pc = next_pc;
1000 ctx->pipe_index++;
1001 continue;
1002 }
1003 break;
1004 default: /* reserved */
1005 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1006 return ERROR_FAIL;
1007 }
1008
1009 /* if we got here the branch was a normal PC change
1010 * (or a periodic synchronization point, which means the same for that matter)
1011 * if we didn't accquire a complete PC continue with the next cycle
1012 */
1013 if (!ctx->pc_ok)
1014 continue;
1015
1016 /* indirect branch to the exception vector means an exception occured */
1017 if ((ctx->last_branch <= 0x20)
1018 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1019 {
1020 if ((ctx->last_branch & 0xff) == 0x10)
1021 {
1022 command_print(cmd_ctx, "data abort");
1023 }
1024 else
1025 {
1026 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1027 ctx->current_pc = ctx->last_branch;
1028 ctx->pipe_index++;
1029 continue;
1030 }
1031 }
1032 }
1033
1034 /* an instruction was executed (or not, depending on the condition flags)
1035 * retrieve it from the image for displaying */
1036 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1037 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1038 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1039 {
1040 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1041 {
1042 /* can't continue tracing with no image available */
1043 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1044 {
1045 return retval;
1046 }
1047 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1048 {
1049 /* TODO: handle incomplete images
1050 * for now we just quit the analsysis*/
1051 return retval;
1052 }
1053 }
1054
1055 cycles = old_index - last_instruction;
1056 }
1057
1058 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1059 {
1060 uint32_t new_data_index = ctx->data_index;
1061 uint32_t new_data_half = ctx->data_half;
1062
1063 /* in case of a branch with data, the branch target address was consumed before
1064 * we temporarily go back to the saved data index */
1065 if (pipestat == STAT_BD)
1066 {
1067 ctx->data_index = old_data_index;
1068 ctx->data_half = old_data_half;
1069 }
1070
1071 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1072 {
1073 uint8_t packet;
1074 int shift = 0;
1075
1076 do {
1077 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1078 return ERROR_ETM_ANALYSIS_FAILED;
1079 ctx->last_ptr &= ~(0x7f << shift);
1080 ctx->last_ptr |= (packet & 0x7f) << shift;
1081 shift += 7;
1082 } while ((packet & 0x80) && (shift < 32));
1083
1084 if (shift >= 32)
1085 ctx->ptr_ok = 1;
1086
1087 if (ctx->ptr_ok)
1088 {
1089 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1090 }
1091 }
1092
1093 if (ctx->control & ETM_CTRL_TRACE_DATA)
1094 {
1095 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1096 {
1097 int i;
1098 for (i = 0; i < 16; i++)
1099 {
1100 if (instruction.info.load_store_multiple.register_list & (1 << i))
1101 {
1102 uint32_t data;
1103 if (etmv1_data(ctx, 4, &data) != 0)
1104 return ERROR_ETM_ANALYSIS_FAILED;
1105 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1106 }
1107 }
1108 }
1109 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1110 {
1111 uint32_t data;
1112 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1113 return ERROR_ETM_ANALYSIS_FAILED;
1114 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1115 }
1116 }
1117
1118 /* restore data index after consuming BD address and data */
1119 if (pipestat == STAT_BD)
1120 {
1121 ctx->data_index = new_data_index;
1122 ctx->data_half = new_data_half;
1123 }
1124 }
1125
1126 /* adjust PC */
1127 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1128 {
1129 if (((instruction.type == ARM_B) ||
1130 (instruction.type == ARM_BL) ||
1131 (instruction.type == ARM_BLX)) &&
1132 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1133 {
1134 next_pc = instruction.info.b_bl_bx_blx.target_address;
1135 }
1136 else
1137 {
1138 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1139 }
1140 }
1141 else if (pipestat == STAT_IN)
1142 {
1143 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1144 }
1145
1146 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1147 {
1148 char cycles_text[32] = "";
1149
1150 /* if the trace was captured with cycle accurate tracing enabled,
1151 * output the number of cycles since the last executed instruction
1152 */
1153 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1154 {
1155 snprintf(cycles_text, 32, " (%i %s)",
1156 (int)cycles,
1157 (cycles == 1) ? "cycle" : "cycles");
1158 }
1159
1160 command_print(cmd_ctx, "%s%s%s",
1161 instruction.text,
1162 (pipestat == STAT_IN) ? " (not executed)" : "",
1163 cycles_text);
1164
1165 ctx->current_pc = next_pc;
1166
1167 /* packets for an instruction don't start on or before the preceding
1168 * functional pipestat (i.e. other than WT or TD)
1169 */
1170 if (ctx->data_index <= ctx->pipe_index)
1171 {
1172 ctx->data_index = ctx->pipe_index + 1;
1173 ctx->data_half = 0;
1174 }
1175 }
1176
1177 ctx->pipe_index += 1;
1178 }
1179
1180 return ERROR_OK;
1181 }
1182
1183 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1184 uint32_t *mode)
1185 {
1186 uint32_t tracemode;
1187
1188 /* what parts of data access are traced? */
1189 if (strcmp(CMD_ARGV[0], "none") == 0)
1190 tracemode = 0;
1191 else if (strcmp(CMD_ARGV[0], "data") == 0)
1192 tracemode = ETM_CTRL_TRACE_DATA;
1193 else if (strcmp(CMD_ARGV[0], "address") == 0)
1194 tracemode = ETM_CTRL_TRACE_ADDR;
1195 else if (strcmp(CMD_ARGV[0], "all") == 0)
1196 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1197 else
1198 {
1199 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1200 return ERROR_INVALID_ARGUMENTS;
1201 }
1202
1203 uint8_t context_id;
1204 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1205 switch (context_id)
1206 {
1207 case 0:
1208 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1209 break;
1210 case 8:
1211 tracemode |= ETM_CTRL_CONTEXTID_8;
1212 break;
1213 case 16:
1214 tracemode |= ETM_CTRL_CONTEXTID_16;
1215 break;
1216 case 32:
1217 tracemode |= ETM_CTRL_CONTEXTID_32;
1218 break;
1219 default:
1220 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1221 return ERROR_INVALID_ARGUMENTS;
1222 }
1223
1224 bool etmv1_cycle_accurate;
1225 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1226 if (etmv1_cycle_accurate)
1227 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1228
1229 bool etmv1_branch_output;
1230 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1231 if (etmv1_branch_output)
1232 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1233
1234 /* IGNORED:
1235 * - CPRT tracing (coprocessor register transfers)
1236 * - debug request (causes debug entry on trigger)
1237 * - stall on FIFOFULL (preventing tracedata lossage)
1238 */
1239 *mode = tracemode;
1240
1241 return ERROR_OK;
1242 }
1243
1244 COMMAND_HANDLER(handle_etm_tracemode_command)
1245 {
1246 struct target *target = get_current_target(CMD_CTX);
1247 struct arm *arm = target_to_arm(target);
1248 struct etm_context *etm;
1249
1250 if (!is_arm(arm)) {
1251 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1252 return ERROR_FAIL;
1253 }
1254
1255 etm = arm->etm;
1256 if (!etm) {
1257 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1258 return ERROR_FAIL;
1259 }
1260
1261 uint32_t tracemode = etm->control;
1262
1263 switch (CMD_ARGC)
1264 {
1265 case 0:
1266 break;
1267 case 4:
1268 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1269 &tracemode);
1270 break;
1271 default:
1272 command_print(CMD_CTX, "usage: tracemode "
1273 "('none'|'data'|'address'|'all') "
1274 "context_id_bits "
1275 "('enable'|'disable') "
1276 "('enable'|'disable')"
1277 );
1278 return ERROR_FAIL;
1279 }
1280
1281 /**
1282 * todo: fail if parameters were invalid for this hardware,
1283 * or couldn't be written; display actual hardware state...
1284 */
1285
1286 command_print(CMD_CTX, "current tracemode configuration:");
1287
1288 switch (tracemode & ETM_CTRL_TRACE_MASK)
1289 {
1290 default:
1291 command_print(CMD_CTX, "data tracing: none");
1292 break;
1293 case ETM_CTRL_TRACE_DATA:
1294 command_print(CMD_CTX, "data tracing: data only");
1295 break;
1296 case ETM_CTRL_TRACE_ADDR:
1297 command_print(CMD_CTX, "data tracing: address only");
1298 break;
1299 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1300 command_print(CMD_CTX, "data tracing: address and data");
1301 break;
1302 }
1303
1304 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1305 {
1306 case ETM_CTRL_CONTEXTID_NONE:
1307 command_print(CMD_CTX, "contextid tracing: none");
1308 break;
1309 case ETM_CTRL_CONTEXTID_8:
1310 command_print(CMD_CTX, "contextid tracing: 8 bit");
1311 break;
1312 case ETM_CTRL_CONTEXTID_16:
1313 command_print(CMD_CTX, "contextid tracing: 16 bit");
1314 break;
1315 case ETM_CTRL_CONTEXTID_32:
1316 command_print(CMD_CTX, "contextid tracing: 32 bit");
1317 break;
1318 }
1319
1320 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1321 {
1322 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1323 }
1324 else
1325 {
1326 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1327 }
1328
1329 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1330 {
1331 command_print(CMD_CTX, "full branch address output enabled");
1332 }
1333 else
1334 {
1335 command_print(CMD_CTX, "full branch address output disabled");
1336 }
1337
1338 #define TRACEMODE_MASK ( \
1339 ETM_CTRL_CONTEXTID_MASK \
1340 | ETM_CTRL_BRANCH_OUTPUT \
1341 | ETM_CTRL_CYCLE_ACCURATE \
1342 | ETM_CTRL_TRACE_MASK \
1343 )
1344
1345 /* only update ETM_CTRL register if tracemode changed */
1346 if ((etm->control & TRACEMODE_MASK) != tracemode)
1347 {
1348 struct reg *etm_ctrl_reg;
1349
1350 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1351 if (!etm_ctrl_reg)
1352 return ERROR_FAIL;
1353
1354 etm->control &= ~TRACEMODE_MASK;
1355 etm->control |= tracemode & TRACEMODE_MASK;
1356
1357 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1358 etm_store_reg(etm_ctrl_reg);
1359
1360 /* invalidate old trace data */
1361 etm->capture_status = TRACE_IDLE;
1362 if (etm->trace_depth > 0)
1363 {
1364 free(etm->trace_data);
1365 etm->trace_data = NULL;
1366 }
1367 etm->trace_depth = 0;
1368 }
1369
1370 #undef TRACEMODE_MASK
1371
1372 return ERROR_OK;
1373 }
1374
1375 COMMAND_HANDLER(handle_etm_config_command)
1376 {
1377 struct target *target;
1378 struct arm *arm;
1379 uint32_t portmode = 0x0;
1380 struct etm_context *etm_ctx;
1381 int i;
1382
1383 if (CMD_ARGC != 5)
1384 return ERROR_COMMAND_SYNTAX_ERROR;
1385
1386 target = get_target(CMD_ARGV[0]);
1387 if (!target)
1388 {
1389 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1390 return ERROR_FAIL;
1391 }
1392
1393 arm = target_to_arm(target);
1394 if (!is_arm(arm)) {
1395 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1396 target_name(target),
1397 target_type_name(target));
1398 return ERROR_FAIL;
1399 }
1400
1401 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1402 * version we'll be using!! -- so we can't know how to validate
1403 * params yet. "etm config" should likely be *AFTER* hookup...
1404 *
1405 * - Many more widths might be supported ... and we can easily
1406 * check whether our setting "took".
1407 *
1408 * - The "clock" and "mode" bits are interpreted differently.
1409 * See ARM IHI 0014O table 2-17 for the old behavior, and
1410 * table 2-18 for the new. With ETB it's best to specify
1411 * "normal full" ...
1412 */
1413 uint8_t port_width;
1414 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1415 switch (port_width)
1416 {
1417 /* before ETMv3.0 */
1418 case 4:
1419 portmode |= ETM_PORT_4BIT;
1420 break;
1421 case 8:
1422 portmode |= ETM_PORT_8BIT;
1423 break;
1424 case 16:
1425 portmode |= ETM_PORT_16BIT;
1426 break;
1427 /* ETMv3.0 and later*/
1428 case 24:
1429 portmode |= ETM_PORT_24BIT;
1430 break;
1431 case 32:
1432 portmode |= ETM_PORT_32BIT;
1433 break;
1434 case 48:
1435 portmode |= ETM_PORT_48BIT;
1436 break;
1437 case 64:
1438 portmode |= ETM_PORT_64BIT;
1439 break;
1440 case 1:
1441 portmode |= ETM_PORT_1BIT;
1442 break;
1443 case 2:
1444 portmode |= ETM_PORT_2BIT;
1445 break;
1446 default:
1447 command_print(CMD_CTX,
1448 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1449 return ERROR_FAIL;
1450 }
1451
1452 if (strcmp("normal", CMD_ARGV[2]) == 0)
1453 {
1454 portmode |= ETM_PORT_NORMAL;
1455 }
1456 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1457 {
1458 portmode |= ETM_PORT_MUXED;
1459 }
1460 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1461 {
1462 portmode |= ETM_PORT_DEMUXED;
1463 }
1464 else
1465 {
1466 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1467 return ERROR_FAIL;
1468 }
1469
1470 if (strcmp("half", CMD_ARGV[3]) == 0)
1471 {
1472 portmode |= ETM_PORT_HALF_CLOCK;
1473 }
1474 else if (strcmp("full", CMD_ARGV[3]) == 0)
1475 {
1476 portmode |= ETM_PORT_FULL_CLOCK;
1477 }
1478 else
1479 {
1480 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1481 return ERROR_FAIL;
1482 }
1483
1484 etm_ctx = calloc(1, sizeof(struct etm_context));
1485 if (!etm_ctx) {
1486 LOG_DEBUG("out of memory");
1487 return ERROR_FAIL;
1488 }
1489
1490 for (i = 0; etm_capture_drivers[i]; i++)
1491 {
1492 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1493 {
1494 int retval = register_commands(CMD_CTX, NULL,
1495 etm_capture_drivers[i]->commands);
1496 if (ERROR_OK != retval)
1497 {
1498 free(etm_ctx);
1499 return retval;
1500 }
1501
1502 etm_ctx->capture_driver = etm_capture_drivers[i];
1503
1504 break;
1505 }
1506 }
1507
1508 if (!etm_capture_drivers[i])
1509 {
1510 /* no supported capture driver found, don't register an ETM */
1511 free(etm_ctx);
1512 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1513 return ERROR_FAIL;
1514 }
1515
1516 etm_ctx->target = target;
1517 etm_ctx->trace_data = NULL;
1518 etm_ctx->control = portmode;
1519 etm_ctx->core_state = ARM_STATE_ARM;
1520
1521 arm->etm = etm_ctx;
1522
1523 return etm_register_user_commands(CMD_CTX);
1524 }
1525
1526 COMMAND_HANDLER(handle_etm_info_command)
1527 {
1528 struct target *target;
1529 struct arm *arm;
1530 struct etm_context *etm;
1531 struct reg *etm_sys_config_reg;
1532 int max_port_size;
1533 uint32_t config;
1534
1535 target = get_current_target(CMD_CTX);
1536 arm = target_to_arm(target);
1537 if (!is_arm(arm))
1538 {
1539 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1540 return ERROR_FAIL;
1541 }
1542
1543 etm = arm->etm;
1544 if (!etm)
1545 {
1546 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1547 return ERROR_FAIL;
1548 }
1549
1550 command_print(CMD_CTX, "ETM v%d.%d",
1551 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1552 command_print(CMD_CTX, "pairs of address comparators: %i",
1553 (int) (etm->config >> 0) & 0x0f);
1554 command_print(CMD_CTX, "data comparators: %i",
1555 (int) (etm->config >> 4) & 0x0f);
1556 command_print(CMD_CTX, "memory map decoders: %i",
1557 (int) (etm->config >> 8) & 0x1f);
1558 command_print(CMD_CTX, "number of counters: %i",
1559 (int) (etm->config >> 13) & 0x07);
1560 command_print(CMD_CTX, "sequencer %spresent",
1561 (int) (etm->config & (1 << 16)) ? "" : "not ");
1562 command_print(CMD_CTX, "number of ext. inputs: %i",
1563 (int) (etm->config >> 17) & 0x07);
1564 command_print(CMD_CTX, "number of ext. outputs: %i",
1565 (int) (etm->config >> 20) & 0x07);
1566 command_print(CMD_CTX, "FIFO full %spresent",
1567 (int) (etm->config & (1 << 23)) ? "" : "not ");
1568 if (etm->bcd_vers < 0x20)
1569 command_print(CMD_CTX, "protocol version: %i",
1570 (int) (etm->config >> 28) & 0x07);
1571 else {
1572 command_print(CMD_CTX,
1573 "coprocessor and memory access %ssupported",
1574 (etm->config & (1 << 26)) ? "" : "not ");
1575 command_print(CMD_CTX, "trace start/stop %spresent",
1576 (etm->config & (1 << 26)) ? "" : "not ");
1577 command_print(CMD_CTX, "number of context comparators: %i",
1578 (int) (etm->config >> 24) & 0x03);
1579 }
1580
1581 /* SYS_CONFIG isn't present before ETMv1.2 */
1582 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1583 if (!etm_sys_config_reg)
1584 return ERROR_OK;
1585
1586 etm_get_reg(etm_sys_config_reg);
1587 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1588
1589 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1590
1591 max_port_size = config & 0x7;
1592 if (etm->bcd_vers >= 0x30)
1593 max_port_size |= (config >> 6) & 0x08;
1594 switch (max_port_size)
1595 {
1596 /* before ETMv3.0 */
1597 case 0:
1598 max_port_size = 4;
1599 break;
1600 case 1:
1601 max_port_size = 8;
1602 break;
1603 case 2:
1604 max_port_size = 16;
1605 break;
1606 /* ETMv3.0 and later*/
1607 case 3:
1608 max_port_size = 24;
1609 break;
1610 case 4:
1611 max_port_size = 32;
1612 break;
1613 case 5:
1614 max_port_size = 48;
1615 break;
1616 case 6:
1617 max_port_size = 64;
1618 break;
1619 case 8:
1620 max_port_size = 1;
1621 break;
1622 case 9:
1623 max_port_size = 2;
1624 break;
1625 default:
1626 LOG_ERROR("Illegal max_port_size");
1627 return ERROR_FAIL;
1628 }
1629 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1630
1631 if (etm->bcd_vers < 0x30) {
1632 command_print(CMD_CTX, "half-rate clocking %ssupported",
1633 (config & (1 << 3)) ? "" : "not ");
1634 command_print(CMD_CTX, "full-rate clocking %ssupported",
1635 (config & (1 << 4)) ? "" : "not ");
1636 command_print(CMD_CTX, "normal trace format %ssupported",
1637 (config & (1 << 5)) ? "" : "not ");
1638 command_print(CMD_CTX, "multiplex trace format %ssupported",
1639 (config & (1 << 6)) ? "" : "not ");
1640 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1641 (config & (1 << 7)) ? "" : "not ");
1642 } else {
1643 /* REVISIT show which size and format are selected ... */
1644 command_print(CMD_CTX, "current port size %ssupported",
1645 (config & (1 << 10)) ? "" : "not ");
1646 command_print(CMD_CTX, "current trace format %ssupported",
1647 (config & (1 << 11)) ? "" : "not ");
1648 }
1649 if (etm->bcd_vers >= 0x21)
1650 command_print(CMD_CTX, "fetch comparisons %ssupported",
1651 (config & (1 << 17)) ? "not " : "");
1652 command_print(CMD_CTX, "FIFO full %ssupported",
1653 (config & (1 << 8)) ? "" : "not ");
1654
1655 return ERROR_OK;
1656 }
1657
1658 COMMAND_HANDLER(handle_etm_status_command)
1659 {
1660 struct target *target;
1661 struct arm *arm;
1662 struct etm_context *etm;
1663 trace_status_t trace_status;
1664
1665 target = get_current_target(CMD_CTX);
1666 arm = target_to_arm(target);
1667 if (!is_arm(arm))
1668 {
1669 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1670 return ERROR_FAIL;
1671 }
1672
1673 etm = arm->etm;
1674 if (!etm)
1675 {
1676 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1677 return ERROR_FAIL;
1678 }
1679
1680 /* ETM status */
1681 if (etm->bcd_vers >= 0x11) {
1682 struct reg *reg;
1683
1684 reg = etm_reg_lookup(etm, ETM_STATUS);
1685 if (!reg)
1686 return ERROR_FAIL;
1687 if (etm_get_reg(reg) == ERROR_OK) {
1688 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1689
1690 command_print(CMD_CTX, "etm: %s%s%s%s",
1691 /* bit(1) == progbit */
1692 (etm->bcd_vers >= 0x12)
1693 ? ((s & (1 << 1))
1694 ? "disabled" : "enabled")
1695 : "?",
1696 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1697 ? " triggered" : "",
1698 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1699 ? " start/stop" : "",
1700 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1701 ? " untraced-overflow" : "");
1702 } /* else ignore and try showing trace port status */
1703 }
1704
1705 /* Trace Port Driver status */
1706 trace_status = etm->capture_driver->status(etm);
1707 if (trace_status == TRACE_IDLE)
1708 {
1709 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1710 }
1711 else
1712 {
1713 static char *completed = " completed";
1714 static char *running = " is running";
1715 static char *overflowed = ", overflowed";
1716 static char *triggered = ", triggered";
1717
1718 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1719 etm->capture_driver->name,
1720 (trace_status & TRACE_RUNNING) ? running : completed,
1721 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1722 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1723
1724 if (etm->trace_depth > 0)
1725 {
1726 command_print(CMD_CTX, "%i frames of trace data read",
1727 (int)(etm->trace_depth));
1728 }
1729 }
1730
1731 return ERROR_OK;
1732 }
1733
1734 COMMAND_HANDLER(handle_etm_image_command)
1735 {
1736 struct target *target;
1737 struct arm *arm;
1738 struct etm_context *etm_ctx;
1739
1740 if (CMD_ARGC < 1)
1741 {
1742 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1743 return ERROR_FAIL;
1744 }
1745
1746 target = get_current_target(CMD_CTX);
1747 arm = target_to_arm(target);
1748 if (!is_arm(arm))
1749 {
1750 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1751 return ERROR_FAIL;
1752 }
1753
1754 etm_ctx = arm->etm;
1755 if (!etm_ctx)
1756 {
1757 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1758 return ERROR_FAIL;
1759 }
1760
1761 if (etm_ctx->image)
1762 {
1763 image_close(etm_ctx->image);
1764 free(etm_ctx->image);
1765 command_print(CMD_CTX, "previously loaded image found and closed");
1766 }
1767
1768 etm_ctx->image = malloc(sizeof(struct image));
1769 etm_ctx->image->base_address_set = 0;
1770 etm_ctx->image->start_address_set = 0;
1771
1772 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1773 if (CMD_ARGC >= 2)
1774 {
1775 etm_ctx->image->base_address_set = 1;
1776 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1777 }
1778 else
1779 {
1780 etm_ctx->image->base_address_set = 0;
1781 }
1782
1783 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1784 {
1785 free(etm_ctx->image);
1786 etm_ctx->image = NULL;
1787 return ERROR_FAIL;
1788 }
1789
1790 return ERROR_OK;
1791 }
1792
1793 COMMAND_HANDLER(handle_etm_dump_command)
1794 {
1795 struct fileio file;
1796 struct target *target;
1797 struct arm *arm;
1798 struct etm_context *etm_ctx;
1799 uint32_t i;
1800
1801 if (CMD_ARGC != 1)
1802 {
1803 command_print(CMD_CTX, "usage: etm dump <file>");
1804 return ERROR_FAIL;
1805 }
1806
1807 target = get_current_target(CMD_CTX);
1808 arm = target_to_arm(target);
1809 if (!is_arm(arm))
1810 {
1811 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1812 return ERROR_FAIL;
1813 }
1814
1815 etm_ctx = arm->etm;
1816 if (!etm_ctx)
1817 {
1818 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1819 return ERROR_FAIL;
1820 }
1821
1822 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1823 {
1824 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1825 return ERROR_OK;
1826 }
1827
1828 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1829 {
1830 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1831 command_print(CMD_CTX, "trace capture not completed");
1832 return ERROR_FAIL;
1833 }
1834
1835 /* read the trace data if it wasn't read already */
1836 if (etm_ctx->trace_depth == 0)
1837 etm_ctx->capture_driver->read_trace(etm_ctx);
1838
1839 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1840 {
1841 return ERROR_FAIL;
1842 }
1843
1844 fileio_write_u32(&file, etm_ctx->capture_status);
1845 fileio_write_u32(&file, etm_ctx->control);
1846 fileio_write_u32(&file, etm_ctx->trace_depth);
1847
1848 for (i = 0; i < etm_ctx->trace_depth; i++)
1849 {
1850 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1851 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1852 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1853 }
1854
1855 fileio_close(&file);
1856
1857 return ERROR_OK;
1858 }
1859
1860 COMMAND_HANDLER(handle_etm_load_command)
1861 {
1862 struct fileio file;
1863 struct target *target;
1864 struct arm *arm;
1865 struct etm_context *etm_ctx;
1866 uint32_t i;
1867
1868 if (CMD_ARGC != 1)
1869 {
1870 command_print(CMD_CTX, "usage: etm load <file>");
1871 return ERROR_FAIL;
1872 }
1873
1874 target = get_current_target(CMD_CTX);
1875 arm = target_to_arm(target);
1876 if (!is_arm(arm))
1877 {
1878 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1879 return ERROR_FAIL;
1880 }
1881
1882 etm_ctx = arm->etm;
1883 if (!etm_ctx)
1884 {
1885 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1886 return ERROR_FAIL;
1887 }
1888
1889 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1890 {
1891 command_print(CMD_CTX, "trace capture running, stop first");
1892 return ERROR_FAIL;
1893 }
1894
1895 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1896 {
1897 return ERROR_FAIL;
1898 }
1899
1900 if (file.size % 4)
1901 {
1902 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1903 fileio_close(&file);
1904 return ERROR_FAIL;
1905 }
1906
1907 if (etm_ctx->trace_depth > 0)
1908 {
1909 free(etm_ctx->trace_data);
1910 etm_ctx->trace_data = NULL;
1911 }
1912
1913 {
1914 uint32_t tmp;
1915 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1916 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1917 fileio_read_u32(&file, &etm_ctx->trace_depth);
1918 }
1919 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1920 if (etm_ctx->trace_data == NULL)
1921 {
1922 command_print(CMD_CTX, "not enough memory to perform operation");
1923 fileio_close(&file);
1924 return ERROR_FAIL;
1925 }
1926
1927 for (i = 0; i < etm_ctx->trace_depth; i++)
1928 {
1929 uint32_t pipestat, packet, flags;
1930 fileio_read_u32(&file, &pipestat);
1931 fileio_read_u32(&file, &packet);
1932 fileio_read_u32(&file, &flags);
1933 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1934 etm_ctx->trace_data[i].packet = packet & 0xffff;
1935 etm_ctx->trace_data[i].flags = flags;
1936 }
1937
1938 fileio_close(&file);
1939
1940 return ERROR_OK;
1941 }
1942
1943 COMMAND_HANDLER(handle_etm_start_command)
1944 {
1945 struct target *target;
1946 struct arm *arm;
1947 struct etm_context *etm_ctx;
1948 struct reg *etm_ctrl_reg;
1949
1950 target = get_current_target(CMD_CTX);
1951 arm = target_to_arm(target);
1952 if (!is_arm(arm))
1953 {
1954 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1955 return ERROR_FAIL;
1956 }
1957
1958 etm_ctx = arm->etm;
1959 if (!etm_ctx)
1960 {
1961 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1962 return ERROR_FAIL;
1963 }
1964
1965 /* invalidate old tracing data */
1966 etm_ctx->capture_status = TRACE_IDLE;
1967 if (etm_ctx->trace_depth > 0)
1968 {
1969 free(etm_ctx->trace_data);
1970 etm_ctx->trace_data = NULL;
1971 }
1972 etm_ctx->trace_depth = 0;
1973
1974 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1975 if (!etm_ctrl_reg)
1976 return ERROR_FAIL;
1977
1978 etm_get_reg(etm_ctrl_reg);
1979
1980 /* Clear programming bit (10), set port selection bit (11) */
1981 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1982
1983 etm_store_reg(etm_ctrl_reg);
1984 jtag_execute_queue();
1985
1986 etm_ctx->capture_driver->start_capture(etm_ctx);
1987
1988 return ERROR_OK;
1989 }
1990
1991 COMMAND_HANDLER(handle_etm_stop_command)
1992 {
1993 struct target *target;
1994 struct arm *arm;
1995 struct etm_context *etm_ctx;
1996 struct reg *etm_ctrl_reg;
1997
1998 target = get_current_target(CMD_CTX);
1999 arm = target_to_arm(target);
2000 if (!is_arm(arm))
2001 {
2002 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2003 return ERROR_FAIL;
2004 }
2005
2006 etm_ctx = arm->etm;
2007 if (!etm_ctx)
2008 {
2009 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2010 return ERROR_FAIL;
2011 }
2012
2013 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2014 if (!etm_ctrl_reg)
2015 return ERROR_FAIL;
2016
2017 etm_get_reg(etm_ctrl_reg);
2018
2019 /* Set programming bit (10), clear port selection bit (11) */
2020 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2021
2022 etm_store_reg(etm_ctrl_reg);
2023 jtag_execute_queue();
2024
2025 etm_ctx->capture_driver->stop_capture(etm_ctx);
2026
2027 return ERROR_OK;
2028 }
2029
2030 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2031 {
2032 struct target *target;
2033 struct arm *arm;
2034 struct etm_context *etm;
2035
2036 target = get_current_target(CMD_CTX);
2037 arm = target_to_arm(target);
2038 if (!is_arm(arm))
2039 {
2040 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2041 target_name(target));
2042 return ERROR_FAIL;
2043 }
2044
2045 etm = arm->etm;
2046 if (!etm)
2047 {
2048 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2049 target_name(target));
2050 return ERROR_FAIL;
2051 }
2052
2053 if (CMD_ARGC == 1) {
2054 struct reg *etm_ctrl_reg;
2055 bool dbgrq;
2056
2057 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2058 if (!etm_ctrl_reg)
2059 return ERROR_FAIL;
2060
2061 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2062 if (dbgrq)
2063 etm->control |= ETM_CTRL_DBGRQ;
2064 else
2065 etm->control &= ~ETM_CTRL_DBGRQ;
2066
2067 /* etm->control will be written to hardware
2068 * the next time an "etm start" is issued.
2069 */
2070 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2071 }
2072
2073 command_print(CMD_CTX, "ETM: %s debug halt",
2074 (etm->control & ETM_CTRL_DBGRQ)
2075 ? "triggers"
2076 : "does not trigger");
2077 return ERROR_OK;
2078 }
2079
2080 COMMAND_HANDLER(handle_etm_analyze_command)
2081 {
2082 struct target *target;
2083 struct arm *arm;
2084 struct etm_context *etm_ctx;
2085 int retval;
2086
2087 target = get_current_target(CMD_CTX);
2088 arm = target_to_arm(target);
2089 if (!is_arm(arm))
2090 {
2091 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2092 return ERROR_FAIL;
2093 }
2094
2095 etm_ctx = arm->etm;
2096 if (!etm_ctx)
2097 {
2098 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2099 return ERROR_FAIL;
2100 }
2101
2102 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2103 {
2104 switch (retval)
2105 {
2106 case ERROR_ETM_ANALYSIS_FAILED:
2107 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2108 break;
2109 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2110 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2111 break;
2112 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2113 command_print(CMD_CTX, "no image available for trace analysis");
2114 break;
2115 default:
2116 command_print(CMD_CTX, "unknown error: %i", retval);
2117 }
2118 }
2119
2120 return retval;
2121 }
2122
2123 static const struct command_registration etm_config_command_handlers[] = {
2124 {
2125 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2126 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2127 *
2128 * Also, these parameters don't match ETM v3+ modules...
2129 */
2130 .name = "config",
2131 .handler = handle_etm_config_command,
2132 .mode = COMMAND_CONFIG,
2133 .help = "Set up ETM output port.",
2134 .usage = "target port_width port_mode clocking capture_driver",
2135 },
2136 COMMAND_REGISTRATION_DONE
2137 };
2138 const struct command_registration etm_command_handlers[] = {
2139 {
2140 .name = "etm",
2141 .mode = COMMAND_ANY,
2142 .help = "Emebdded Trace Macrocell command group",
2143 .chain = etm_config_command_handlers,
2144 },
2145 COMMAND_REGISTRATION_DONE
2146 };
2147
2148 static const struct command_registration etm_exec_command_handlers[] = {
2149 {
2150 .name = "tracemode",
2151 .handler = handle_etm_tracemode_command,
2152 .mode = COMMAND_EXEC,
2153 .help = "configure/display trace mode",
2154 .usage = "('none'|'data'|'address'|'all') "
2155 "context_id_bits "
2156 "['enable'|'disable'] "
2157 "['enable'|'disable']",
2158 },
2159 {
2160 .name = "info",
2161 .handler = handle_etm_info_command,
2162 .mode = COMMAND_EXEC,
2163 .help = "display info about the current target's ETM",
2164 },
2165 {
2166 .name = "status",
2167 .handler = handle_etm_status_command,
2168 .mode = COMMAND_EXEC,
2169 .help = "display current target's ETM status",
2170 },
2171 {
2172 .name = "start",
2173 .handler = handle_etm_start_command,
2174 .mode = COMMAND_EXEC,
2175 .help = "start ETM trace collection",
2176 },
2177 {
2178 .name = "stop",
2179 .handler = handle_etm_stop_command,
2180 .mode = COMMAND_EXEC,
2181 .help = "stop ETM trace collection",
2182 },
2183 {
2184 .name = "trigger_debug",
2185 .handler = handle_etm_trigger_debug_command,
2186 .mode = COMMAND_EXEC,
2187 .help = "enable/disable debug entry on trigger",
2188 .usage = "['enable'|'disable']",
2189 },
2190 {
2191 .name = "analyze",
2192 .handler = handle_etm_analyze_command,
2193 .mode = COMMAND_EXEC,
2194 .help = "analyze collected ETM trace",
2195 },
2196 {
2197 .name = "image",
2198 .handler = handle_etm_image_command,
2199 .mode = COMMAND_EXEC,
2200 .help = "load image from file with optional offset",
2201 .usage = "filename [offset]",
2202 },
2203 {
2204 .name = "dump",
2205 .handler = handle_etm_dump_command,
2206 .mode = COMMAND_EXEC,
2207 .help = "dump captured trace data to file",
2208 .usage = "filename",
2209 },
2210 {
2211 .name = "load",
2212 .handler = handle_etm_load_command,
2213 .mode = COMMAND_EXEC,
2214 .help = "load trace data for analysis <file>",
2215 },
2216 COMMAND_REGISTRATION_DONE
2217 };
2218
2219 static int etm_register_user_commands(struct command_context *cmd_ctx)
2220 {
2221 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2222 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2223 }
OpenOCD fork with SWD works