src/target/dsp5680xx.h

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Rodrigo L. Rosa                                 *
   3  *   rodrigorosa.LG@gmail.com                                              *
   4  *                                                                         *
   5  *   Based on dsp563xx_once.h written by Mathias Kuester                   *
   6  *   mkdorg@users.sourceforge.net                                          *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef DSP5680XX_H
  24 #define DSP5680XX_H
  25
  26 #include <jtag/jtag.h>
  27
  28 #define S_FILE_DATA_OFFSET 0x200000
  29
  30 //----------------------------------------------------------------
  31 // JTAG
  32 //----------------------------------------------------------------
  33 #define DSP5680XX_JTAG_CORE_TAP_IRLEN   4
  34 #define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
  35
  36 #define JTAG_STATUS_MASK                0x03
  37
  38 #define JTAG_STATUS_NORMAL              0x01
  39 #define JTAG_STATUS_STOPWAIT            0x05
  40 #define JTAG_STATUS_BUSY                0x09
  41 #define JTAG_STATUS_DEBUG               0x0D
  42 #define JTAG_STATUS_DEAD                0x0f
  43
  44 #define JTAG_INSTR_EXTEST               0x0
  45 #define JTAG_INSTR_SAMPLE_PRELOAD       0x1
  46 #define JTAG_INSTR_IDCODE               0x2
  47 #define JTAG_INSTR_EXTEST_PULLUP        0x3
  48 #define JTAG_INSTR_HIGHZ                0x4
  49 #define JTAG_INSTR_CLAMP                0x5
  50 #define JTAG_INSTR_ENABLE_ONCE          0x6
  51 #define JTAG_INSTR_DEBUG_REQUEST        0x7
  52 #define JTAG_INSTR_BYPASS               0xF
  53 //----------------------------------------------------------------
  54
  55
  56 //----------------------------------------------------------------
  57 // Master TAP instructions from MC56F8000RM.pdf
  58 //----------------------------------------------------------------
  59 #define MASTER_TAP_CMD_BYPASS      0xFF
  60 #define MASTER_TAP_CMD_IDCODE      0x02
  61 #define MASTER_TAP_CMD_TLM_SEL     0x05
  62 #define MASTER_TAP_CMD_FLASH_ERASE 0x08
  63 //----------------------------------------------------------------
  64
  65 //----------------------------------------------------------------
  66 // EOnCE control register info
  67 //----------------------------------------------------------------
  68 #define DSP5680XX_ONCE_OCR_EX   (1<<5)
  69 /* EX Bit Definition
  70         0 Remain in the Debug Processing State
  71         1 Leave the Debug Processing State */
  72 #define DSP5680XX_ONCE_OCR_GO   (1<<6)
  73 /* GO Bit Definition
  74         0 Inactive—No Action Taken
  75         1 Execute Controller Instruction */
  76 #define DSP5680XX_ONCE_OCR_RW   (1<<7)
  77 /* RW Bit Definition
  78         0 Write To the Register Specified by the RS[4:0] Bits
  79         1 ReadFrom the Register Specified by the RS[4:0] Bits */
  80 //----------------------------------------------------------------
  81
  82 //----------------------------------------------------------------
  83 // EOnCE Status Register
  84 //----------------------------------------------------------------
  85 #define DSP5680XX_ONCE_OSCR_OS1         (1<<5)
  86 #define DSP5680XX_ONCE_OSCR_OS0         (1<<4)
  87 //----------------------------------------------------------------
  88
  89 //----------------------------------------------------------------
  90 // EOnCE Core Status - Describes the operating status of the core controller
  91 //----------------------------------------------------------------
  92 #define DSP5680XX_ONCE_OSCR_NORMAL_M    (0)
  93 //00  -   Normal      -   Controller Core Executing Instructions or in Reset
  94 #define DSP5680XX_ONCE_OSCR_STOPWAIT_M  (DSP5680XX_ONCE_OSCR_OS0)
  95 //01  -   Stop/Wait   -   Controller Core in Stop or Wait Mode
  96 #define DSP5680XX_ONCE_OSCR_BUSY_M      (DSP5680XX_ONCE_OSCR_OS1)
  97 //10  -   Busy        -   Controller is Performing External or Peripheral Access (Wait States)
  98 #define DSP5680XX_ONCE_OSCR_DEBUG_M     (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
  99 //11  -   Debug       -   Controller Core Halted and in Debug Mode
 100 #define EONCE_STAT_MASK 0x30
 101 //----------------------------------------------------------------
 102
 103 //----------------------------------------------------------------
 104 // Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
 105 //----------------------------------------------------------------
 106 #define DSP5680XX_ONCE_NOREG    0x00 /* No register selected */
 107 #define DSP5680XX_ONCE_OCR      0x01 /* OnCE Debug Control Register */
 108 #define DSP5680XX_ONCE_OCNTR    0x02 /* OnCE Breakpoint and Trace Counter */
 109 #define DSP5680XX_ONCE_OSR      0x03 /* EOnCE status register */
 110 #define DSP5680XX_ONCE_OBAR     0x04 /* OnCE Breakpoint Address Register */
 111 #define DSP5680XX_ONCE_OBASE    0x05 /* EOnCE Peripheral Base Address register */
 112 #define DSP5680XX_ONCE_OTXRXSR  0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR)  */
 113 #define DSP5680XX_ONCE_OTX      0x07 /* EOnCE Transmit register (OTX)  */
 114 #define DSP5680XX_ONCE_OPDBR    0x08 /* EOnCE Program Data Bus Register (OPDBR) */
 115 #define DSP5680XX_ONCE_OTX1     0x09 /* EOnCE Upper Transmit register (OTX1) */
 116 #define DSP5680XX_ONCE_OPABFR   0x0A /* OnCE Program Address Register—Fetch cycle */
 117 #define DSP5680XX_ONCE_ORX      0x0B /* EOnCE Receive register (ORX) */
 118 #define DSP5680XX_ONCE_OCNTR_C  0x0C /* Clear OCNTR */
 119 #define DSP5680XX_ONCE_ORX1     0x0D /* EOnCE Upper Receive register (ORX1) */
 120 #define DSP5680XX_ONCE_OTBCR    0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
 121 #define DSP5680XX_ONCE_OPABER   0x10 /* OnCE Program Address Register—Execute cycle */
 122 #define DSP5680XX_ONCE_OPFIFO   0x11 /* OnCE Program address FIFO */
 123 #define DSP5680XX_ONCE_OBAR1    0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
 124 #define DSP5680XX_ONCE_OPABDR   0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
 125 //----------------------------------------------------------------
 126
 127 #define FLUSH_COUNT_WRITE 4095 // This value works, higher values (and lower...) may work as well.
 128 #define FLUSH_COUNT_FLASH 7 // Waiting for longer queues will cause flashing errors.
 129 //----------------------------------------------------------------
 130 // HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
 131 //----------------------------------------------------------------
 132 #define HFM_ERASE_VERIFY                  0x05
 133 #define HFM_CALCULATE_DATA_SIGNATURE      0x06
 134 #define HFM_WORD_PROGRAM                  0x20
 135 #define HFM_PAGE_ERASE                    0x40
 136 #define HFM_MASS_ERASE                    0x41
 137 #define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
 138 //----------------------------------------------------------------
 139
 140 //----------------------------------------------------------------
 141 // Flashing (ref:MC56F801xRM.pdf@159)
 142 //----------------------------------------------------------------
 143 #define HFM_BASE_ADDR     0x0F400 // In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR to get data into x: mem.)
 144 // The following are register addresses, not memory addresses (though all registers are memory mapped)
 145 #define HFM_CLK_DIV       0x00 // r/w
 146 #define HFM_CNFG          0x01 // r/w
 147 #define HFM_SECHI         0x03 // r
 148 #define HFM_SECLO         0x04 // r
 149 #define HFM_PROT          0x10 // r/w
 150 #define HFM_PROTB         0x11 // r/w
 151 #define HFM_USTAT         0x13 // r/w
 152 #define HFM_CMD           0x14 // r/w
 153 #define HFM_DATA          0x18 // r
 154 #define HFM_OPT1          0x1B // r
 155 #define HFM_TSTSIG        0x1D // r
 156
 157 #define HFM_EXEC_COMPLETE  0x40
 158
 159 // User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5)
 160 #define HFM_USTAT_MASK_BLANK 0x4
 161 #define HFM_USTAT_MASK_PVIOL_ACCER 0x30
 162
 163 #define HFM_CLK_DEFAULT 0x29
 164 #define HFM_FLASH_BASE_ADDR 0x0
 165 #define HFM_SIZE 0x8000 // This is not true for 56F8013, but it is necessary to get the byte/word addressing workaround to actually work.
 166 #define HFM_SIZE_REAL 0x2000
 167 #define HFM_SECTOR_SIZE 0x8000 // 512 bytes pages.
 168 #define HFM_SECTOR_COUNT 1
 169
 170 #define HFM_LOCK_FLASH 0xE70A
 171 #define HFM_LOCK_ADDR_L 0x1FF7
 172 #define HFM_LOCK_ADDR_H 0x1FF8
 173 // Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
 174 //----------------------------------------------------------------
 175
 176 //----------------------------------------------------------------
 177 // Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
 178 //----------------------------------------------------------------
 179 #define MC568013_EONCE_OBASE_ADDR 0xFF
 180 // The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
 181 #define MC568013_EONCE_TX_RX_ADDR    0xFFFE //
 182 #define MC568013_EONCE_TX1_RX1_HIGH_ADDR  0xFFFF // Relative to EONCE_OBASE_ADDR
 183 #define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
 184 //----------------------------------------------------------------
 185
 186 //----------------------------------------------------------------
 187 // SIM addresses & commands (MC56F80xx.h from freescale)
 188 //----------------------------------------------------------------
 189 #define MC568013_SIM_BASE_ADDR 0xF140
 190 #define MC56803x_2x_SIM_BASE_ADDR 0xF100
 191
 192 #define SIM_CMD_RESET 0x10
 193 //----------------------------------------------------------------
 194
 195 struct dsp5680xx_common{
 196   //TODO
 197   uint32_t stored_pc;
 198   int flush;
 199 }context;
 200
 201 static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target){
 202   return target->arch_info;
 203 }
 204
 205 int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count);
 206
 207 int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased);
 208 int dsp5680xx_f_erase(struct target * target, int first, int last);
 209 int dsp5680xx_f_protect_check(struct target * target, uint8_t * protected);
 210 int dsp5680xx_f_lock(struct target * target);
 211 int dsp5680xx_f_unlock(struct target * target);
 212
 213 #endif // dsp5680xx.h