1 # Generic init scripts for all ST SPEAr3xx family
2 # http://www.st.com/spear
5 # Author: Antonio Borneo <borneo.antonio@gmail.com>
8 # Initialize internal clock
14 # - DDR_CLK = 332 MHz async
17 proc sp3xx_clock_default
{} {
18 mww
0xfca00000 0x00000002 ;# set sysclk slow
19 mww
0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
21 # DDRCORE disable to change frequency
22 set val
[expr ([mrw
0xfca8002c] & ~
0x20000000) |
0x40000000]
24 mww
0xfca8002c $val ;# Yes, write twice!
27 mww
0xfca8000c 0xa600010c ;# M=166 P=1 N=12
28 mww
0xfca80008 0x00001c0a ;# power down
29 mww
0xfca80008 0x00001c0e ;# enable
30 mww
0xfca80008 0x00001c06 ;# strobe
31 mww
0xfca80008 0x00001c0e
32 while { [expr [mrw
0xfca80008] & 0x01] == 0x00 } { sleep
1 }
35 mww
0xfca80018 0xa600010c ;# M=166, P=1, N=12
36 mww
0xfca80014 0x00001c0a ;# power down
37 mww
0xfca80014 0x00001c0e ;# enable
38 mww
0xfca80014 0x00001c06 ;# strobe
39 mww
0xfca80014 0x00001c0e
40 while { [expr [mrw
0xfca80014] & 0x01] == 0x00 } { sleep
1 }
42 mww
0xfca80028 0x00000082 ;# enable plltimeen
43 mww
0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
45 mww
0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
46 while { [expr [mrw
0xfca00000] & 0x20] != 0x20 } { sleep
1 }
48 # Select source of DDR clock
49 #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
50 mmw
0xfca80020 0x30000000 0x70000000 ;# PLL2
52 # DDRCORE enable after change frequency
53 mmw
0xfca8002c 0x20000000 0x00000000
56 proc sp3xx_common_init
{} {
57 mww
0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
58 mww
0xfca80038 0x00000000 ;# remove reset of all peripherals
60 mww
0xfca80034 0x0000ffff ;# enable all RAS clocks
61 mww
0xfca80040 0x00000000 ;# remove all RAS resets
63 mww
0xfca800e4 0x78000008 ;# COMP1V8_REG
64 mww
0xfca800ec 0x78000008 ;# COMP3V3_REG
66 mww
0xfc000000 0x10000f5f ;# init SMI and set HW mode
67 mww
0xfc000000 0x00000f5f
69 # Initialize Bus Interconnection Matrix
70 # All ports Round-Robin and lowest priority
71 mww
0xfca8007c 0x80000007
72 mww
0xfca80080 0x80000007
73 mww
0xfca80084 0x80000007
74 mww
0xfca80088 0x80000007
75 mww
0xfca8008c 0x80000007
76 mww
0xfca80090 0x80000007
77 mww
0xfca80094 0x80000007
78 mww
0xfca80098 0x80000007
79 mww
0xfca8009c 0x80000007
83 # Specific init scripts for ST SPEAr310 system on chip
85 mww
0xb4000008 0x00002ff4 ;# RAS function enable
87 mww
0xfca80050 0x00000001 ;# Enable clk mem port 1
89 mww
0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
90 mww
0xfca80140 0x017bdef6
93 proc sp310_emi_init
{} {
94 # set EMI pad strength
95 mmw
0xfca80134 0x0e000000 0x00000000
96 mmw
0xfca80138 0x0e739ce7 0x00000000
97 mmw
0xfca8013c 0x00039ce7 0x00000000
99 # set safe EMI timing as in BootROM
100 #mww 0x4f000000 0x0000000f ;# tAP_0_reg
101 #mww 0x4f000004 0x00000000 ;# tSDP_0_reg
102 #mww 0x4f000008 0x000000ff ;# tDPw_0_reg
103 #mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
104 #mww 0x4f000010 0x00000002 ;# tDCS_0_reg
106 # set fast EMI timing as in Linux
107 mww
0x4f000000 0x00000010 ;# tAP_0_reg
108 mww
0x4f000004 0x00000005 ;# tSDP_0_reg
109 mww
0x4f000008 0x0000000a ;# tDPw_0_reg
110 mww
0x4f00000c 0x0000000a ;# tDPr_0_reg
111 mww
0x4f000010 0x00000005 ;# tDCS_0_re
113 # 32bit wide, 8/16/32bit access
114 mww
0x4f000014 0x0000000e ;# control_0_reg
115 mww
0x4f000094 0x0000003f ;# ack_reg