src/jtag/swd.h

   1 //
   2
   3 /* Bits in SWD command packets, written from host to target
   4  * first bit on the wire is START
   5  */
   6 #define SWD_CMD_START   (1 << 0)        /* always set */
   7 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
   8 #define SWD_CMD_RnW     (1 << 2)        /* set only for read access */
   9 #define SWD_CMD_A32     (3 << 3)        /* bits A[3:2] of register addr */
  10 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  11 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  12 #define SWD_CMD_PARK    (0 << 7)        /* not driven by host (pull high) */
  13 /* followed by TRN, 3-bits of ACK, TRN */
  14
  15 /* pbit16 holds precomputed parity bits for each nibble */
  16 #define pbit(parity, nibble) (parity << nibble)
  17
  18 static const uint16_t pbit16 =
  19         pbit(0, 0) | pbit(1, 1) | pbit(1, 2) | pbit(0, 3)
  20         | pbit(1, 4) | pbit(0, 5) | pbit(0, 6) | pbit(1, 7)
  21         | pbit(1, 8) | pbit(0, 9) | pbit(0, 0xa) | pbit(1, 0xb)
  22         | pbit(0, 0xc) | pbit(1, 0xd) | pbit(1, 0xe) | pbit(0, 0xf);
  23
  24 #define nibble_parity(nibble) (pbit16 & pbit(1, nibble))
  25
  26 /**
  27  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  28  * and swd_driver.write_reg() methods will use directly.
  29  */
  30 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  31 {
  32         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  33                 | (is_read ? SWD_CMD_RnW : 0)
  34                 | ((regnum & 0xc) << 1);
  35
  36         //8 cmd bits 4:1 may be set
  37         if (nibble_parity(cmd >> 1))
  38                 cmd |= SWD_CMD_PARITY;
  39
  40         /* driver handles START, STOP, and TRN */
  41
  42         return cmd;
  43 }
  44
  45 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  46
  47 /*
  48  * FOR NOW  ... SWD driver ops are synchronous and return ACK
  49  * status ... no quueueing.
  50  *
  51  * Individual ops are request/response, and fast-fail permits much
  52  * better fault handling.  Upper layers may queue if desired.
  53  */
  54
  55 struct swd_driver {
  56         /**
  57          * Initialize the debug link so it can perform
  58          * synchronous SWD operations.
  59          * @param trn value from WCR: how many clocks
  60          * to not drive the SWDIO line at certain points in
  61          * the SWD protocol (at least 1 clock).
  62          *
  63          * As an example, this would switch a dual-mode debug adapter
  64          * into SWD mode and out of JTAG mode.
  65           *
  66           * @return ERROR_OK on success, else a negative fault code.
  67          */
  68         int (*init)(uint8_t trn);
  69
  70
  71          /**
  72           * Synchronous read of an AP or DP register.
  73           *
  74           * @param cmd with APnDP/RnW/addr/parity bits
  75           * @param where to store value to read from register
  76           *
  77           * @return SWD_ACK_* code for the transaction
  78           *     or (negative) fault code
  79           */
  80          int (*read_reg)(uint8_t cmd, uint32_t *value);
  81
  82          /**
  83           * Synchronous write of an AP or DP register.
  84           *
  85           * @param cmd with APnDP/RnW/addr/parity bits
  86           * @param value to be written to the register
  87           *
  88           * @return SWD_ACK_* code for the transaction
  89           *     or (negative) fault code
  90           */
  91          int (*write_reg)(uint8_t cmd, uint32_t value);
  92
  93         /* XXX START WITH enough to:
  94          *      init (synch mode, WCR)
  95          *              for async, TRN > 1
  96          *      read IDCODE from DP
  97          */
  98
  99         /**
 100          * Configures data collection from the Single-wire
 101          * trace (SWO) signal.
 102          * @param swo true if SWO data collection should be routed.
 103          *
 104          * For example,  some debug adapters include a UART which
 105          * is normally connected to a microcontroller's UART TX,
 106          * but which may instead be connected to SWO for use in
 107          * collecting ITM (and possibly ETM) trace data.
 108           *
 109           * @return ERROR_OK on success, else a negative fault code.
 110          */
 111         int *(*trace)(bool swo);
 112 };
 113
 114 bool transport_is_swd(void);