1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "jtag/interface.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
77 /* These two below are to be removed when transport is finished... */
78 extern const struct dap_ops jtag_dap_ops
;
79 extern struct jtag_interface
*jtag_interface
;
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
89 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
92 /***************************************************************************
94 * DP and MEM-AP register access through APACC and DPACC *
96 ***************************************************************************/
99 * Select one of the APs connected to the specified DAP. The
100 * selection is implicitly used with future AP transactions.
101 * This is a NOP if the specified AP is already selected.
104 * @param apsel Number of the AP to (implicitly) use with further
105 * transactions. This normally identifies a MEM-AP.
107 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
109 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
111 if (new_ap
!= dap
->ap_current
) {
112 dap
->ap_current
= new_ap
;
113 /* Switching AP invalidates cached values.
114 * Values MUST BE UPDATED BEFORE AP ACCESS.
116 dap
->ap_bank_value
= -1;
117 dap
->ap_csw_value
= -1;
118 dap
->ap_tar_value
= -1;
123 * Queue transactions setting up transfer parameters for the
124 * currently selected MEM-AP.
126 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
127 * initiate data reads or writes using memory or peripheral addresses.
128 * If the CSW is configured for it, the TAR may be automatically
129 * incremented after each transfer.
131 * @todo Rename to reflect it being specifically a MEM-AP function.
133 * @param dap The DAP connected to the MEM-AP.
134 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
135 * matches the cached value, the register is not changed.
136 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
137 * matches the cached address, the register is not changed.
139 * @return ERROR_OK if the transaction was properly queued, else a fault code.
141 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
145 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
146 if (csw
!= dap
->ap_csw_value
) {
147 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
148 retval
= dap_queue_ap_write(dap
, AP_REG_CSW
, csw
);
149 if (retval
!= ERROR_OK
)
151 dap
->ap_csw_value
= csw
;
153 if (tar
!= dap
->ap_tar_value
) {
154 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
155 retval
= dap_queue_ap_write(dap
, AP_REG_TAR
, tar
);
156 if (retval
!= ERROR_OK
)
158 dap
->ap_tar_value
= tar
;
160 /* Disable TAR cache when autoincrementing */
161 if (csw
& CSW_ADDRINC_MASK
)
162 dap
->ap_tar_value
= -1;
167 * Asynchronous (queued) read of a word from memory or a system register.
169 * @param dap The DAP connected to the MEM-AP performing the read.
170 * @param address Address of the 32-bit word to read; it must be
171 * readable by the currently selected MEM-AP.
172 * @param value points to where the word will be stored when the
173 * transaction queue is flushed (assuming no errors).
175 * @return ERROR_OK for success. Otherwise a fault code.
177 int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
182 /* Use banked addressing (REG_BDx) to avoid some link traffic
183 * (updating TAR) when reading several consecutive addresses.
185 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
186 address
& 0xFFFFFFF0);
187 if (retval
!= ERROR_OK
)
190 return dap_queue_ap_read(dap
, AP_REG_BD0
| (address
& 0xC), value
);
194 * Synchronous read of a word from memory or a system register.
195 * As a side effect, this flushes any queued transactions.
197 * @param dap The DAP connected to the MEM-AP performing the read.
198 * @param address Address of the 32-bit word to read; it must be
199 * readable by the currently selected MEM-AP.
200 * @param value points to where the result will be stored.
202 * @return ERROR_OK for success; *value holds the result.
203 * Otherwise a fault code.
205 int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
210 retval
= mem_ap_read_u32(dap
, address
, value
);
211 if (retval
!= ERROR_OK
)
218 * Asynchronous (queued) write of a word to memory or a system register.
220 * @param dap The DAP connected to the MEM-AP.
221 * @param address Address to be written; it must be writable by
222 * the currently selected MEM-AP.
223 * @param value Word that will be written to the address when transaction
224 * queue is flushed (assuming no errors).
226 * @return ERROR_OK for success. Otherwise a fault code.
228 int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
233 /* Use banked addressing (REG_BDx) to avoid some link traffic
234 * (updating TAR) when writing several consecutive addresses.
236 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
237 address
& 0xFFFFFFF0);
238 if (retval
!= ERROR_OK
)
241 return dap_queue_ap_write(dap
, AP_REG_BD0
| (address
& 0xC),
246 * Synchronous write of a word to memory or a system register.
247 * As a side effect, this flushes any queued transactions.
249 * @param dap The DAP connected to the MEM-AP.
250 * @param address Address to be written; it must be writable by
251 * the currently selected MEM-AP.
252 * @param value Word that will be written.
254 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
256 int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
259 int retval
= mem_ap_write_u32(dap
, address
, value
);
261 if (retval
!= ERROR_OK
)
267 /*****************************************************************************
269 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
271 * Write a buffer in target order (little endian) *
273 *****************************************************************************/
274 int mem_ap_write_buf_u32(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
276 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
277 uint32_t adr
= address
;
278 const uint8_t *pBuffer
= buffer
;
283 /* if we have an unaligned access - reorder data */
285 for (writecount
= 0; writecount
< count
; writecount
++) {
288 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
290 for (i
= 0; i
< 4; i
++) {
291 *((uint8_t *)pBuffer
+ (adr
& 0x3)) = outvalue
;
295 pBuffer
+= sizeof(uint32_t);
300 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
301 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
302 if (wcount
< blocksize
)
305 /* handle unaligned data at 4k boundary */
309 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
310 if (retval
!= ERROR_OK
)
313 for (writecount
= 0; writecount
< blocksize
; writecount
++) {
315 tmp
= buf_get_u32(buffer
+ 4 * writecount
, 0, 32);
316 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, tmp
);
317 if (retval
!= ERROR_OK
)
321 retval
= dap_run(dap
);
322 if (retval
== ERROR_OK
) {
323 wcount
= wcount
- blocksize
;
324 address
= address
+ 4 * blocksize
;
325 buffer
= buffer
+ 4 * blocksize
;
329 if (errorcount
> 1) {
330 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
338 static int mem_ap_write_buf_packed_u16(struct adiv5_dap
*dap
,
339 const uint8_t *buffer
, int count
, uint32_t address
)
341 int retval
= ERROR_OK
;
342 int wcount
, blocksize
, writecount
, i
;
349 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
350 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
352 if (wcount
< blocksize
)
355 /* handle unaligned data at 4k boundary */
359 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
360 if (retval
!= ERROR_OK
)
362 writecount
= blocksize
;
365 nbytes
= MIN((writecount
<< 1), 4);
368 retval
= mem_ap_write_buf_u16(dap
, buffer
,
370 if (retval
!= ERROR_OK
) {
371 LOG_WARNING("Block write error address "
372 "0x%" PRIx32
", count 0x%x",
377 address
+= nbytes
>> 1;
380 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
382 for (i
= 0; i
< nbytes
; i
++) {
383 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
388 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
389 retval
= dap_queue_ap_write(dap
,
390 AP_REG_DRW
, outvalue
);
391 if (retval
!= ERROR_OK
)
394 retval
= dap_run(dap
);
395 if (retval
!= ERROR_OK
) {
396 LOG_WARNING("Block write error address "
397 "0x%" PRIx32
", count 0x%x",
403 buffer
+= nbytes
>> 1;
404 writecount
-= nbytes
>> 1;
406 } while (writecount
);
413 int mem_ap_write_buf_u16(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
415 int retval
= ERROR_OK
;
418 return mem_ap_write_buf_packed_u16(dap
, buffer
, count
, address
);
421 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
422 if (retval
!= ERROR_OK
)
425 memcpy(&svalue
, buffer
, sizeof(uint16_t));
426 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
427 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
428 if (retval
!= ERROR_OK
)
431 retval
= dap_run(dap
);
432 if (retval
!= ERROR_OK
)
443 static int mem_ap_write_buf_packed_u8(struct adiv5_dap
*dap
,
444 const uint8_t *buffer
, int count
, uint32_t address
)
446 int retval
= ERROR_OK
;
447 int wcount
, blocksize
, writecount
, i
;
454 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
455 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
457 if (wcount
< blocksize
)
460 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
461 if (retval
!= ERROR_OK
)
463 writecount
= blocksize
;
466 nbytes
= MIN(writecount
, 4);
469 retval
= mem_ap_write_buf_u8(dap
, buffer
, nbytes
, address
);
470 if (retval
!= ERROR_OK
) {
471 LOG_WARNING("Block write error address "
472 "0x%" PRIx32
", count 0x%x",
480 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
482 for (i
= 0; i
< nbytes
; i
++) {
483 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
488 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
489 retval
= dap_queue_ap_write(dap
,
490 AP_REG_DRW
, outvalue
);
491 if (retval
!= ERROR_OK
)
494 retval
= dap_run(dap
);
495 if (retval
!= ERROR_OK
) {
496 LOG_WARNING("Block write error address "
497 "0x%" PRIx32
", count 0x%x",
504 writecount
-= nbytes
;
506 } while (writecount
);
513 int mem_ap_write_buf_u8(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
515 int retval
= ERROR_OK
;
518 return mem_ap_write_buf_packed_u8(dap
, buffer
, count
, address
);
521 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
522 if (retval
!= ERROR_OK
)
524 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
525 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
526 if (retval
!= ERROR_OK
)
529 retval
= dap_run(dap
);
530 if (retval
!= ERROR_OK
)
541 /* FIXME don't import ... this is a temporary workaround for the
542 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
544 extern int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
545 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
546 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
);
549 * Synchronously read a block of 32-bit words into a buffer
550 * @param dap The DAP connected to the MEM-AP.
551 * @param buffer where the words will be stored (in host byte order).
552 * @param count How many words to read.
553 * @param address Memory address from which to read words; all the
554 * words must be readable by the currently selected MEM-AP.
555 * @Warning! THIS FUNCTION HAS JTAG CALLS HARDCODED!!!
557 int mem_ap_read_buf_u32_jtag(struct adiv5_dap
*dap
, uint8_t *buffer
,
558 int count
, uint32_t address
)
560 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
561 uint32_t adr
= address
;
562 uint8_t *pBuffer
= buffer
;
568 /* Adjust to read blocks within boundaries aligned to the
569 * TAR autoincrement size (at least 2^10). Autoincrement
570 * mode avoids an extra per-word roundtrip to update TAR.
572 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
574 if (wcount
< blocksize
)
577 /* handle unaligned data at 4k boundary */
581 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
583 if (retval
!= ERROR_OK
)
586 /* FIXME remove these three calls to adi_jtag_dp_scan(),
587 * so this routine becomes transport-neutral. Be careful
588 * not to cause performance problems with JTAG; would it
589 * suffice to loop over dap_queue_ap_read(), or would that
590 * be slower when JTAG is the chosen transport?
593 /* Scan out first read */
594 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
595 DPAP_READ
, 0, NULL
, NULL
);
596 if (retval
!= ERROR_OK
)
598 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++) {
599 /* Scan out next read; scan in posted value for the
600 * previous one. Assumes read is acked "OK/FAULT",
601 * and CTRL_STAT says that meant "OK".
603 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
604 DPAP_READ
, 0, buffer
+ 4 * readcount
,
606 if (retval
!= ERROR_OK
)
610 /* Scan in last posted value; RDBUFF has no other effect,
611 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
613 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_DPACC
, DP_RDBUFF
,
614 DPAP_READ
, 0, buffer
+ 4 * readcount
,
616 if (retval
!= ERROR_OK
)
619 retval
= dap_run(dap
);
620 if (retval
!= ERROR_OK
) {
622 if (errorcount
<= 1) {
626 LOG_WARNING("Block read error address 0x%" PRIx32
, address
);
629 wcount
= wcount
- blocksize
;
630 address
+= 4 * blocksize
;
631 buffer
+= 4 * blocksize
;
634 /* if we have an unaligned access - reorder data */
636 for (readcount
= 0; readcount
< count
; readcount
++) {
639 memcpy(&data
, pBuffer
, sizeof(uint32_t));
641 for (i
= 0; i
< 4; i
++) {
642 *((uint8_t *)pBuffer
) =
643 (data
>> 8 * (adr
& 0x3));
654 * This is a SWD handler, maybe future transport independent implementation
655 * of mem_ap_read_buf_u32() that is responsible to read data from mem-ap.
657 int mem_ap_read_buf_u32_swd(struct adiv5_dap
*dap
, uint8_t *buffer
,
658 int count
, uint32_t address
)
660 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
661 uint32_t adr
= address
;
662 uint8_t *pBuffer
= buffer
;
668 /* Adjust to read blocks within boundaries aligned to the
669 * TAR autoincrement size (at least 2^10). Autoincrement
670 * mode avoids an extra per-word roundtrip to update TAR.
672 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
674 if (wcount
< blocksize
)
677 /* handle unaligned data at 4k boundary */
681 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
683 if (retval
!= ERROR_OK
)
686 /* FIXME remove these three calls to adi_jtag_dp_scan(),
687 * so this routine becomes transport-neutral. Be careful
688 * not to cause performance problems with JTAG; would it
689 * suffice to loop over dap_queue_ap_read(), or would that
690 * be slower when JTAG is the chosen transport?
693 /* Stage 1: Scan out first read to initiate memory operation. */
694 /*retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, */
695 /* DPAP_READ, 0, NULL, NULL); */
696 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, NULL
);
697 if (retval
!= ERROR_OK
)
699 goto mem_ap_read_buf_u32_swd_handle_errors
;
701 /* Stage 2: Loop memory reads with TAR autoincrement. */
702 /* TODO: For SWD it might be possible to read data without
703 * additional request-ack-data phase. Try it out :-) */
704 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++) {
705 /* Scan out next read; scan in posted value for the
706 * previous one. Assumes read is acked "OK/FAULT",
707 * and CTRL_STAT says that meant "OK".
710 * retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
711 * DPAP_READ, 0, buffer + 4 * readcount,
713 * TODO: IS THIS POINTER/MEMORY OPERATION VALID??
715 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, (uint32_t *)buffer
+readcount
);
716 /* TODO: For SWD we will get response after call. */
717 /* We need to react / retry operation in here. */
718 if (retval
!= ERROR_OK
)
720 goto mem_ap_read_buf_u32_swd_handle_errors
;
723 /* Stage 3: Scan in last posted value; RDBUFF has no other effect,
724 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
727 * retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
728 * DPAP_READ, 0, buffer + 4 * readcount,
731 retval
= dap_queue_ap_read(dap
, DP_RDBUFF
, (uint32_t *)buffer
+readcount
);
732 if (retval
!= ERROR_OK
)
733 goto mem_ap_read_buf_u32_swd_handle_errors
;
735 retval
= dap_run(dap
);
737 mem_ap_read_buf_u32_swd_handle_errors
:
738 if (retval
!= ERROR_OK
) {
740 if (errorcount
<= 1) {
744 LOG_WARNING("Target - ARM DAP MEM-AP block read error address 0x%" PRIx32
, address
);
747 wcount
= wcount
- blocksize
;
748 address
+= 4 * blocksize
;
749 buffer
+= 4 * blocksize
;
752 /* if we have an unaligned access - reorder data */
754 for (readcount
= 0; readcount
< count
; readcount
++) {
757 memcpy(&data
, pBuffer
, sizeof(uint32_t));
759 for (i
= 0; i
< 4; i
++) {
760 *((uint8_t *)pBuffer
) =
761 (data
>> 8 * (adr
& 0x3));
773 * TEMPORARY WRAPPER WORKAROUND FOR MEM_AP_READ_BUF_U32
774 * UNTIL IT BECOMES TRANSPORT INDEPENDENT (ORIGINAL HAD JTAG CODE HARDCODED).
776 int mem_ap_read_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
,
777 int count
, uint32_t address
)
779 if (strncmp(jtag_interface
->transport
->name
, "swd", 3) == 0) {
780 return mem_ap_read_buf_u32_swd(dap
, buffer
, count
, address
);
781 } else if (strncmp(jtag_interface
->transport
->name
, "jtag", 4) == 0) {
782 return mem_ap_read_buf_u32_jtag(dap
, buffer
, count
, address
);
784 LOG_ERROR("Target - ARM ADI - unsupported transport selected!");
790 static int mem_ap_read_buf_packed_u16(struct adiv5_dap
*dap
,
791 uint8_t *buffer
, int count
, uint32_t address
)
794 int retval
= ERROR_OK
;
795 int wcount
, blocksize
, readcount
, i
;
802 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
803 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
804 if (wcount
< blocksize
)
807 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
808 if (retval
!= ERROR_OK
)
811 /* handle unaligned data at 4k boundary */
814 readcount
= blocksize
;
817 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
818 if (retval
!= ERROR_OK
)
820 retval
= dap_run(dap
);
821 if (retval
!= ERROR_OK
) {
822 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
826 nbytes
= MIN((readcount
<< 1), 4);
828 for (i
= 0; i
< nbytes
; i
++) {
829 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
834 readcount
-= (nbytes
>> 1);
843 * Synchronously read a block of 16-bit halfwords into a buffer
844 * @param dap The DAP connected to the MEM-AP.
845 * @param buffer where the halfwords will be stored (in host byte order).
846 * @param count How many halfwords to read.
847 * @param address Memory address from which to read words; all the
848 * words must be readable by the currently selected MEM-AP.
850 int mem_ap_read_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
,
851 int count
, uint32_t address
)
854 int retval
= ERROR_OK
;
857 return mem_ap_read_buf_packed_u16(dap
, buffer
, count
, address
);
860 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
861 if (retval
!= ERROR_OK
)
863 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
864 if (retval
!= ERROR_OK
)
867 retval
= dap_run(dap
);
868 if (retval
!= ERROR_OK
)
872 for (i
= 0; i
< 2; i
++) {
873 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
878 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
879 memcpy(buffer
, &svalue
, sizeof(uint16_t));
889 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
890 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
892 * The solution is to arrange for a large out/in scan in this loop and
893 * and convert data afterwards.
895 static int mem_ap_read_buf_packed_u8(struct adiv5_dap
*dap
,
896 uint8_t *buffer
, int count
, uint32_t address
)
899 int retval
= ERROR_OK
;
900 int wcount
, blocksize
, readcount
, i
;
907 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
908 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
910 if (wcount
< blocksize
)
913 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
914 if (retval
!= ERROR_OK
)
916 readcount
= blocksize
;
919 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
920 if (retval
!= ERROR_OK
)
922 retval
= dap_run(dap
);
923 if (retval
!= ERROR_OK
) {
924 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
928 nbytes
= MIN(readcount
, 4);
930 for (i
= 0; i
< nbytes
; i
++) {
931 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
945 * Synchronously read a block of bytes into a buffer
946 * @param dap The DAP connected to the MEM-AP.
947 * @param buffer where the bytes will be stored.
948 * @param count How many bytes to read.
949 * @param address Memory address from which to read data; all the
950 * data must be readable by the currently selected MEM-AP.
952 int mem_ap_read_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
,
953 int count
, uint32_t address
)
956 int retval
= ERROR_OK
;
959 return mem_ap_read_buf_packed_u8(dap
, buffer
, count
, address
);
962 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
963 if (retval
!= ERROR_OK
)
965 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
966 if (retval
!= ERROR_OK
)
968 retval
= dap_run(dap
);
969 if (retval
!= ERROR_OK
)
972 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
981 /*--------------------------------------------------------------------*/
982 /* Wrapping function with selection of AP */
983 /*--------------------------------------------------------------------*/
984 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
985 uint32_t address
, uint32_t *value
)
987 dap_ap_select(swjdp
, ap
);
988 return mem_ap_read_u32(swjdp
, address
, value
);
991 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
992 uint32_t address
, uint32_t value
)
994 dap_ap_select(swjdp
, ap
);
995 return mem_ap_write_u32(swjdp
, address
, value
);
998 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
999 uint32_t address
, uint32_t *value
)
1001 dap_ap_select(swjdp
, ap
);
1002 return mem_ap_read_atomic_u32(swjdp
, address
, value
);
1005 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
1006 uint32_t address
, uint32_t value
)
1008 dap_ap_select(swjdp
, ap
);
1009 return mem_ap_write_atomic_u32(swjdp
, address
, value
);
1012 int mem_ap_sel_read_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
1013 uint8_t *buffer
, int count
, uint32_t address
)
1015 dap_ap_select(swjdp
, ap
);
1016 return mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1019 int mem_ap_sel_read_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
1020 uint8_t *buffer
, int count
, uint32_t address
)
1022 dap_ap_select(swjdp
, ap
);
1023 return mem_ap_read_buf_u16(swjdp
, buffer
, count
, address
);
1026 int mem_ap_sel_read_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
1027 uint8_t *buffer
, int count
, uint32_t address
)
1029 dap_ap_select(swjdp
, ap
);
1030 return mem_ap_read_buf_u32(swjdp
, buffer
, count
, address
);
1033 int mem_ap_sel_write_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
1034 const uint8_t *buffer
, int count
, uint32_t address
)
1036 dap_ap_select(swjdp
, ap
);
1037 return mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1040 int mem_ap_sel_write_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
1041 const uint8_t *buffer
, int count
, uint32_t address
)
1043 dap_ap_select(swjdp
, ap
);
1044 return mem_ap_write_buf_u16(swjdp
, buffer
, count
, address
);
1047 int mem_ap_sel_write_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
1048 const uint8_t *buffer
, int count
, uint32_t address
)
1050 dap_ap_select(swjdp
, ap
);
1051 return mem_ap_write_buf_u32(swjdp
, buffer
, count
, address
);
1054 #define MDM_REG_STAT 0x00
1055 #define MDM_REG_CTRL 0x04
1056 #define MDM_REG_ID 0xfc
1058 #define MDM_STAT_FMEACK (1<<0)
1059 #define MDM_STAT_FREADY (1<<1)
1060 #define MDM_STAT_SYSSEC (1<<2)
1061 #define MDM_STAT_SYSRES (1<<3)
1062 #define MDM_STAT_FMEEN (1<<5)
1063 #define MDM_STAT_BACKDOOREN (1<<6)
1064 #define MDM_STAT_LPEN (1<<7)
1065 #define MDM_STAT_VLPEN (1<<8)
1066 #define MDM_STAT_LLSMODEXIT (1<<9)
1067 #define MDM_STAT_VLLSXMODEXIT (1<<10)
1068 #define MDM_STAT_CORE_HALTED (1<<16)
1069 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
1070 #define MDM_STAT_CORESLEEPING (1<<18)
1072 #define MEM_CTRL_FMEIP (1<<0)
1073 #define MEM_CTRL_DBG_DIS (1<<1)
1074 #define MEM_CTRL_DBG_REQ (1<<2)
1075 #define MEM_CTRL_SYS_RES_REQ (1<<3)
1076 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
1077 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
1078 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
1079 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
1084 int dap_syssec_kinetis_mdmap(struct adiv5_dap
*dap
)
1088 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1090 dap_ap_select(dap
, 1);
1092 /* first check mdm-ap id register */
1093 retval
= dap_queue_ap_read(dap
, MDM_REG_ID
, &val
);
1094 if (retval
!= ERROR_OK
)
1098 if (val
!= 0x001C0000) {
1099 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val
);
1100 dap_ap_select(dap
, 0);
1104 /* read and parse status register
1105 * it's important that the device is out of
1108 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
1109 if (retval
!= ERROR_OK
)
1113 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1115 if ((val
& (MDM_STAT_SYSSEC
|MDM_STAT_FREADY
)) != (MDM_STAT_FREADY
)) {
1116 LOG_DEBUG("MDMAP: system is secured, masserase needed");
1118 if (!(val
& MDM_STAT_FMEEN
))
1119 LOG_DEBUG("MDMAP: masserase is disabled");
1121 /* we need to assert reset */
1122 if (jtag_reset_config
& RESET_HAS_SRST
) {
1123 /* default to asserting srst */
1124 adapter_assert_reset();
1126 LOG_DEBUG("SRST not configured");
1127 dap_ap_select(dap
, 0);
1132 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, MEM_CTRL_FMEIP
);
1133 if (retval
!= ERROR_OK
)
1136 /* read status register and wait for ready */
1137 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
1138 if (retval
!= ERROR_OK
)
1141 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1148 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, 0);
1149 if (retval
!= ERROR_OK
)
1152 /* read status register */
1153 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
1154 if (retval
!= ERROR_OK
)
1157 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1158 /* read control register and wait for ready */
1159 retval
= dap_queue_ap_read(dap
, MDM_REG_CTRL
, &val
);
1160 if (retval
!= ERROR_OK
)
1163 LOG_DEBUG("MDM_REG_CTRL %08X", val
);
1171 dap_ap_select(dap
, 0);
1177 struct dap_syssec_filter
{
1181 int (*dap_init
)(struct adiv5_dap
*dap
);
1185 static struct dap_syssec_filter dap_syssec_filter_data
[] = {
1186 { 0x4BA00477, dap_syssec_kinetis_mdmap
}
1192 int dap_syssec(struct adiv5_dap
*dap
)
1195 struct jtag_tap
*tap
;
1197 for (i
= 0; i
< sizeof(dap_syssec_filter_data
); i
++) {
1198 tap
= dap
->jtag_info
->tap
;
1200 while (tap
!= NULL
) {
1201 if (tap
->hasidcode
&& (dap_syssec_filter_data
[i
].idcode
== tap
->idcode
)) {
1202 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap
->idcode
);
1203 dap_syssec_filter_data
[i
].dap_init(dap
);
1205 tap
= tap
->next_tap
;
1212 /*--------------------------------------------------------------------------*/
1215 /* FIXME don't import ... just initialize as
1216 * part of DAP transport setup
1218 extern const struct dap_ops jtag_dp_ops
;
1220 /*--------------------------------------------------------------------------*/
1223 * Initialize a DAP. This sets up the power domains, prepares the DP
1224 * for further use, and arranges to use AP #0 for all AP operations
1225 * until dap_ap-select() changes that policy.
1227 * @param dap The DAP being initialized.
1229 * @todo Rename this. We also need an initialization scheme which account
1230 * for SWD transports not just JTAG; that will need to address differences
1231 * in layering. (JTAG is useful without any debug target; but not SWD.)
1232 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1234 int ahbap_debugport_init(struct adiv5_dap
*dap
)
1242 /* JTAG-DP or SWJ-DP, in JTAG mode
1243 * ... for SWD mode this is patched as part
1244 * of link switchover
1247 dap
->ops
= &jtag_dap_ops
;
1249 /* Default MEM-AP setup.
1251 * REVISIT AP #0 may be an inappropriate default for this.
1252 * Should we probe, or take a hint from the caller?
1253 * Presumably we can ignore the possibility of multiple APs.
1255 dap
->ap_current
= !0;
1256 dap_ap_select(dap
, 0);
1258 /* DP initialization */
1260 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1261 if (retval
!= ERROR_OK
)
1264 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
1265 if (retval
!= ERROR_OK
)
1268 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1269 if (retval
!= ERROR_OK
)
1272 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1273 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1274 if (retval
!= ERROR_OK
)
1277 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1278 if (retval
!= ERROR_OK
)
1280 retval
= dap_run(dap
);
1281 if (retval
!= ERROR_OK
)
1284 /* Check that we have debug power domains activated */
1285 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10)) {
1286 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1287 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1288 if (retval
!= ERROR_OK
)
1290 retval
= dap_run(dap
);
1291 if (retval
!= ERROR_OK
)
1296 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10)) {
1297 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1298 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1299 if (retval
!= ERROR_OK
)
1301 retval
= dap_run(dap
);
1302 if (retval
!= ERROR_OK
)
1307 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1308 if (retval
!= ERROR_OK
)
1310 /* With debug power on we can activate OVERRUN checking */
1311 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1312 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1313 if (retval
!= ERROR_OK
)
1315 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1316 if (retval
!= ERROR_OK
)
1324 /* CID interpretation -- see ARM IHI 0029B section 3
1325 * and ARM IHI 0031A table 13-3.
1327 static const char *class_description
[16] = {
1328 "Reserved", "ROM table", "Reserved", "Reserved",
1329 "Reserved", "Reserved", "Reserved", "Reserved",
1330 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1331 "Reserved", "OptimoDE DESS",
1332 "Generic IP component", "PrimeCell or System component"
1335 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1337 return cid3
== 0xb1 && cid2
== 0x05
1338 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1341 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
1342 uint32_t *out_dbgbase
, uint32_t *out_apid
)
1346 uint32_t dbgbase
, apid
;
1348 /* AP address is in bits 31:24 of DP_SELECT */
1350 return ERROR_COMMAND_SYNTAX_ERROR
;
1352 ap_old
= dap
->ap_current
;
1353 dap_ap_select(dap
, ap
);
1355 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &dbgbase
);
1356 if (retval
!= ERROR_OK
)
1358 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1359 if (retval
!= ERROR_OK
)
1361 retval
= dap_run(dap
);
1362 if (retval
!= ERROR_OK
)
1365 /* Excavate the device ID code */
1366 struct jtag_tap
*tap
= dap
->jtag_info
->tap
;
1367 while (tap
!= NULL
) {
1370 tap
= tap
->next_tap
;
1372 if (tap
== NULL
|| !tap
->hasidcode
)
1375 dap_ap_select(dap
, ap_old
);
1377 /* The asignment happens only here to prevent modification of these
1378 * values before they are certain. */
1379 *out_dbgbase
= dbgbase
;
1385 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
1386 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
)
1389 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
1390 int retval
= ERROR_FAIL
;
1393 return ERROR_COMMAND_SYNTAX_ERROR
;
1395 ap_old
= dap
->ap_current
;
1396 dap_ap_select(dap
, ap
);
1399 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) |
1400 entry_offset
, &romentry
);
1401 if (retval
!= ERROR_OK
)
1404 component_base
= (dbgbase
& 0xFFFFF000)
1405 + (romentry
& 0xFFFFF000);
1407 if (romentry
& 0x1) {
1408 retval
= mem_ap_read_atomic_u32(dap
,
1409 (component_base
& 0xfffff000) | 0xfcc,
1411 if (retval
!= ERROR_OK
)
1413 if ((devtype
& 0xff) == type
) {
1414 *addr
= component_base
;
1420 } while (romentry
> 0);
1422 dap_ap_select(dap
, ap_old
);
1427 static int dap_info_command(struct command_context
*cmd_ctx
,
1428 struct adiv5_dap
*dap
, int ap
)
1431 uint32_t dbgbase
= 0, apid
= 0; /* Silence gcc by initializing */
1432 int romtable_present
= 0;
1436 retval
= dap_get_debugbase(dap
, ap
, &dbgbase
, &apid
);
1437 if (retval
!= ERROR_OK
)
1440 ap_old
= dap
->ap_current
;
1441 dap_ap_select(dap
, ap
);
1443 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1444 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1445 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1447 switch (apid
&0x0F) {
1449 command_print(cmd_ctx
, "\tType is JTAG-AP");
1452 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1455 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1458 command_print(cmd_ctx
, "\tUnknown AP type");
1462 /* NOTE: a MEM-AP may have a single CoreSight component that's
1463 * not a ROM table ... or have no such components at all.
1466 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
, dbgbase
);
1468 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
);
1470 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1471 if (romtable_present
) {
1472 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
1473 uint16_t entry_offset
;
1475 /* bit 16 of apid indicates a memory access port */
1477 command_print(cmd_ctx
, "\tValid ROM table present");
1479 command_print(cmd_ctx
, "\tROM table in legacy format");
1481 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1482 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1483 if (retval
!= ERROR_OK
)
1485 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1486 if (retval
!= ERROR_OK
)
1488 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1489 if (retval
!= ERROR_OK
)
1491 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1492 if (retval
!= ERROR_OK
)
1494 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1495 if (retval
!= ERROR_OK
)
1497 retval
= dap_run(dap
);
1498 if (retval
!= ERROR_OK
)
1501 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1502 command_print(cmd_ctx
, "\tCID3 0x%2.2x"
1506 (unsigned) cid3
, (unsigned)cid2
,
1507 (unsigned) cid1
, (unsigned) cid0
);
1509 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1511 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1512 "Dedicated debug bus.");
1514 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1517 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1518 if (retval
!= ERROR_OK
)
1520 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"", entry_offset
, romentry
);
1521 if (romentry
& 0x01) {
1522 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1523 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1524 uint32_t component_base
;
1528 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
1530 /* IDs are in last 4K section */
1531 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE0, &c_pid0
);
1532 if (retval
!= ERROR_OK
)
1535 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE4, &c_pid1
);
1536 if (retval
!= ERROR_OK
)
1539 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE8, &c_pid2
);
1540 if (retval
!= ERROR_OK
)
1543 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFEC, &c_pid3
);
1544 if (retval
!= ERROR_OK
)
1547 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFD0, &c_pid4
);
1548 if (retval
!= ERROR_OK
)
1552 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF0, &c_cid0
);
1553 if (retval
!= ERROR_OK
)
1556 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF4, &c_cid1
);
1557 if (retval
!= ERROR_OK
)
1560 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF8, &c_cid2
);
1561 if (retval
!= ERROR_OK
)
1564 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFFC, &c_cid3
);
1565 if (retval
!= ERROR_OK
)
1569 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
","
1570 "start address 0x%" PRIx32
, component_base
,
1571 /* component may take multiple 4K pages */
1572 component_base
- 0x1000*(c_pid4
>> 4));
1573 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1574 (int) (c_cid1
>> 4) & 0xf,
1575 /* See ARM IHI 0029B Table 3-3 */
1576 class_description
[(c_cid1
>> 4) & 0xf]);
1578 /* CoreSight component? */
1579 if (((c_cid1
>> 4) & 0x0f) == 9) {
1582 char *major
= "Reserved", *subtype
= "Reserved";
1584 retval
= mem_ap_read_atomic_u32(dap
,
1585 (component_base
& 0xfffff000) | 0xfcc,
1587 if (retval
!= ERROR_OK
)
1589 minor
= (devtype
>> 4) & 0x0f;
1590 switch (devtype
& 0x0f) {
1592 major
= "Miscellaneous";
1598 subtype
= "Validation component";
1603 major
= "Trace Sink";
1617 major
= "Trace Link";
1623 subtype
= "Funnel, router";
1629 subtype
= "FIFO, buffer";
1634 major
= "Trace Source";
1640 subtype
= "Processor";
1646 subtype
= "Engine/Coprocessor";
1654 major
= "Debug Control";
1660 subtype
= "Trigger Matrix";
1663 subtype
= "Debug Auth";
1668 major
= "Debug Logic";
1674 subtype
= "Processor";
1680 subtype
= "Engine/Coprocessor";
1685 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1686 (unsigned) (devtype
& 0xff),
1688 /* REVISIT also show 0xfc8 DevId */
1691 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1692 command_print(cmd_ctx
,
1701 command_print(cmd_ctx
,
1702 "\t\tPeripheral ID[4..0] = hex "
1703 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1704 (int) c_pid4
, (int) c_pid3
, (int) c_pid2
,
1705 (int) c_pid1
, (int) c_pid0
);
1707 /* Part number interpretations are from Cortex
1708 * core specs, the CoreSight components TRM
1709 * (ARM DDI 0314H), CoreSight System Design
1710 * Guide (ARM DGI 0012D) and ETM specs; also
1711 * from chip observation (e.g. TI SDTI).
1713 part_num
= (c_pid0
& 0xff);
1714 part_num
|= (c_pid1
& 0x0f) << 8;
1717 type
= "Cortex-M3 NVIC";
1718 full
= "(Interrupt Controller)";
1721 type
= "Cortex-M3 ITM";
1722 full
= "(Instrumentation Trace Module)";
1725 type
= "Cortex-M3 DWT";
1726 full
= "(Data Watchpoint and Trace)";
1729 type
= "Cortex-M3 FBP";
1730 full
= "(Flash Patch and Breakpoint)";
1733 type
= "Cortex-M4 SCS";
1734 full
= "(System Control Space)";
1737 type
= "CoreSight ETM11";
1738 full
= "(Embedded Trace)";
1740 /* case 0x113: what? */
1741 case 0x120: /* from OMAP3 memmap */
1743 full
= "(System Debug Trace Interface)";
1745 case 0x343: /* from OMAP3 memmap */
1750 type
= "Coresight CTI";
1751 full
= "(Cross Trigger)";
1754 type
= "Coresight ETB";
1755 full
= "(Trace Buffer)";
1758 type
= "Coresight CSTF";
1759 full
= "(Trace Funnel)";
1762 type
= "CoreSight ETM9";
1763 full
= "(Embedded Trace)";
1766 type
= "Coresight TPIU";
1767 full
= "(Trace Port Interface Unit)";
1770 type
= "Cortex-A8 ETM";
1771 full
= "(Embedded Trace)";
1774 type
= "Cortex-A8 CTI";
1775 full
= "(Cross Trigger)";
1778 type
= "Cortex-M3 TPIU";
1779 full
= "(Trace Port Interface Unit)";
1782 type
= "Cortex-M3 ETM";
1783 full
= "(Embedded Trace)";
1786 type
= "Cortex-M4 ETM";
1787 full
= "(Embedded Trace)";
1790 type
= "Cortex-R4 ETM";
1791 full
= "(Embedded Trace)";
1794 type
= "Cortex-M4 TPUI";
1795 full
= "(Trace Port Interface Unit)";
1798 type
= "Cortex-A8 Debug";
1799 full
= "(Debug Unit)";
1802 type
= "-*- unrecognized -*-";
1806 command_print(cmd_ctx
, "\t\tPart is %s %s",
1810 command_print(cmd_ctx
, "\t\tComponent not present");
1812 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1815 } while (romentry
> 0);
1817 command_print(cmd_ctx
, "\tNo ROM table present");
1818 dap_ap_select(dap
, ap_old
);
1823 COMMAND_HANDLER(handle_dap_info_command
)
1825 struct target
*target
= get_current_target(CMD_CTX
);
1826 struct arm
*arm
= target_to_arm(target
);
1827 struct adiv5_dap
*dap
= arm
->dap
;
1835 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1838 return ERROR_COMMAND_SYNTAX_ERROR
;
1841 return dap_info_command(CMD_CTX
, dap
, apsel
);
1844 COMMAND_HANDLER(dap_baseaddr_command
)
1846 struct target
*target
= get_current_target(CMD_CTX
);
1847 struct arm
*arm
= target_to_arm(target
);
1848 struct adiv5_dap
*dap
= arm
->dap
;
1850 uint32_t apsel
, baseaddr
;
1858 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1859 /* AP address is in bits 31:24 of DP_SELECT */
1861 return ERROR_COMMAND_SYNTAX_ERROR
;
1864 return ERROR_COMMAND_SYNTAX_ERROR
;
1867 dap_ap_select(dap
, apsel
);
1869 /* NOTE: assumes we're talking to a MEM-AP, which
1870 * has a base address. There are other kinds of AP,
1871 * though they're not common for now. This should
1872 * use the ID register to verify it's a MEM-AP.
1874 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &baseaddr
);
1875 if (retval
!= ERROR_OK
)
1877 retval
= dap_run(dap
);
1878 if (retval
!= ERROR_OK
)
1881 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1886 COMMAND_HANDLER(dap_memaccess_command
)
1888 struct target
*target
= get_current_target(CMD_CTX
);
1889 struct arm
*arm
= target_to_arm(target
);
1890 struct adiv5_dap
*dap
= arm
->dap
;
1892 uint32_t memaccess_tck
;
1896 memaccess_tck
= dap
->memaccess_tck
;
1899 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1902 return ERROR_COMMAND_SYNTAX_ERROR
;
1904 dap
->memaccess_tck
= memaccess_tck
;
1906 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1907 dap
->memaccess_tck
);
1912 COMMAND_HANDLER(dap_apsel_command
)
1914 struct target
*target
= get_current_target(CMD_CTX
);
1915 struct arm
*arm
= target_to_arm(target
);
1916 struct adiv5_dap
*dap
= arm
->dap
;
1918 uint32_t apsel
, apid
;
1926 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1927 /* AP address is in bits 31:24 of DP_SELECT */
1929 return ERROR_COMMAND_SYNTAX_ERROR
;
1932 return ERROR_COMMAND_SYNTAX_ERROR
;
1936 dap_ap_select(dap
, apsel
);
1938 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1939 if (retval
!= ERROR_OK
)
1941 retval
= dap_run(dap
);
1942 if (retval
!= ERROR_OK
)
1945 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1951 COMMAND_HANDLER(dap_apid_command
)
1953 struct target
*target
= get_current_target(CMD_CTX
);
1954 struct arm
*arm
= target_to_arm(target
);
1955 struct adiv5_dap
*dap
= arm
->dap
;
1957 uint32_t apsel
, apid
;
1965 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1966 /* AP address is in bits 31:24 of DP_SELECT */
1968 return ERROR_COMMAND_SYNTAX_ERROR
;
1971 return ERROR_COMMAND_SYNTAX_ERROR
;
1974 dap_ap_select(dap
, apsel
);
1976 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1977 if (retval
!= ERROR_OK
)
1979 retval
= dap_run(dap
);
1980 if (retval
!= ERROR_OK
)
1983 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1988 static const struct command_registration dap_commands
[] = {
1991 .handler
= handle_dap_info_command
,
1992 .mode
= COMMAND_EXEC
,
1993 .help
= "display ROM table for MEM-AP "
1994 "(default currently selected AP)",
1995 .usage
= "[ap_num]",
1999 .handler
= dap_apsel_command
,
2000 .mode
= COMMAND_EXEC
,
2001 .help
= "Set the currently selected AP (default 0) "
2002 "and display the result",
2003 .usage
= "[ap_num]",
2007 .handler
= dap_apid_command
,
2008 .mode
= COMMAND_EXEC
,
2009 .help
= "return ID register from AP "
2010 "(default currently selected AP)",
2011 .usage
= "[ap_num]",
2015 .handler
= dap_baseaddr_command
,
2016 .mode
= COMMAND_EXEC
,
2017 .help
= "return debug base address from MEM-AP "
2018 "(default currently selected AP)",
2019 .usage
= "[ap_num]",
2022 .name
= "memaccess",
2023 .handler
= dap_memaccess_command
,
2024 .mode
= COMMAND_EXEC
,
2025 .help
= "set/get number of extra tck for MEM-AP memory "
2026 "bus access [0-255]",
2027 .usage
= "[cycles]",
2029 COMMAND_REGISTRATION_DONE
2032 const struct command_registration dap_command_handlers
[] = {
2035 .mode
= COMMAND_EXEC
,
2036 .help
= "DAP command group",
2038 .chain
= dap_commands
,
2040 COMMAND_REGISTRATION_DONE