1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2009-2010 by David Brownell
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 ***************************************************************************/
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
42 #include <interface/feature.h>
44 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
45 #define JTAG_DP_ABORT 0x8
46 #define JTAG_DP_DPACC 0xA
47 #define JTAG_DP_APACC 0xB
48 #define JTAG_DP_IDCODE 0xE
50 /* three-bit ACK values for DPACC and APACC reads */
51 #define JTAG_ACK_OK_FAULT 0x2
52 #define JTAG_ACK_WAIT 0x1
54 /***************************************************************************
56 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
58 ***************************************************************************/
61 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
62 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
63 * discusses operations which access these registers.
65 * Note that only one scan is performed. If RnW is set, a separate scan
66 * will be needed to collect the data which was read; the "invalue" collects
67 * the posted result of a preceding operation, not the current one.
70 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
71 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
72 * SELECT register has more addressing bits.
73 * @param RnW false iff outvalue will be written to the DP or AP
74 * @param outvalue points to a 32-bit (little-endian) integer
75 * @param invalue NULL, or points to a 32-bit (little-endian) integer
76 * @param ack points to where the three bit JTAG_ACK_* code will be stored
79 /* FIXME don't export ... this is a temporary workaround for the
80 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
82 int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
83 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
84 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
86 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
87 struct scan_field fields
[2];
91 retval
= arm_jtag_set_instr(jtag_info
, instr
, NULL
, TAP_IDLE
);
92 if (retval
!= ERROR_OK
)
95 /* Scan out a read or write operation using some DP or AP register.
96 * For APACC access with any sticky error flag set, this is discarded.
98 fields
[0].num_bits
= 3;
99 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
100 fields
[0].out_value
= &out_addr_buf
;
101 fields
[0].in_value
= ack
;
103 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
104 * complete; data we write is discarded, data we read is unpredictable.
105 * When overrun detect is active, STICKYORUN is set.
108 fields
[1].num_bits
= 32;
109 fields
[1].out_value
= outvalue
;
110 fields
[1].in_value
= invalue
;
112 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_IDLE
);
114 /* Add specified number of tck clocks after starting memory bus
115 * access, giving the hardware time to complete the access.
116 * They provide more time for the (MEM) AP to complete the read ...
117 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
119 if ((instr
== JTAG_DP_APACC
)
120 && ((reg_addr
== AP_REG_DRW
)
121 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
122 && (dap
->memaccess_tck
!= 0))
123 jtag_add_runtest(dap
->memaccess_tck
,
130 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
131 * This is exactly like adi_jtag_dp_scan(), except that endianness
132 * conversions are performed (so the types of invalue and outvalue
133 * must be different).
135 static int adi_jtag_dp_scan_u32(struct adiv5_dap
*dap
,
136 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
137 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
139 uint8_t out_value_buf
[4];
142 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
144 retval
= adi_jtag_dp_scan(dap
, instr
, reg_addr
, RnW
,
145 out_value_buf
, (uint8_t *)invalue
, ack
);
146 if (retval
!= ERROR_OK
)
150 jtag_add_callback(arm_le_to_h_u32
,
151 (jtag_callback_data_t
) invalue
);
157 * Utility to write AP registers.
159 static inline int adi_jtag_ap_write_check(struct adiv5_dap
*dap
,
160 uint8_t reg_addr
, uint8_t *outvalue
)
162 return adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg_addr
, DPAP_WRITE
,
163 outvalue
, NULL
, NULL
);
166 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap
*dap
,
167 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
168 uint32_t outvalue
, uint32_t *invalue
)
172 /* Issue the read or write */
173 retval
= adi_jtag_dp_scan_u32(dap
, instr
, reg_addr
,
174 RnW
, outvalue
, NULL
, NULL
);
175 if (retval
!= ERROR_OK
)
178 /* For reads, collect posted value; RDBUFF has no other effect.
179 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
181 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
182 retval
= adi_jtag_dp_scan_u32(dap
, JTAG_DP_DPACC
,
183 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &dap
->ack
);
187 static int jtagdp_transaction_endcheck(struct adiv5_dap
*dap
)
192 /* too expensive to call keep_alive() here */
196 * It is easy to be in a JTAG clock range where the target
197 * is not operating in a stable fashion. This happens
200 * - the user may construct a simple test case to try to see
201 * if a higher JTAG clock works to eke out more performance.
202 * This simple case may pass, but more complex situations can
205 * - The mostly works JTAG clock rate and the complete failure
206 * JTAG clock rate may be as much as 2-4x apart. This seems
207 * to be especially true on RC oscillator driven parts.
209 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
210 * times here seems to "make things better here", it is just
211 * hiding problems with too high a JTAG clock.
213 * Note that even if some parts have RCLK/RTCK, that doesn't
214 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
215 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
216 * before the RC oscillator phase is not yet complete.
219 /* Post CTRL/STAT read; discard any previous posted read value
220 * but collect its ACK status.
222 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
223 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
224 if (retval
!= ERROR_OK
)
226 retval
= jtag_execute_queue();
227 if (retval
!= ERROR_OK
)
230 dap
->ack
= dap
->ack
& 0x7;
232 /* common code path avoids calling timeval_ms() */
233 if (dap
->ack
!= JTAG_ACK_OK_FAULT
) {
234 long long then
= timeval_ms();
236 while (dap
->ack
!= JTAG_ACK_OK_FAULT
) {
237 if (dap
->ack
== JTAG_ACK_WAIT
) {
238 if ((timeval_ms()-then
) > 1000) {
239 /* NOTE: this would be a good spot
240 * to use JTAG_DP_ABORT.
242 LOG_WARNING("Timeout (1000ms) waiting "
244 "in JTAG-DP transaction");
245 return ERROR_JTAG_DEVICE_ERROR
;
248 LOG_WARNING("Invalid ACK %#x "
249 "in JTAG-DP transaction",
251 return ERROR_JTAG_DEVICE_ERROR
;
254 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
255 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
256 if (retval
!= ERROR_OK
)
258 retval
= jtag_execute_queue();
259 if (retval
!= ERROR_OK
)
261 dap
->ack
= dap
->ack
& 0x7;
265 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
267 /* Check for STICKYERR and STICKYORUN */
268 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
)) {
269 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
270 /* Check power to debug regions */
271 if ((ctrlstat
& 0xf0000000) != 0xf0000000) {
272 retval
= ahbap_debugport_init(dap
);
273 if (retval
!= ERROR_OK
)
276 uint32_t mem_ap_csw
, mem_ap_tar
;
278 /* Maybe print information about last intended
279 * MEM-AP access; but not if autoincrementing.
280 * *Real* CSW and TAR values are always shown.
282 if (dap
->ap_tar_value
!= (uint32_t) -1)
283 LOG_DEBUG("MEM-AP Cached values: "
285 ", ap_csw 0x%" PRIx32
286 ", ap_tar 0x%" PRIx32
,
291 if (ctrlstat
& SSTICKYORUN
)
292 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
293 "memaccess, or reduce jtag speed");
295 if (ctrlstat
& SSTICKYERR
)
296 LOG_ERROR("JTAG-DP STICKY ERROR");
298 /* Clear Sticky Error Bits */
299 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
300 DP_CTRL_STAT
, DPAP_WRITE
,
301 dap
->dp_ctrl_stat
| SSTICKYORUN
303 if (retval
!= ERROR_OK
)
305 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
306 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
307 if (retval
!= ERROR_OK
)
309 retval
= jtag_execute_queue();
310 if (retval
!= ERROR_OK
)
313 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
315 retval
= dap_queue_ap_read(dap
,
316 AP_REG_CSW
, &mem_ap_csw
);
317 if (retval
!= ERROR_OK
)
320 retval
= dap_queue_ap_read(dap
,
321 AP_REG_TAR
, &mem_ap_tar
);
322 if (retval
!= ERROR_OK
)
325 retval
= jtag_execute_queue();
326 if (retval
!= ERROR_OK
)
328 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
329 PRIx32
, mem_ap_csw
, mem_ap_tar
);
332 retval
= jtag_execute_queue();
333 if (retval
!= ERROR_OK
)
335 return ERROR_JTAG_DEVICE_ERROR
;
341 /*--------------------------------------------------------------------------*/
343 static int jtag_idcode_q_read(struct adiv5_dap
*dap
,
344 uint8_t *ack
, uint32_t *data
)
346 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
348 struct scan_field fields
[1];
350 /* This is a standard JTAG operation -- no DAP tweakage */
351 retval
= arm_jtag_set_instr(jtag_info
, JTAG_DP_IDCODE
, NULL
, TAP_IDLE
);
352 if (retval
!= ERROR_OK
)
355 fields
[0].num_bits
= 32;
356 fields
[0].out_value
= NULL
;
357 fields
[0].in_value
= (void *) data
;
359 jtag_add_dr_scan(jtag_info
->tap
, 1, fields
, TAP_IDLE
);
361 jtag_add_callback(arm_le_to_h_u32
,
362 (jtag_callback_data_t
) data
);
367 static int jtag_dp_q_read(struct adiv5_dap
*dap
, unsigned reg
,
370 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
371 reg
, DPAP_READ
, 0, data
);
374 static int jtag_dp_q_write(struct adiv5_dap
*dap
, unsigned reg
,
377 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
378 reg
, DPAP_WRITE
, data
, NULL
);
381 /** Select the AP register bank matching bits 7:4 of reg. */
382 static int jtag_ap_q_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
384 uint32_t select_ap_bank
= reg
& 0x000000F0;
386 if (select_ap_bank
== dap
->ap_bank_value
)
388 dap
->ap_bank_value
= select_ap_bank
;
390 select_ap_bank
|= dap
->ap_current
;
392 return jtag_dp_q_write(dap
, DP_SELECT
, select_ap_bank
);
395 static int jtag_ap_q_read(struct adiv5_dap
*dap
, unsigned reg
,
398 int retval
= jtag_ap_q_bankselect(dap
, reg
);
400 if (retval
!= ERROR_OK
)
403 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_APACC
, reg
,
407 static int jtag_ap_q_write(struct adiv5_dap
*dap
, unsigned reg
,
410 uint8_t out_value_buf
[4];
412 int retval
= jtag_ap_q_bankselect(dap
, reg
);
413 if (retval
!= ERROR_OK
)
416 buf_set_u32(out_value_buf
, 0, 32, data
);
418 return adi_jtag_ap_write_check(dap
, reg
, out_value_buf
);
421 static int jtag_ap_q_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
423 /* for JTAG, this is the only valid ABORT register operation */
424 return adi_jtag_dp_scan_u32(dap
, JTAG_DP_ABORT
,
425 0, DPAP_WRITE
, 1, NULL
, ack
);
428 static int jtag_dp_run(struct adiv5_dap
*dap
)
430 return jtagdp_transaction_endcheck(dap
);
433 /* FIXME don't export ... just initialize as
436 const struct dap_ops jtag_dap_ops
= {
437 .select
= jtag_select
,
439 .queue_idcode_read
= jtag_idcode_q_read
,
440 .queue_dp_read
= jtag_dp_q_read
,
441 .queue_dp_write
= jtag_dp_q_write
,
442 .queue_ap_read
= jtag_ap_q_read
,
443 .queue_ap_write
= jtag_ap_q_write
,
444 .queue_ap_abort
= jtag_ap_q_abort
,
449 * Interface features that adds JTAG support for an interface.
450 * Attach to driver feature list by driver setup or interface definition.
452 oocd_feature_t oocd_transport_jtag_arm_dap_feature
= {
453 .name
= OOCD_FEATURE_ARM_DAP
,
454 .description
= "JTAG transport feature to work with ARM DAP.",
455 .body
= (void *) &jtag_dap_ops
,
460 static const uint8_t swd2jtag_bitseq
[] = {
461 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
462 * putting both JTAG and SWD logic into reset state.
464 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
465 /* Switching equence disables SWD and enables JTAG
466 * NOTE: bits in the DP's IDCODE can expose the need for
467 * the old/deprecated sequence (0xae 0xde).
470 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
471 * putting both JTAG and SWD logic into reset state.
472 * NOTE: some docs say "at least 5".
474 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
477 /** Put the debug link into JTAG mode, if the target supports it.
478 * The link's initial mode may be either SWD or JTAG.
480 * @param target Enters JTAG mode (if possible).
482 * Note that targets implemented with SW-DP do not support JTAG, and
483 * that some targets which could otherwise support it may have been
484 * configured to disable JTAG signaling
486 * @return ERROR_OK or else a fault code.
488 int dap_to_jtag(struct target
*target
)
492 LOG_DEBUG("Enter JTAG mode");
494 /* REVISIT it's nasty to need to make calls to a "jtag"
495 * subsystem if the link isn't in JTAG mode...
498 retval
= jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq
),
499 swd2jtag_bitseq
, TAP_RESET
);
500 if (retval
== ERROR_OK
)
501 retval
= jtag_execute_queue();
503 /* REVISIT set up the DAP's ops vector for JTAG mode. */