1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
115 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
116 A @dfn{TAP} is a ``Test Access Port'', a module which processes
117 special instructions and data. TAPs are daisy-chained within and
118 between chips and boards.
120 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
121 based, parallel port based, and other standalone boxes that run
122 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
125 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
126 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
127 debugged via the GDB protocol.
129 @b{Flash Programing:} Flash writing is supported for external CFI
130 compatible NOR flashes (Intel and AMD/Spansion command set) and several
131 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
132 STM32x). Preliminary support for various NAND flash controllers
133 (LPC3180, Orion, S3C24xx, more) controller is included.
135 @section OpenOCD Web Site
137 The OpenOCD web site provides the latest public news from the community:
139 @uref{http://openocd.berlios.de/web/}
141 @section Latest User's Guide:
143 The user's guide you are now reading may not be the latest one
144 available. A version for more recent code may be available.
145 Its HTML form is published irregularly at:
147 @uref{http://openocd.berlios.de/doc/html/index.html}
149 PDF form is likewise published at:
151 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
153 @section OpenOCD User's Forum
155 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
161 @chapter OpenOCD Developer Resources
164 If you are interested in improving the state of OpenOCD's debugging and
165 testing support, new contributions will be welcome. Motivated developers
166 can produce new target, flash or interface drivers, improve the
167 documentation, as well as more conventional bug fixes and enhancements.
169 The resources in this chapter are available for developers wishing to explore
170 or expand the OpenOCD source code.
172 @section OpenOCD GIT Repository
174 During the 0.3.x release cycle, OpenOCD switched from Subversion to
175 a GIT repository hosted at SourceForge. The repository URL is:
177 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
179 You may prefer to use a mirror and the HTTP protocol:
181 @uref{http://repo.or.cz/r/openocd.git}
183 With standard GIT tools, use @command{git clone} to initialize
184 a local repository, and @command{git pull} to update it.
185 There are also gitweb pages letting you browse the repository
186 with a web browser, or download arbitrary snapshots without
187 needing a GIT client:
189 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
191 @uref{http://repo.or.cz/w/openocd.git}
193 The @file{README} file contains the instructions for building the project
194 from the repository or a snapshot.
196 Developers that want to contribute patches to the OpenOCD system are
197 @b{strongly} encouraged to work against mainline.
198 Patches created against older versions may require additional
199 work from their submitter in order to be updated for newer releases.
201 @section Doxygen Developer Manual
203 During the 0.2.x release cycle, the OpenOCD project began
204 providing a Doxygen reference manual. This document contains more
205 technical information about the software internals, development
206 processes, and similar documentation:
208 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
210 This document is a work-in-progress, but contributions would be welcome
211 to fill in the gaps. All of the source files are provided in-tree,
212 listed in the Doxyfile configuration in the top of the source tree.
214 @section OpenOCD Developer Mailing List
216 The OpenOCD Developer Mailing List provides the primary means of
217 communication between developers:
219 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
221 Discuss and submit patches to this list.
222 The @file{PATCHES} file contains basic information about how
226 @node JTAG Hardware Dongles
227 @chapter JTAG Hardware Dongles
236 Defined: @b{dongle}: A small device that plugins into a computer and serves as
237 an adapter .... [snip]
239 In the OpenOCD case, this generally refers to @b{a small adapater} one
240 attaches to your computer via USB or the Parallel Printer Port. The
241 execption being the Zylin ZY1000 which is a small box you attach via
242 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
243 require any drivers to be installed on the developer PC. It also has
244 a built in web interface. It supports RTCK/RCLK or adaptive clocking
245 and has a built in relay to power cycle targets remotely.
248 @section Choosing a Dongle
250 There are several things you should keep in mind when choosing a dongle.
253 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
254 Does your dongle support it? You might need a level converter.
255 @item @b{Pinout} What pinout does your target board use?
256 Does your dongle support it? You may be able to use jumper
257 wires, or an "octopus" connector, to convert pinouts.
258 @item @b{Connection} Does your computer have the USB, printer, or
259 Ethernet port needed?
260 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
263 @section Stand alone Systems
265 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
266 dongle, but a standalone box. The ZY1000 has the advantage that it does
267 not require any drivers installed on the developer PC. It also has
268 a built in web interface. It supports RTCK/RCLK or adaptive clocking
269 and has a built in relay to power cycle targets remotely.
271 @section USB FT2232 Based
273 There are many USB JTAG dongles on the market, many of them are based
274 on a chip from ``Future Technology Devices International'' (FTDI)
275 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
276 See: @url{http://www.ftdichip.com} for more information.
277 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
278 chips are starting to become available in JTAG adapters.
282 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
284 @* See: @url{http://www.amontec.com/jtagkey.shtml}
286 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
288 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
290 @* See: @url{http://www.signalyzer.com}
291 @item @b{evb_lm3s811}
292 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
293 @item @b{luminary_icdi}
294 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
295 @item @b{olimex-jtag}
296 @* See: @url{http://www.olimex.com}
298 @* See: @url{http://www.tincantools.com}
299 @item @b{turtelizer2}
301 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
302 @url{http://www.ethernut.de}
304 @* Link: @url{http://www.hitex.com/index.php?id=383}
306 @* Link @url{http://www.hitex.com/stm32-stick}
307 @item @b{axm0432_jtag}
308 @* Axiom AXM-0432 Link @url{http://www.axman.com}
310 @* Link @url{http://www.hitex.com/index.php?id=cortino}
313 @section USB JLINK based
314 There are several OEM versions of the Segger @b{JLINK} adapter. It is
315 an example of a micro controller based JTAG adapter, it uses an
316 AT91SAM764 internally.
319 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
320 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
321 @item @b{SEGGER JLINK}
322 @* Link: @url{http://www.segger.com/jlink.html}
324 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
327 @section USB RLINK based
328 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
331 @item @b{Raisonance RLink}
332 @* Link: @url{http://www.raisonance.com/products/RLink.php}
333 @item @b{STM32 Primer}
334 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
335 @item @b{STM32 Primer2}
336 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
342 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
344 @item @b{USB - Presto}
345 @* Link: @url{http://tools.asix.net/prg_presto.htm}
347 @item @b{Versaloon-Link}
348 @* Link: @url{http://www.simonqian.com/en/Versaloon}
350 @item @b{ARM-JTAG-EW}
351 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
354 @section IBM PC Parallel Printer Port Based
356 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
357 and the MacGraigor Wiggler. There are many clones and variations of
360 Note that parallel ports are becoming much less common, so if you
361 have the choice you should probably avoid these adapters in favor
366 @item @b{Wiggler} - There are many clones of this.
367 @* Link: @url{http://www.macraigor.com/wiggler.htm}
369 @item @b{DLC5} - From XILINX - There are many clones of this
370 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
371 produced, PDF schematics are easily found and it is easy to make.
373 @item @b{Amontec - JTAG Accelerator}
374 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
377 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
380 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
381 Improved parallel-port wiggler-style JTAG adapter}
383 @item @b{Wiggler_ntrst_inverted}
384 @* Yet another variation - See the source code, src/jtag/parport.c
386 @item @b{old_amt_wiggler}
387 @* Unknown - probably not on the market today
390 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
393 @* Link: @url{http://www.amontec.com/chameleon.shtml}
399 @* ispDownload from Lattice Semiconductor
400 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
403 @* From ST Microsystems;
404 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
405 FlashLINK JTAG programing cable for PSD and uPSD}
413 @* An EP93xx based Linux machine using the GPIO pins directly.
416 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
421 @chapter About JIM-Tcl
425 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
426 This programming language provides a simple and extensible
429 All commands presented in this Guide are extensions to JIM-Tcl.
430 You can use them as simple commands, without needing to learn
431 much of anything about Tcl.
432 Alternatively, can write Tcl programs with them.
434 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
437 @item @b{JIM vs. Tcl}
438 @* JIM-TCL is a stripped down version of the well known Tcl language,
439 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
440 fewer features. JIM-Tcl is a single .C file and a single .H file and
441 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
442 4.2 MB .zip file containing 1540 files.
444 @item @b{Missing Features}
445 @* Our practice has been: Add/clone the real Tcl feature if/when
446 needed. We welcome JIM Tcl improvements, not bloat.
449 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
450 command interpreter today is a mixture of (newer)
451 JIM-Tcl commands, and (older) the orginal command interpreter.
454 @* At the OpenOCD telnet command line (or via the GDB mon command) one
455 can type a Tcl for() loop, set variables, etc.
456 Some of the commands documented in this guide are implemented
457 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
459 @item @b{Historical Note}
460 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
462 @item @b{Need a crash course in Tcl?}
463 @*@xref{Tcl Crash Course}.
468 @cindex command line options
470 @cindex directory search
472 The @option{--help} option shows:
476 --help | -h display this help
477 --version | -v display OpenOCD version
478 --file | -f use configuration file <name>
479 --search | -s dir to search for config files and scripts
480 --debug | -d set debug level <0-3>
481 --log_output | -l redirect log output to file <name>
482 --command | -c run <command>
483 --pipe | -p use pipes when talking to gdb
486 By default OpenOCD reads the configuration file @file{openocd.cfg}.
487 To specify a different (or multiple)
488 configuration file, you can use the @option{-f} option. For example:
491 openocd -f config1.cfg -f config2.cfg -f config3.cfg
494 Configuration files and scripts are searched for in
496 @item the current directory,
497 @item any search dir specified on the command line using the @option{-s} option,
498 @item @file{$HOME/.openocd} (not on Windows),
499 @item the site wide script library @file{$pkgdatadir/site} and
500 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
502 The first found file with a matching file name will be used.
504 @section Simple setup, no customization
506 In the best case, you can use two scripts from one of the script
507 libraries, hook up your JTAG adapter, and start the server ... and
508 your JTAG setup will just work "out of the box". Always try to
509 start by reusing those scripts, but assume you'll need more
510 customization even if this works. @xref{OpenOCD Project Setup}.
512 If you find a script for your JTAG adapter, and for your board or
513 target, you may be able to hook up your JTAG adapter then start
517 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
520 You might also need to configure which reset signals are present,
521 using @option{-c 'reset_config trst_and_srst'} or something similar.
522 If all goes well you'll see output something like
525 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
526 For bug reports, read
527 http://openocd.berlios.de/doc/doxygen/bugs.html
528 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
529 (mfg: 0x23b, part: 0xba00, ver: 0x3)
532 Seeing that "tap/device found" message, and no warnings, means
533 the JTAG communication is working. That's a key milestone, but
534 you'll probably need more project-specific setup.
536 @section What OpenOCD does as it starts
538 OpenOCD starts by processing the configuration commands provided
539 on the command line or, if there were no @option{-c command} or
540 @option{-f file.cfg} options given, in @file{openocd.cfg}.
541 @xref{Configuration Stage}.
542 At the end of the configuration stage it verifies the JTAG scan
543 chain defined using those commands; your configuration should
544 ensure that this always succeeds.
545 Normally, OpenOCD then starts running as a daemon.
546 Alternatively, commands may be used to terminate the configuration
547 stage early, perform work (such as updating some flash memory),
548 and then shut down without acting as a daemon.
550 Once OpenOCD starts running as a daemon, it waits for connections from
551 clients (Telnet, GDB, Other) and processes the commands issued through
554 If you are having problems, you can enable internal debug messages via
555 the @option{-d} option.
557 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
558 @option{-c} command line switch.
560 To enable debug output (when reporting problems or working on OpenOCD
561 itself), use the @option{-d} command line switch. This sets the
562 @option{debug_level} to "3", outputting the most information,
563 including debug messages. The default setting is "2", outputting only
564 informational messages, warnings and errors. You can also change this
565 setting from within a telnet or gdb session using @command{debug_level
566 <n>} (@pxref{debug_level}).
568 You can redirect all output from the daemon to a file using the
569 @option{-l <logfile>} switch.
571 For details on the @option{-p} option. @xref{Connecting to GDB}.
573 Note! OpenOCD will launch the GDB & telnet server even if it can not
574 establish a connection with the target. In general, it is possible for
575 the JTAG controller to be unresponsive until the target is set up
576 correctly via e.g. GDB monitor commands in a GDB init script.
578 @node OpenOCD Project Setup
579 @chapter OpenOCD Project Setup
581 To use OpenOCD with your development projects, you need to do more than
582 just connecting the JTAG adapter hardware (dongle) to your development board
583 and then starting the OpenOCD server.
584 You also need to configure that server so that it knows
585 about that adapter and board, and helps your work.
586 You may also want to connect OpenOCD to GDB, possibly
587 using Eclipse or some other GUI.
589 @section Hooking up the JTAG Adapter
591 Today's most common case is a dongle with a JTAG cable on one side
592 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
593 and a USB cable on the other.
594 Instead of USB, some cables use Ethernet;
595 older ones may use a PC parallel port, or even a serial port.
598 @item @emph{Start with power to your target board turned off},
599 and nothing connected to your JTAG adapter.
600 If you're particularly paranoid, unplug power to the board.
601 It's important to have the ground signal properly set up,
602 unless you are using a JTAG adapter which provides
603 galvanic isolation between the target board and the
606 @item @emph{Be sure it's the right kind of JTAG connector.}
607 If your dongle has a 20-pin ARM connector, you need some kind
608 of adapter (or octopus, see below) to hook it up to
609 boards using 14-pin or 10-pin connectors ... or to 20-pin
610 connectors which don't use ARM's pinout.
612 In the same vein, make sure the voltage levels are compatible.
613 Not all JTAG adapters have the level shifters needed to work
614 with 1.2 Volt boards.
616 @item @emph{Be certain the cable is properly oriented} or you might
617 damage your board. In most cases there are only two possible
618 ways to connect the cable.
619 Connect the JTAG cable from your adapter to the board.
620 Be sure it's firmly connected.
622 In the best case, the connector is keyed to physically
623 prevent you from inserting it wrong.
624 This is most often done using a slot on the board's male connector
625 housing, which must match a key on the JTAG cable's female connector.
626 If there's no housing, then you must look carefully and
627 make sure pin 1 on the cable hooks up to pin 1 on the board.
628 Ribbon cables are frequently all grey except for a wire on one
629 edge, which is red. The red wire is pin 1.
631 Sometimes dongles provide cables where one end is an ``octopus'' of
632 color coded single-wire connectors, instead of a connector block.
633 These are great when converting from one JTAG pinout to another,
634 but are tedious to set up.
635 Use these with connector pinout diagrams to help you match up the
636 adapter signals to the right board pins.
638 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
639 A USB, parallel, or serial port connector will go to the host which
640 you are using to run OpenOCD.
641 For Ethernet, consult the documentation and your network administrator.
643 For USB based JTAG adapters you have an easy sanity check at this point:
644 does the host operating system see the JTAG adapter? If that host is an
645 MS-Windows host, you'll need to install a driver before OpenOCD works.
647 @item @emph{Connect the adapter's power supply, if needed.}
648 This step is primarily for non-USB adapters,
649 but sometimes USB adapters need extra power.
651 @item @emph{Power up the target board.}
652 Unless you just let the magic smoke escape,
653 you're now ready to set up the OpenOCD server
654 so you can use JTAG to work with that board.
658 Talk with the OpenOCD server using
659 telnet (@code{telnet localhost 4444} on many systems) or GDB.
660 @xref{GDB and OpenOCD}.
662 @section Project Directory
664 There are many ways you can configure OpenOCD and start it up.
666 A simple way to organize them all involves keeping a
667 single directory for your work with a given board.
668 When you start OpenOCD from that directory,
669 it searches there first for configuration files, scripts,
670 files accessed through semihosting,
671 and for code you upload to the target board.
672 It is also the natural place to write files,
673 such as log files and data you download from the board.
675 @section Configuration Basics
677 There are two basic ways of configuring OpenOCD, and
678 a variety of ways you can mix them.
679 Think of the difference as just being how you start the server:
682 @item Many @option{-f file} or @option{-c command} options on the command line
683 @item No options, but a @dfn{user config file}
684 in the current directory named @file{openocd.cfg}
687 Here is an example @file{openocd.cfg} file for a setup
688 using a Signalyzer FT2232-based JTAG adapter to talk to
689 a board with an Atmel AT91SAM7X256 microcontroller:
692 source [find interface/signalyzer.cfg]
694 # GDB can also flash my flash!
695 gdb_memory_map enable
696 gdb_flash_program enable
698 source [find target/sam7x256.cfg]
701 Here is the command line equivalent of that configuration:
704 openocd -f interface/signalyzer.cfg \
705 -c "gdb_memory_map enable" \
706 -c "gdb_flash_program enable" \
707 -f target/sam7x256.cfg
710 You could wrap such long command lines in shell scripts,
711 each supporting a different development task.
712 One might re-flash the board with a specific firmware version.
713 Another might set up a particular debugging or run-time environment.
716 At this writing (October 2009) the command line method has
717 problems with how it treats variables.
718 For example, after @option{-c "set VAR value"}, or doing the
719 same in a script, the variable @var{VAR} will have no value
720 that can be tested in a later script.
723 Here we will focus on the simpler solution: one user config
724 file, including basic configuration plus any TCL procedures
725 to simplify your work.
727 @section User Config Files
728 @cindex config file, user
729 @cindex user config file
730 @cindex config file, overview
732 A user configuration file ties together all the parts of a project
734 One of the following will match your situation best:
737 @item Ideally almost everything comes from configuration files
738 provided by someone else.
739 For example, OpenOCD distributes a @file{scripts} directory
740 (probably in @file{/usr/share/openocd/scripts} on Linux).
741 Board and tool vendors can provide these too, as can individual
742 user sites; the @option{-s} command line option lets you say
743 where to find these files. (@xref{Running}.)
744 The AT91SAM7X256 example above works this way.
746 Three main types of non-user configuration file each have their
747 own subdirectory in the @file{scripts} directory:
750 @item @b{interface} -- one for each kind of JTAG adapter/dongle
751 @item @b{board} -- one for each different board
752 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
755 Best case: include just two files, and they handle everything else.
756 The first is an interface config file.
757 The second is board-specific, and it sets up the JTAG TAPs and
758 their GDB targets (by deferring to some @file{target.cfg} file),
759 declares all flash memory, and leaves you nothing to do except
763 source [find interface/olimex-jtag-tiny.cfg]
764 source [find board/csb337.cfg]
767 Boards with a single microcontroller often won't need more
768 than the target config file, as in the AT91SAM7X256 example.
769 That's because there is no external memory (flash, DDR RAM), and
770 the board differences are encapsulated by application code.
772 @item Maybe you don't know yet what your board looks like to JTAG.
773 Once you know the @file{interface.cfg} file to use, you may
774 need help from OpenOCD to discover what's on the board.
775 Once you find the TAPs, you can just search for appropriate
776 configuration files ... or write your own, from the bottom up.
779 @item You can often reuse some standard config files but
780 need to write a few new ones, probably a @file{board.cfg} file.
781 You will be using commands described later in this User's Guide,
782 and working with the guidelines in the next chapter.
784 For example, there may be configuration files for your JTAG adapter
785 and target chip, but you need a new board-specific config file
786 giving access to your particular flash chips.
787 Or you might need to write another target chip configuration file
788 for a new chip built around the Cortex M3 core.
791 When you write new configuration files, please submit
792 them for inclusion in the next OpenOCD release.
793 For example, a @file{board/newboard.cfg} file will help the
794 next users of that board, and a @file{target/newcpu.cfg}
795 will help support users of any board using that chip.
799 You may may need to write some C code.
800 It may be as simple as a supporting a new ft2232 or parport
801 based dongle; a bit more involved, like a NAND or NOR flash
802 controller driver; or a big piece of work like supporting
803 a new chip architecture.
806 Reuse the existing config files when you can.
807 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
808 You may find a board configuration that's a good example to follow.
810 When you write config files, separate the reusable parts
811 (things every user of that interface, chip, or board needs)
812 from ones specific to your environment and debugging approach.
816 For example, a @code{gdb-attach} event handler that invokes
817 the @command{reset init} command will interfere with debugging
818 early boot code, which performs some of the same actions
819 that the @code{reset-init} event handler does.
822 Likewise, the @command{arm9 vector_catch} command (or
824 its siblings @command{xscale vector_catch}
825 and @command{cortex_m3 vector_catch}) can be a timesaver
826 during some debug sessions, but don't make everyone use that either.
827 Keep those kinds of debugging aids in your user config file,
828 along with messaging and tracing setup.
829 (@xref{Software Debug Messages and Tracing}.)
832 You might need to override some defaults.
833 For example, you might need to move, shrink, or back up the target's
834 work area if your application needs much SRAM.
837 TCP/IP port configuration is another example of something which
838 is environment-specific, and should only appear in
839 a user config file. @xref{TCP/IP Ports}.
842 @section Project-Specific Utilities
844 A few project-specific utility
845 routines may well speed up your work.
846 Write them, and keep them in your project's user config file.
848 For example, if you are making a boot loader work on a
849 board, it's nice to be able to debug the ``after it's
850 loaded to RAM'' parts separately from the finicky early
851 code which sets up the DDR RAM controller and clocks.
852 A script like this one, or a more GDB-aware sibling,
856 proc ramboot @{ @} @{
857 # Reset, running the target's "reset-init" scripts
858 # to initialize clocks and the DDR RAM controller.
859 # Leave the CPU halted.
862 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
863 load_image u-boot.bin 0x20000000
870 Then once that code is working you will need to make it
871 boot from NOR flash; a different utility would help.
872 Alternatively, some developers write to flash using GDB.
873 (You might use a similar script if you're working with a flash
874 based microcontroller application instead of a boot loader.)
877 proc newboot @{ @} @{
878 # Reset, leaving the CPU halted. The "reset-init" event
879 # proc gives faster access to the CPU and to NOR flash;
880 # "reset halt" would be slower.
883 # Write standard version of U-Boot into the first two
884 # sectors of NOR flash ... the standard version should
885 # do the same lowlevel init as "reset-init".
886 flash protect 0 0 1 off
887 flash erase_sector 0 0 1
888 flash write_bank 0 u-boot.bin 0x0
889 flash protect 0 0 1 on
891 # Reboot from scratch using that new boot loader.
896 You may need more complicated utility procedures when booting
898 That often involves an extra bootloader stage,
899 running from on-chip SRAM to perform DDR RAM setup so it can load
900 the main bootloader code (which won't fit into that SRAM).
902 Other helper scripts might be used to write production system images,
903 involving considerably more than just a three stage bootloader.
905 @section Target Software Changes
907 Sometimes you may want to make some small changes to the software
908 you're developing, to help make JTAG debugging work better.
909 For example, in C or assembly language code you might
910 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
911 handling issues like:
915 @item @b{ARM Semihosting}...
916 @cindex ARM semihosting
917 When linked with a special runtime library provided with many
918 toolchains@footnote{See chapter 8 "Semihosting" in
919 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
920 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
921 The CodeSourcery EABI toolchain also includes a semihosting library.},
922 your target code can use I/O facilities on the debug host. That library
923 provides a small set of system calls which are handled by OpenOCD.
924 It can let the debugger provide your system console and a file system,
925 helping with early debugging or providing a more capable environment
926 for sometimes-complex tasks like installing system firmware onto
929 @item @b{ARM Wait-For-Interrupt}...
930 Many ARM chips synchronize the JTAG clock using the core clock.
931 Low power states which stop that core clock thus prevent JTAG access.
932 Idle loops in tasking environments often enter those low power states
933 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
935 You may want to @emph{disable that instruction} in source code,
936 or otherwise prevent using that state,
937 to ensure you can get JTAG access at any time.
938 For example, the OpenOCD @command{halt} command may not
939 work for an idle processor otherwise.
941 @item @b{Delay after reset}...
942 Not all chips have good support for debugger access
943 right after reset; many LPC2xxx chips have issues here.
944 Similarly, applications that reconfigure pins used for
945 JTAG access as they start will also block debugger access.
947 To work with boards like this, @emph{enable a short delay loop}
948 the first thing after reset, before "real" startup activities.
949 For example, one second's delay is usually more than enough
950 time for a JTAG debugger to attach, so that
951 early code execution can be debugged
952 or firmware can be replaced.
954 @item @b{Debug Communications Channel (DCC)}...
955 Some processors include mechanisms to send messages over JTAG.
956 Many ARM cores support these, as do some cores from other vendors.
957 (OpenOCD may be able to use this DCC internally, speeding up some
958 operations like writing to memory.)
960 Your application may want to deliver various debugging messages
961 over JTAG, by @emph{linking with a small library of code}
962 provided with OpenOCD and using the utilities there to send
963 various kinds of message.
964 @xref{Software Debug Messages and Tracing}.
968 @node Config File Guidelines
969 @chapter Config File Guidelines
971 This chapter is aimed at any user who needs to write a config file,
972 including developers and integrators of OpenOCD and any user who
973 needs to get a new board working smoothly.
974 It provides guidelines for creating those files.
976 You should find the following directories under @t{$(INSTALLDIR)/scripts},
977 with files including the ones listed here.
978 Use them as-is where you can; or as models for new files.
980 @item @file{interface} ...
981 think JTAG Dongle. Files that configure JTAG adapters go here.
984 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
985 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
986 at91rm9200.cfg jlink.cfg parport.cfg
987 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
988 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
989 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
990 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
991 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
992 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
993 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
994 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
997 @item @file{board} ...
998 think Circuit Board, PWA, PCB, they go by many names. Board files
999 contain initialization items that are specific to a board.
1000 They reuse target configuration files, since the same
1001 microprocessor chips are used on many boards,
1002 but support for external parts varies widely. For
1003 example, the SDRAM initialization sequence for the board, or the type
1004 of external flash and what address it uses. Any initialization
1005 sequence to enable that external flash or SDRAM should be found in the
1006 board file. Boards may also contain multiple targets: two CPUs; or
1010 arm_evaluator7t.cfg keil_mcb1700.cfg
1011 at91rm9200-dk.cfg keil_mcb2140.cfg
1012 at91sam9g20-ek.cfg linksys_nslu2.cfg
1013 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1014 atmel_at91sam9260-ek.cfg mini2440.cfg
1015 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1016 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1017 csb337.cfg olimex_sam7_ex256.cfg
1018 csb732.cfg olimex_sam9_l9260.cfg
1019 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1020 dm355evm.cfg omap2420_h4.cfg
1021 dm365evm.cfg osk5912.cfg
1022 dm6446evm.cfg pic-p32mx.cfg
1023 eir.cfg propox_mmnet1001.cfg
1024 ek-lm3s1968.cfg pxa255_sst.cfg
1025 ek-lm3s3748.cfg sheevaplug.cfg
1026 ek-lm3s811.cfg stm3210e_eval.cfg
1027 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1028 hammer.cfg str910-eval.cfg
1029 hitex_lpc2929.cfg telo.cfg
1030 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1031 hitex_str9-comstick.cfg topas910.cfg
1032 iar_str912_sk.cfg topasa900.cfg
1033 imx27ads.cfg unknown_at91sam9260.cfg
1034 imx27lnst.cfg x300t.cfg
1035 imx31pdk.cfg zy1000.cfg
1038 @item @file{target} ...
1039 think chip. The ``target'' directory represents the JTAG TAPs
1041 which OpenOCD should control, not a board. Two common types of targets
1042 are ARM chips and FPGA or CPLD chips.
1043 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1044 the target config file defines all of them.
1047 aduc702x.cfg imx27.cfg pxa255.cfg
1048 ar71xx.cfg imx31.cfg pxa270.cfg
1049 at91eb40a.cfg imx35.cfg readme.txt
1050 at91r40008.cfg is5114.cfg sam7se512.cfg
1051 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1052 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1053 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1054 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1055 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1056 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1057 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1058 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1059 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1060 at91sam9260.cfg lpc2129.cfg stm32.cfg
1061 c100.cfg lpc2148.cfg str710.cfg
1062 c100config.tcl lpc2294.cfg str730.cfg
1063 c100helper.tcl lpc2378.cfg str750.cfg
1064 c100regs.tcl lpc2478.cfg str912.cfg
1065 cs351x.cfg lpc2900.cfg telo.cfg
1066 davinci.cfg mega128.cfg ti_dm355.cfg
1067 dragonite.cfg netx500.cfg ti_dm365.cfg
1068 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1069 feroceon.cfg omap3530.cfg tmpa900.cfg
1070 icepick.cfg omap5912.cfg tmpa910.cfg
1071 imx21.cfg pic32mx.cfg xba_revA3.cfg
1074 @item @emph{more} ... browse for other library files which may be useful.
1075 For example, there are various generic and CPU-specific utilities.
1078 The @file{openocd.cfg} user config
1079 file may override features in any of the above files by
1080 setting variables before sourcing the target file, or by adding
1081 commands specific to their situation.
1083 @section Interface Config Files
1085 The user config file
1086 should be able to source one of these files with a command like this:
1089 source [find interface/FOOBAR.cfg]
1092 A preconfigured interface file should exist for every interface in use
1093 today, that said, perhaps some interfaces have only been used by the
1094 sole developer who created it.
1096 A separate chapter gives information about how to set these up.
1097 @xref{Interface - Dongle Configuration}.
1098 Read the OpenOCD source code if you have a new kind of hardware interface
1099 and need to provide a driver for it.
1101 @section Board Config Files
1102 @cindex config file, board
1103 @cindex board config file
1105 The user config file
1106 should be able to source one of these files with a command like this:
1109 source [find board/FOOBAR.cfg]
1112 The point of a board config file is to package everything
1113 about a given board that user config files need to know.
1114 In summary the board files should contain (if present)
1117 @item One or more @command{source [target/...cfg]} statements
1118 @item NOR flash configuration (@pxref{NOR Configuration})
1119 @item NAND flash configuration (@pxref{NAND Configuration})
1120 @item Target @code{reset} handlers for SDRAM and I/O configuration
1121 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1122 @item All things that are not ``inside a chip''
1125 Generic things inside target chips belong in target config files,
1126 not board config files. So for example a @code{reset-init} event
1127 handler should know board-specific oscillator and PLL parameters,
1128 which it passes to target-specific utility code.
1130 The most complex task of a board config file is creating such a
1131 @code{reset-init} event handler.
1132 Define those handlers last, after you verify the rest of the board
1133 configuration works.
1135 @subsection Communication Between Config files
1137 In addition to target-specific utility code, another way that
1138 board and target config files communicate is by following a
1139 convention on how to use certain variables.
1141 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1142 Thus the rule we follow in OpenOCD is this: Variables that begin with
1143 a leading underscore are temporary in nature, and can be modified and
1144 used at will within a target configuration file.
1146 Complex board config files can do the things like this,
1147 for a board with three chips:
1150 # Chip #1: PXA270 for network side, big endian
1151 set CHIPNAME network
1153 source [find target/pxa270.cfg]
1154 # on return: _TARGETNAME = network.cpu
1155 # other commands can refer to the "network.cpu" target.
1156 $_TARGETNAME configure .... events for this CPU..
1158 # Chip #2: PXA270 for video side, little endian
1161 source [find target/pxa270.cfg]
1162 # on return: _TARGETNAME = video.cpu
1163 # other commands can refer to the "video.cpu" target.
1164 $_TARGETNAME configure .... events for this CPU..
1166 # Chip #3: Xilinx FPGA for glue logic
1169 source [find target/spartan3.cfg]
1172 That example is oversimplified because it doesn't show any flash memory,
1173 or the @code{reset-init} event handlers to initialize external DRAM
1174 or (assuming it needs it) load a configuration into the FPGA.
1175 Such features are usually needed for low-level work with many boards,
1176 where ``low level'' implies that the board initialization software may
1177 not be working. (That's a common reason to need JTAG tools. Another
1178 is to enable working with microcontroller-based systems, which often
1179 have no debugging support except a JTAG connector.)
1181 Target config files may also export utility functions to board and user
1182 config files. Such functions should use name prefixes, to help avoid
1185 Board files could also accept input variables from user config files.
1186 For example, there might be a @code{J4_JUMPER} setting used to identify
1187 what kind of flash memory a development board is using, or how to set
1188 up other clocks and peripherals.
1190 @subsection Variable Naming Convention
1191 @cindex variable names
1193 Most boards have only one instance of a chip.
1194 However, it should be easy to create a board with more than
1195 one such chip (as shown above).
1196 Accordingly, we encourage these conventions for naming
1197 variables associated with different @file{target.cfg} files,
1198 to promote consistency and
1199 so that board files can override target defaults.
1201 Inputs to target config files include:
1204 @item @code{CHIPNAME} ...
1205 This gives a name to the overall chip, and is used as part of
1206 tap identifier dotted names.
1207 While the default is normally provided by the chip manufacturer,
1208 board files may need to distinguish between instances of a chip.
1209 @item @code{ENDIAN} ...
1210 By default @option{little} - although chips may hard-wire @option{big}.
1211 Chips that can't change endianness don't need to use this variable.
1212 @item @code{CPUTAPID} ...
1213 When OpenOCD examines the JTAG chain, it can be told verify the
1214 chips against the JTAG IDCODE register.
1215 The target file will hold one or more defaults, but sometimes the
1216 chip in a board will use a different ID (perhaps a newer revision).
1219 Outputs from target config files include:
1222 @item @code{_TARGETNAME} ...
1223 By convention, this variable is created by the target configuration
1224 script. The board configuration file may make use of this variable to
1225 configure things like a ``reset init'' script, or other things
1226 specific to that board and that target.
1227 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1228 @code{_TARGETNAME1}, ... etc.
1231 @subsection The reset-init Event Handler
1232 @cindex event, reset-init
1233 @cindex reset-init handler
1235 Board config files run in the OpenOCD configuration stage;
1236 they can't use TAPs or targets, since they haven't been
1238 This means you can't write memory or access chip registers;
1239 you can't even verify that a flash chip is present.
1240 That's done later in event handlers, of which the target @code{reset-init}
1241 handler is one of the most important.
1243 Except on microcontrollers, the basic job of @code{reset-init} event
1244 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1245 Microcontrollers rarely use boot loaders; they run right out of their
1246 on-chip flash and SRAM memory. But they may want to use one of these
1247 handlers too, if just for developer convenience.
1250 Because this is so very board-specific, and chip-specific, no examples
1252 Instead, look at the board config files distributed with OpenOCD.
1253 If you have a boot loader, its source code will help; so will
1254 configuration files for other JTAG tools
1255 (@pxref{Translating Configuration Files}).
1258 Some of this code could probably be shared between different boards.
1259 For example, setting up a DRAM controller often doesn't differ by
1260 much except the bus width (16 bits or 32?) and memory timings, so a
1261 reusable TCL procedure loaded by the @file{target.cfg} file might take
1262 those as parameters.
1263 Similarly with oscillator, PLL, and clock setup;
1264 and disabling the watchdog.
1265 Structure the code cleanly, and provide comments to help
1266 the next developer doing such work.
1267 (@emph{You might be that next person} trying to reuse init code!)
1269 The last thing normally done in a @code{reset-init} handler is probing
1270 whatever flash memory was configured. For most chips that needs to be
1271 done while the associated target is halted, either because JTAG memory
1272 access uses the CPU or to prevent conflicting CPU access.
1274 @subsection JTAG Clock Rate
1276 Before your @code{reset-init} handler has set up
1277 the PLLs and clocking, you may need to run with
1278 a low JTAG clock rate.
1280 Then you'd increase that rate after your handler has
1281 made it possible to use the faster JTAG clock.
1282 When the initial low speed is board-specific, for example
1283 because it depends on a board-specific oscillator speed, then
1284 you should probably set it up in the board config file;
1285 if it's target-specific, it belongs in the target config file.
1287 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1288 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1289 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1290 Consult chip documentation to determine the peak JTAG clock rate,
1291 which might be less than that.
1294 On most ARMs, JTAG clock detection is coupled to the core clock, so
1295 software using a @option{wait for interrupt} operation blocks JTAG access.
1296 Adaptive clocking provides a partial workaround, but a more complete
1297 solution just avoids using that instruction with JTAG debuggers.
1300 If the board supports adaptive clocking, use the @command{jtag_rclk}
1301 command, in case your board is used with JTAG adapter which
1302 also supports it. Otherwise use @command{jtag_khz}.
1303 Set the slow rate at the beginning of the reset sequence,
1304 and the faster rate as soon as the clocks are at full speed.
1306 @section Target Config Files
1307 @cindex config file, target
1308 @cindex target config file
1310 Board config files communicate with target config files using
1311 naming conventions as described above, and may source one or
1312 more target config files like this:
1315 source [find target/FOOBAR.cfg]
1318 The point of a target config file is to package everything
1319 about a given chip that board config files need to know.
1320 In summary the target files should contain
1324 @item Add TAPs to the scan chain
1325 @item Add CPU targets (includes GDB support)
1326 @item CPU/Chip/CPU-Core specific features
1330 As a rule of thumb, a target file sets up only one chip.
1331 For a microcontroller, that will often include a single TAP,
1332 which is a CPU needing a GDB target, and its on-chip flash.
1334 More complex chips may include multiple TAPs, and the target
1335 config file may need to define them all before OpenOCD
1336 can talk to the chip.
1337 For example, some phone chips have JTAG scan chains that include
1338 an ARM core for operating system use, a DSP,
1339 another ARM core embedded in an image processing engine,
1340 and other processing engines.
1342 @subsection Default Value Boiler Plate Code
1344 All target configuration files should start with code like this,
1345 letting board config files express environment-specific
1346 differences in how things should be set up.
1349 # Boards may override chip names, perhaps based on role,
1350 # but the default should match what the vendor uses
1351 if @{ [info exists CHIPNAME] @} @{
1352 set _CHIPNAME $CHIPNAME
1354 set _CHIPNAME sam7x256
1357 # ONLY use ENDIAN with targets that can change it.
1358 if @{ [info exists ENDIAN] @} @{
1364 # TAP identifiers may change as chips mature, for example with
1365 # new revision fields (the "3" here). Pick a good default; you
1366 # can pass several such identifiers to the "jtag newtap" command.
1367 if @{ [info exists CPUTAPID ] @} @{
1368 set _CPUTAPID $CPUTAPID
1370 set _CPUTAPID 0x3f0f0f0f
1373 @c but 0x3f0f0f0f is for an str73x part ...
1375 @emph{Remember:} Board config files may include multiple target
1376 config files, or the same target file multiple times
1377 (changing at least @code{CHIPNAME}).
1379 Likewise, the target configuration file should define
1380 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1381 use it later on when defining debug targets:
1384 set _TARGETNAME $_CHIPNAME.cpu
1385 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1388 @subsection Adding TAPs to the Scan Chain
1389 After the ``defaults'' are set up,
1390 add the TAPs on each chip to the JTAG scan chain.
1391 @xref{TAP Declaration}, and the naming convention
1394 In the simplest case the chip has only one TAP,
1395 probably for a CPU or FPGA.
1396 The config file for the Atmel AT91SAM7X256
1397 looks (in part) like this:
1400 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1403 A board with two such at91sam7 chips would be able
1404 to source such a config file twice, with different
1405 values for @code{CHIPNAME}, so
1406 it adds a different TAP each time.
1408 If there are nonzero @option{-expected-id} values,
1409 OpenOCD attempts to verify the actual tap id against those values.
1410 It will issue error messages if there is mismatch, which
1411 can help to pinpoint problems in OpenOCD configurations.
1414 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1415 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1416 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1417 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1418 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1421 There are more complex examples too, with chips that have
1422 multiple TAPs. Ones worth looking at include:
1425 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1426 plus a JRC to enable them
1427 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1428 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1429 is not currently used)
1432 @subsection Add CPU targets
1434 After adding a TAP for a CPU, you should set it up so that
1435 GDB and other commands can use it.
1436 @xref{CPU Configuration}.
1437 For the at91sam7 example above, the command can look like this;
1438 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1439 to little endian, and this chip doesn't support changing that.
1442 set _TARGETNAME $_CHIPNAME.cpu
1443 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1446 Work areas are small RAM areas associated with CPU targets.
1447 They are used by OpenOCD to speed up downloads,
1448 and to download small snippets of code to program flash chips.
1449 If the chip includes a form of ``on-chip-ram'' - and many do - define
1450 a work area if you can.
1451 Again using the at91sam7 as an example, this can look like:
1454 $_TARGETNAME configure -work-area-phys 0x00200000 \
1455 -work-area-size 0x4000 -work-area-backup 0
1458 @subsection Chip Reset Setup
1460 As a rule, you should put the @command{reset_config} command
1461 into the board file. Most things you think you know about a
1462 chip can be tweaked by the board.
1464 Some chips have specific ways the TRST and SRST signals are
1465 managed. In the unusual case that these are @emph{chip specific}
1466 and can never be changed by board wiring, they could go here.
1467 For example, some chips can't support JTAG debugging without
1470 Provide a @code{reset-assert} event handler if you can.
1471 Such a handler uses JTAG operations to reset the target,
1472 letting this target config be used in systems which don't
1473 provide the optional SRST signal, or on systems where you
1474 don't want to reset all targets at once.
1475 Such a handler might write to chip registers to force a reset,
1476 use a JRC to do that (preferable -- the target may be wedged!),
1477 or force a watchdog timer to trigger.
1478 (For Cortex-M3 targets, this is not necessary. The target
1479 driver knows how to use trigger an NVIC reset when SRST is
1482 Some chips need special attention during reset handling if
1483 they're going to be used with JTAG.
1484 An example might be needing to send some commands right
1485 after the target's TAP has been reset, providing a
1486 @code{reset-deassert-post} event handler that writes a chip
1487 register to report that JTAG debugging is being done.
1488 Another would be reconfiguring the watchdog so that it stops
1489 counting while the core is halted in the debugger.
1491 JTAG clocking constraints often change during reset, and in
1492 some cases target config files (rather than board config files)
1493 are the right places to handle some of those issues.
1494 For example, immediately after reset most chips run using a
1495 slower clock than they will use later.
1496 That means that after reset (and potentially, as OpenOCD
1497 first starts up) they must use a slower JTAG clock rate
1498 than they will use later.
1501 @quotation Important
1502 When you are debugging code that runs right after chip
1503 reset, getting these issues right is critical.
1504 In particular, if you see intermittent failures when
1505 OpenOCD verifies the scan chain after reset,
1506 look at how you are setting up JTAG clocking.
1509 @subsection ARM Core Specific Hacks
1511 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1512 special high speed download features - enable it.
1514 If present, the MMU, the MPU and the CACHE should be disabled.
1516 Some ARM cores are equipped with trace support, which permits
1517 examination of the instruction and data bus activity. Trace
1518 activity is controlled through an ``Embedded Trace Module'' (ETM)
1519 on one of the core's scan chains. The ETM emits voluminous data
1520 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1521 If you are using an external trace port,
1522 configure it in your board config file.
1523 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1524 configure it in your target config file.
1527 etm config $_TARGETNAME 16 normal full etb
1528 etb config $_TARGETNAME $_CHIPNAME.etb
1531 @subsection Internal Flash Configuration
1533 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1535 @b{Never ever} in the ``target configuration file'' define any type of
1536 flash that is external to the chip. (For example a BOOT flash on
1537 Chip Select 0.) Such flash information goes in a board file - not
1538 the TARGET (chip) file.
1542 @item at91sam7x256 - has 256K flash YES enable it.
1543 @item str912 - has flash internal YES enable it.
1544 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1545 @item pxa270 - again - CS0 flash - it goes in the board file.
1548 @anchor{Translating Configuration Files}
1549 @section Translating Configuration Files
1551 If you have a configuration file for another hardware debugger
1552 or toolset (Abatron, BDI2000, BDI3000, CCS,
1553 Lauterbach, Segger, Macraigor, etc.), translating
1554 it into OpenOCD syntax is often quite straightforward. The most tricky
1555 part of creating a configuration script is oftentimes the reset init
1556 sequence where e.g. PLLs, DRAM and the like is set up.
1558 One trick that you can use when translating is to write small
1559 Tcl procedures to translate the syntax into OpenOCD syntax. This
1560 can avoid manual translation errors and make it easier to
1561 convert other scripts later on.
1563 Example of transforming quirky arguments to a simple search and
1567 # Lauterbach syntax(?)
1569 # Data.Set c15:0x042f %long 0x40000015
1571 # OpenOCD syntax when using procedure below.
1573 # setc15 0x01 0x00050078
1575 proc setc15 @{regs value@} @{
1578 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1580 arm mcr 15 [expr ($regs>>12)&0x7] \
1581 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1582 [expr ($regs>>8)&0x7] $value
1588 @node Daemon Configuration
1589 @chapter Daemon Configuration
1590 @cindex initialization
1591 The commands here are commonly found in the openocd.cfg file and are
1592 used to specify what TCP/IP ports are used, and how GDB should be
1595 @anchor{Configuration Stage}
1596 @section Configuration Stage
1597 @cindex configuration stage
1598 @cindex config command
1600 When the OpenOCD server process starts up, it enters a
1601 @emph{configuration stage} which is the only time that
1602 certain commands, @emph{configuration commands}, may be issued.
1603 In this manual, the definition of a configuration command is
1604 presented as a @emph{Config Command}, not as a @emph{Command}
1605 which may be issued interactively.
1607 Those configuration commands include declaration of TAPs,
1609 the interface used for JTAG communication,
1610 and other basic setup.
1611 The server must leave the configuration stage before it
1612 may access or activate TAPs.
1613 After it leaves this stage, configuration commands may no
1616 @section Entering the Run Stage
1618 The first thing OpenOCD does after leaving the configuration
1619 stage is to verify that it can talk to the scan chain
1620 (list of TAPs) which has been configured.
1621 It will warn if it doesn't find TAPs it expects to find,
1622 or finds TAPs that aren't supposed to be there.
1623 You should see no errors at this point.
1624 If you see errors, resolve them by correcting the
1625 commands you used to configure the server.
1626 Common errors include using an initial JTAG speed that's too
1627 fast, and not providing the right IDCODE values for the TAPs
1630 Once OpenOCD has entered the run stage, a number of commands
1632 A number of these relate to the debug targets you may have declared.
1633 For example, the @command{mww} command will not be available until
1634 a target has been successfuly instantiated.
1635 If you want to use those commands, you may need to force
1636 entry to the run stage.
1638 @deffn {Config Command} init
1639 This command terminates the configuration stage and
1640 enters the run stage. This helps when you need to have
1641 the startup scripts manage tasks such as resetting the target,
1642 programming flash, etc. To reset the CPU upon startup, add "init" and
1643 "reset" at the end of the config script or at the end of the OpenOCD
1644 command line using the @option{-c} command line switch.
1646 If this command does not appear in any startup/configuration file
1647 OpenOCD executes the command for you after processing all
1648 configuration files and/or command line options.
1650 @b{NOTE:} This command normally occurs at or near the end of your
1651 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1652 targets ready. For example: If your openocd.cfg file needs to
1653 read/write memory on your target, @command{init} must occur before
1654 the memory read/write commands. This includes @command{nand probe}.
1657 @deffn {Overridable Procedure} jtag_init
1658 This is invoked at server startup to verify that it can talk
1659 to the scan chain (list of TAPs) which has been configured.
1661 The default implementation first tries @command{jtag arp_init},
1662 which uses only a lightweight JTAG reset before examining the
1664 If that fails, it tries again, using a harder reset
1665 from the overridable procedure @command{init_reset}.
1667 Implementations must have verified the JTAG scan chain before
1669 This is done by calling @command{jtag arp_init}
1670 (or @command{jtag arp_init-reset}).
1673 @anchor{TCP/IP Ports}
1674 @section TCP/IP Ports
1679 The OpenOCD server accepts remote commands in several syntaxes.
1680 Each syntax uses a different TCP/IP port, which you may specify
1681 only during configuration (before those ports are opened).
1683 For reasons including security, you may wish to prevent remote
1684 access using one or more of these ports.
1685 In such cases, just specify the relevant port number as zero.
1686 If you disable all access through TCP/IP, you will need to
1687 use the command line @option{-pipe} option.
1689 @deffn {Command} gdb_port (number)
1691 Specify or query the first port used for incoming GDB connections.
1692 The GDB port for the
1693 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1694 When not specified during the configuration stage,
1695 the port @var{number} defaults to 3333.
1696 When specified as zero, this port is not activated.
1699 @deffn {Command} tcl_port (number)
1700 Specify or query the port used for a simplified RPC
1701 connection that can be used by clients to issue TCL commands and get the
1702 output from the Tcl engine.
1703 Intended as a machine interface.
1704 When not specified during the configuration stage,
1705 the port @var{number} defaults to 6666.
1706 When specified as zero, this port is not activated.
1709 @deffn {Command} telnet_port (number)
1710 Specify or query the
1711 port on which to listen for incoming telnet connections.
1712 This port is intended for interaction with one human through TCL commands.
1713 When not specified during the configuration stage,
1714 the port @var{number} defaults to 4444.
1715 When specified as zero, this port is not activated.
1718 @anchor{GDB Configuration}
1719 @section GDB Configuration
1721 @cindex GDB configuration
1722 You can reconfigure some GDB behaviors if needed.
1723 The ones listed here are static and global.
1724 @xref{Target Configuration}, about configuring individual targets.
1725 @xref{Target Events}, about configuring target-specific event handling.
1727 @anchor{gdb_breakpoint_override}
1728 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1729 Force breakpoint type for gdb @command{break} commands.
1730 This option supports GDB GUIs which don't
1731 distinguish hard versus soft breakpoints, if the default OpenOCD and
1732 GDB behaviour is not sufficient. GDB normally uses hardware
1733 breakpoints if the memory map has been set up for flash regions.
1736 @anchor{gdb_flash_program}
1737 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1738 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1739 vFlash packet is received.
1740 The default behaviour is @option{enable}.
1743 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1744 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1745 requested. GDB will then know when to set hardware breakpoints, and program flash
1746 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1747 for flash programming to work.
1748 Default behaviour is @option{enable}.
1749 @xref{gdb_flash_program}.
1752 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1753 Specifies whether data aborts cause an error to be reported
1754 by GDB memory read packets.
1755 The default behaviour is @option{disable};
1756 use @option{enable} see these errors reported.
1759 @anchor{Event Polling}
1760 @section Event Polling
1762 Hardware debuggers are parts of asynchronous systems,
1763 where significant events can happen at any time.
1764 The OpenOCD server needs to detect some of these events,
1765 so it can report them to through TCL command line
1768 Examples of such events include:
1771 @item One of the targets can stop running ... maybe it triggers
1772 a code breakpoint or data watchpoint, or halts itself.
1773 @item Messages may be sent over ``debug message'' channels ... many
1774 targets support such messages sent over JTAG,
1775 for receipt by the person debugging or tools.
1776 @item Loss of power ... some adapters can detect these events.
1777 @item Resets not issued through JTAG ... such reset sources
1778 can include button presses or other system hardware, sometimes
1779 including the target itself (perhaps through a watchdog).
1780 @item Debug instrumentation sometimes supports event triggering
1781 such as ``trace buffer full'' (so it can quickly be emptied)
1782 or other signals (to correlate with code behavior).
1785 None of those events are signaled through standard JTAG signals.
1786 However, most conventions for JTAG connectors include voltage
1787 level and system reset (SRST) signal detection.
1788 Some connectors also include instrumentation signals, which
1789 can imply events when those signals are inputs.
1791 In general, OpenOCD needs to periodically check for those events,
1792 either by looking at the status of signals on the JTAG connector
1793 or by sending synchronous ``tell me your status'' JTAG requests
1794 to the various active targets.
1795 There is a command to manage and monitor that polling,
1796 which is normally done in the background.
1798 @deffn Command poll [@option{on}|@option{off}]
1799 Poll the current target for its current state.
1800 (Also, @pxref{target curstate}.)
1801 If that target is in debug mode, architecture
1802 specific information about the current state is printed.
1803 An optional parameter
1804 allows background polling to be enabled and disabled.
1806 You could use this from the TCL command shell, or
1807 from GDB using @command{monitor poll} command.
1810 background polling: on
1811 target state: halted
1812 target halted in ARM state due to debug-request, \
1813 current mode: Supervisor
1814 cpsr: 0x800000d3 pc: 0x11081bfc
1815 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1820 @node Interface - Dongle Configuration
1821 @chapter Interface - Dongle Configuration
1822 @cindex config file, interface
1823 @cindex interface config file
1825 JTAG Adapters/Interfaces/Dongles are normally configured
1826 through commands in an interface configuration
1827 file which is sourced by your @file{openocd.cfg} file, or
1828 through a command line @option{-f interface/....cfg} option.
1831 source [find interface/olimex-jtag-tiny.cfg]
1835 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1836 A few cases are so simple that you only need to say what driver to use:
1843 Most adapters need a bit more configuration than that.
1846 @section Interface Configuration
1848 The interface command tells OpenOCD what type of JTAG dongle you are
1849 using. Depending on the type of dongle, you may need to have one or
1850 more additional commands.
1852 @deffn {Config Command} {interface} name
1853 Use the interface driver @var{name} to connect to the
1857 @deffn Command {interface_list}
1858 List the interface drivers that have been built into
1859 the running copy of OpenOCD.
1862 @deffn Command {jtag interface}
1863 Returns the name of the interface driver being used.
1866 @section Interface Drivers
1868 Each of the interface drivers listed here must be explicitly
1869 enabled when OpenOCD is configured, in order to be made
1870 available at run time.
1872 @deffn {Interface Driver} {amt_jtagaccel}
1873 Amontec Chameleon in its JTAG Accelerator configuration,
1874 connected to a PC's EPP mode parallel port.
1875 This defines some driver-specific commands:
1877 @deffn {Config Command} {parport_port} number
1878 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1879 the number of the @file{/dev/parport} device.
1882 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1883 Displays status of RTCK option.
1884 Optionally sets that option first.
1888 @deffn {Interface Driver} {arm-jtag-ew}
1889 Olimex ARM-JTAG-EW USB adapter
1890 This has one driver-specific command:
1892 @deffn Command {armjtagew_info}
1897 @deffn {Interface Driver} {at91rm9200}
1898 Supports bitbanged JTAG from the local system,
1899 presuming that system is an Atmel AT91rm9200
1900 and a specific set of GPIOs is used.
1901 @c command: at91rm9200_device NAME
1902 @c chooses among list of bit configs ... only one option
1905 @deffn {Interface Driver} {dummy}
1906 A dummy software-only driver for debugging.
1909 @deffn {Interface Driver} {ep93xx}
1910 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1913 @deffn {Interface Driver} {ft2232}
1914 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1915 These interfaces have several commands, used to configure the driver
1916 before initializing the JTAG scan chain:
1918 @deffn {Config Command} {ft2232_device_desc} description
1919 Provides the USB device description (the @emph{iProduct string})
1920 of the FTDI FT2232 device. If not
1921 specified, the FTDI default value is used. This setting is only valid
1922 if compiled with FTD2XX support.
1925 @deffn {Config Command} {ft2232_serial} serial-number
1926 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1927 in case the vendor provides unique IDs and more than one FT2232 device
1928 is connected to the host.
1929 If not specified, serial numbers are not considered.
1930 (Note that USB serial numbers can be arbitrary Unicode strings,
1931 and are not restricted to containing only decimal digits.)
1934 @deffn {Config Command} {ft2232_layout} name
1935 Each vendor's FT2232 device can use different GPIO signals
1936 to control output-enables, reset signals, and LEDs.
1937 Currently valid layout @var{name} values include:
1939 @item @b{axm0432_jtag} Axiom AXM-0432
1940 @item @b{comstick} Hitex STR9 comstick
1941 @item @b{cortino} Hitex Cortino JTAG interface
1942 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1943 either for the local Cortex-M3 (SRST only)
1944 or in a passthrough mode (neither SRST nor TRST)
1945 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1946 @item @b{flyswatter} Tin Can Tools Flyswatter
1947 @item @b{icebear} ICEbear JTAG adapter from Section 5
1948 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1949 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1950 @item @b{m5960} American Microsystems M5960
1951 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1952 @item @b{oocdlink} OOCDLink
1953 @c oocdlink ~= jtagkey_prototype_v1
1954 @item @b{sheevaplug} Marvell Sheevaplug development kit
1955 @item @b{signalyzer} Xverve Signalyzer
1956 @item @b{stm32stick} Hitex STM32 Performance Stick
1957 @item @b{turtelizer2} egnite Software turtelizer2
1958 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1962 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1963 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1964 default values are used.
1965 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1967 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1971 @deffn {Config Command} {ft2232_latency} ms
1972 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1973 ft2232_read() fails to return the expected number of bytes. This can be caused by
1974 USB communication delays and has proved hard to reproduce and debug. Setting the
1975 FT2232 latency timer to a larger value increases delays for short USB packets but it
1976 also reduces the risk of timeouts before receiving the expected number of bytes.
1977 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1980 For example, the interface config file for a
1981 Turtelizer JTAG Adapter looks something like this:
1985 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1986 ft2232_layout turtelizer2
1987 ft2232_vid_pid 0x0403 0xbdc8
1991 @deffn {Interface Driver} {gw16012}
1992 Gateworks GW16012 JTAG programmer.
1993 This has one driver-specific command:
1995 @deffn {Config Command} {parport_port} number
1996 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1997 the number of the @file{/dev/parport} device.
2001 @deffn {Interface Driver} {jlink}
2002 Segger jlink USB adapter
2003 @c command: jlink_info
2005 @c command: jlink_hw_jtag (2|3)
2006 @c sets version 2 or 3
2009 @deffn {Interface Driver} {parport}
2010 Supports PC parallel port bit-banging cables:
2011 Wigglers, PLD download cable, and more.
2012 These interfaces have several commands, used to configure the driver
2013 before initializing the JTAG scan chain:
2015 @deffn {Config Command} {parport_cable} name
2016 The layout of the parallel port cable used to connect to the target.
2017 Currently valid cable @var{name} values include:
2020 @item @b{altium} Altium Universal JTAG cable.
2021 @item @b{arm-jtag} Same as original wiggler except SRST and
2022 TRST connections reversed and TRST is also inverted.
2023 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2024 in configuration mode. This is only used to
2025 program the Chameleon itself, not a connected target.
2026 @item @b{dlc5} The Xilinx Parallel cable III.
2027 @item @b{flashlink} The ST Parallel cable.
2028 @item @b{lattice} Lattice ispDOWNLOAD Cable
2029 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2031 Amontec's Chameleon Programmer. The new version available from
2032 the website uses the original Wiggler layout ('@var{wiggler}')
2033 @item @b{triton} The parallel port adapter found on the
2034 ``Karo Triton 1 Development Board''.
2035 This is also the layout used by the HollyGates design
2036 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2037 @item @b{wiggler} The original Wiggler layout, also supported by
2038 several clones, such as the Olimex ARM-JTAG
2039 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2040 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2044 @deffn {Config Command} {parport_port} number
2045 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
2046 the @file{/dev/parport} device
2048 When using PPDEV to access the parallel port, use the number of the parallel port:
2049 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2050 you may encounter a problem.
2053 @deffn Command {parport_toggling_time} [nanoseconds]
2054 Displays how many nanoseconds the hardware needs to toggle TCK;
2055 the parport driver uses this value to obey the
2056 @command{jtag_khz} configuration.
2057 When the optional @var{nanoseconds} parameter is given,
2058 that setting is changed before displaying the current value.
2060 The default setting should work reasonably well on commodity PC hardware.
2061 However, you may want to calibrate for your specific hardware.
2063 To measure the toggling time with a logic analyzer or a digital storage
2064 oscilloscope, follow the procedure below:
2066 > parport_toggling_time 1000
2069 This sets the maximum JTAG clock speed of the hardware, but
2070 the actual speed probably deviates from the requested 500 kHz.
2071 Now, measure the time between the two closest spaced TCK transitions.
2072 You can use @command{runtest 1000} or something similar to generate a
2073 large set of samples.
2074 Update the setting to match your measurement:
2076 > parport_toggling_time <measured nanoseconds>
2078 Now the clock speed will be a better match for @command{jtag_khz rate}
2079 commands given in OpenOCD scripts and event handlers.
2081 You can do something similar with many digital multimeters, but note
2082 that you'll probably need to run the clock continuously for several
2083 seconds before it decides what clock rate to show. Adjust the
2084 toggling time up or down until the measured clock rate is a good
2085 match for the jtag_khz rate you specified; be conservative.
2089 @deffn {Config Command} {parport_write_on_exit} (on|off)
2090 This will configure the parallel driver to write a known
2091 cable-specific value to the parallel interface on exiting OpenOCD
2094 For example, the interface configuration file for a
2095 classic ``Wiggler'' cable might look something like this:
2100 parport_cable wiggler
2104 @deffn {Interface Driver} {presto}
2105 ASIX PRESTO USB JTAG programmer.
2106 @c command: presto_serial str
2107 @c sets serial number
2110 @deffn {Interface Driver} {rlink}
2111 Raisonance RLink USB adapter
2114 @deffn {Interface Driver} {usbprog}
2115 usbprog is a freely programmable USB adapter.
2118 @deffn {Interface Driver} {vsllink}
2119 vsllink is part of Versaloon which is a versatile USB programmer.
2122 This defines quite a few driver-specific commands,
2123 which are not currently documented here.
2127 @deffn {Interface Driver} {ZY1000}
2128 This is the Zylin ZY1000 JTAG debugger.
2131 This defines some driver-specific commands,
2132 which are not currently documented here.
2135 @deffn Command power [@option{on}|@option{off}]
2136 Turn power switch to target on/off.
2137 No arguments: print status.
2144 JTAG clock setup is part of system setup.
2145 It @emph{does not belong with interface setup} since any interface
2146 only knows a few of the constraints for the JTAG clock speed.
2147 Sometimes the JTAG speed is
2148 changed during the target initialization process: (1) slow at
2149 reset, (2) program the CPU clocks, (3) run fast.
2150 Both the "slow" and "fast" clock rates are functions of the
2151 oscillators used, the chip, the board design, and sometimes
2152 power management software that may be active.
2154 The speed used during reset, and the scan chain verification which
2155 follows reset, can be adjusted using a @code{reset-start}
2156 target event handler.
2157 It can then be reconfigured to a faster speed by a
2158 @code{reset-init} target event handler after it reprograms those
2159 CPU clocks, or manually (if something else, such as a boot loader,
2160 sets up those clocks).
2161 @xref{Target Events}.
2162 When the initial low JTAG speed is a chip characteristic, perhaps
2163 because of a required oscillator speed, provide such a handler
2164 in the target config file.
2165 When that speed is a function of a board-specific characteristic
2166 such as which speed oscillator is used, it belongs in the board
2167 config file instead.
2168 In both cases it's safest to also set the initial JTAG clock rate
2169 to that same slow speed, so that OpenOCD never starts up using a
2170 clock speed that's faster than the scan chain can support.
2174 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2177 If your system supports adaptive clocking (RTCK), configuring
2178 JTAG to use that is probably the most robust approach.
2179 However, it introduces delays to synchronize clocks; so it
2180 may not be the fastest solution.
2182 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2183 instead of @command{jtag_khz}.
2185 @deffn {Command} jtag_khz max_speed_kHz
2186 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2187 JTAG interfaces usually support a limited number of
2188 speeds. The speed actually used won't be faster
2189 than the speed specified.
2191 Chip data sheets generally include a top JTAG clock rate.
2192 The actual rate is often a function of a CPU core clock,
2193 and is normally less than that peak rate.
2194 For example, most ARM cores accept at most one sixth of the CPU clock.
2196 Speed 0 (khz) selects RTCK method.
2198 If your system uses RTCK, you won't need to change the
2199 JTAG clocking after setup.
2200 Not all interfaces, boards, or targets support ``rtck''.
2201 If the interface device can not
2202 support it, an error is returned when you try to use RTCK.
2205 @defun jtag_rclk fallback_speed_kHz
2206 @cindex adaptive clocking
2208 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2209 If that fails (maybe the interface, board, or target doesn't
2210 support it), falls back to the specified frequency.
2212 # Fall back to 3mhz if RTCK is not supported
2217 @node Reset Configuration
2218 @chapter Reset Configuration
2219 @cindex Reset Configuration
2221 Every system configuration may require a different reset
2222 configuration. This can also be quite confusing.
2223 Resets also interact with @var{reset-init} event handlers,
2224 which do things like setting up clocks and DRAM, and
2225 JTAG clock rates. (@xref{JTAG Speed}.)
2226 They can also interact with JTAG routers.
2227 Please see the various board files for examples.
2230 To maintainers and integrators:
2231 Reset configuration touches several things at once.
2232 Normally the board configuration file
2233 should define it and assume that the JTAG adapter supports
2234 everything that's wired up to the board's JTAG connector.
2236 However, the target configuration file could also make note
2237 of something the silicon vendor has done inside the chip,
2238 which will be true for most (or all) boards using that chip.
2239 And when the JTAG adapter doesn't support everything, the
2240 user configuration file will need to override parts of
2241 the reset configuration provided by other files.
2244 @section Types of Reset
2246 There are many kinds of reset possible through JTAG, but
2247 they may not all work with a given board and adapter.
2248 That's part of why reset configuration can be error prone.
2252 @emph{System Reset} ... the @emph{SRST} hardware signal
2253 resets all chips connected to the JTAG adapter, such as processors,
2254 power management chips, and I/O controllers. Normally resets triggered
2255 with this signal behave exactly like pressing a RESET button.
2257 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2258 just the TAP controllers connected to the JTAG adapter.
2259 Such resets should not be visible to the rest of the system; resetting a
2260 device's the TAP controller just puts that controller into a known state.
2262 @emph{Emulation Reset} ... many devices can be reset through JTAG
2263 commands. These resets are often distinguishable from system
2264 resets, either explicitly (a "reset reason" register says so)
2265 or implicitly (not all parts of the chip get reset).
2267 @emph{Other Resets} ... system-on-chip devices often support
2268 several other types of reset.
2269 You may need to arrange that a watchdog timer stops
2270 while debugging, preventing a watchdog reset.
2271 There may be individual module resets.
2274 In the best case, OpenOCD can hold SRST, then reset
2275 the TAPs via TRST and send commands through JTAG to halt the
2276 CPU at the reset vector before the 1st instruction is executed.
2277 Then when it finally releases the SRST signal, the system is
2278 halted under debugger control before any code has executed.
2279 This is the behavior required to support the @command{reset halt}
2280 and @command{reset init} commands; after @command{reset init} a
2281 board-specific script might do things like setting up DRAM.
2282 (@xref{Reset Command}.)
2284 @anchor{SRST and TRST Issues}
2285 @section SRST and TRST Issues
2287 Because SRST and TRST are hardware signals, they can have a
2288 variety of system-specific constraints. Some of the most
2293 @item @emph{Signal not available} ... Some boards don't wire
2294 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2295 support such signals even if they are wired up.
2296 Use the @command{reset_config} @var{signals} options to say
2297 when either of those signals is not connected.
2298 When SRST is not available, your code might not be able to rely
2299 on controllers having been fully reset during code startup.
2300 Missing TRST is not a problem, since JTAG level resets can
2301 be triggered using with TMS signaling.
2303 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2304 adapter will connect SRST to TRST, instead of keeping them separate.
2305 Use the @command{reset_config} @var{combination} options to say
2306 when those signals aren't properly independent.
2308 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2309 delay circuit, reset supervisor, or on-chip features can extend
2310 the effect of a JTAG adapter's reset for some time after the adapter
2311 stops issuing the reset. For example, there may be chip or board
2312 requirements that all reset pulses last for at least a
2313 certain amount of time; and reset buttons commonly have
2314 hardware debouncing.
2315 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2316 commands to say when extra delays are needed.
2318 @item @emph{Drive type} ... Reset lines often have a pullup
2319 resistor, letting the JTAG interface treat them as open-drain
2320 signals. But that's not a requirement, so the adapter may need
2321 to use push/pull output drivers.
2322 Also, with weak pullups it may be advisable to drive
2323 signals to both levels (push/pull) to minimize rise times.
2324 Use the @command{reset_config} @var{trst_type} and
2325 @var{srst_type} parameters to say how to drive reset signals.
2327 @item @emph{Special initialization} ... Targets sometimes need
2328 special JTAG initialization sequences to handle chip-specific
2329 issues (not limited to errata).
2330 For example, certain JTAG commands might need to be issued while
2331 the system as a whole is in a reset state (SRST active)
2332 but the JTAG scan chain is usable (TRST inactive).
2333 Many systems treat combined assertion of SRST and TRST as a
2334 trigger for a harder reset than SRST alone.
2335 Such custom reset handling is discussed later in this chapter.
2338 There can also be other issues.
2339 Some devices don't fully conform to the JTAG specifications.
2340 Trivial system-specific differences are common, such as
2341 SRST and TRST using slightly different names.
2342 There are also vendors who distribute key JTAG documentation for
2343 their chips only to developers who have signed a Non-Disclosure
2346 Sometimes there are chip-specific extensions like a requirement to use
2347 the normally-optional TRST signal (precluding use of JTAG adapters which
2348 don't pass TRST through), or needing extra steps to complete a TAP reset.
2350 In short, SRST and especially TRST handling may be very finicky,
2351 needing to cope with both architecture and board specific constraints.
2353 @section Commands for Handling Resets
2355 @deffn {Command} jtag_nsrst_assert_width milliseconds
2356 Minimum amount of time (in milliseconds) OpenOCD should wait
2357 after asserting nSRST (active-low system reset) before
2358 allowing it to be deasserted.
2361 @deffn {Command} jtag_nsrst_delay milliseconds
2362 How long (in milliseconds) OpenOCD should wait after deasserting
2363 nSRST (active-low system reset) before starting new JTAG operations.
2364 When a board has a reset button connected to SRST line it will
2365 probably have hardware debouncing, implying you should use this.
2368 @deffn {Command} jtag_ntrst_assert_width milliseconds
2369 Minimum amount of time (in milliseconds) OpenOCD should wait
2370 after asserting nTRST (active-low JTAG TAP reset) before
2371 allowing it to be deasserted.
2374 @deffn {Command} jtag_ntrst_delay milliseconds
2375 How long (in milliseconds) OpenOCD should wait after deasserting
2376 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2379 @deffn {Command} reset_config mode_flag ...
2380 This command displays or modifies the reset configuration
2381 of your combination of JTAG board and target in target
2382 configuration scripts.
2384 Information earlier in this section describes the kind of problems
2385 the command is intended to address (@pxref{SRST and TRST Issues}).
2386 As a rule this command belongs only in board config files,
2387 describing issues like @emph{board doesn't connect TRST};
2388 or in user config files, addressing limitations derived
2389 from a particular combination of interface and board.
2390 (An unlikely example would be using a TRST-only adapter
2391 with a board that only wires up SRST.)
2393 The @var{mode_flag} options can be specified in any order, but only one
2394 of each type -- @var{signals}, @var{combination},
2397 and @var{srst_type} -- may be specified at a time.
2398 If you don't provide a new value for a given type, its previous
2399 value (perhaps the default) is unchanged.
2400 For example, this means that you don't need to say anything at all about
2401 TRST just to declare that if the JTAG adapter should want to drive SRST,
2402 it must explicitly be driven high (@option{srst_push_pull}).
2406 @var{signals} can specify which of the reset signals are connected.
2407 For example, If the JTAG interface provides SRST, but the board doesn't
2408 connect that signal properly, then OpenOCD can't use it.
2409 Possible values are @option{none} (the default), @option{trst_only},
2410 @option{srst_only} and @option{trst_and_srst}.
2413 If your board provides SRST and/or TRST through the JTAG connector,
2414 you must declare that so those signals can be used.
2418 The @var{combination} is an optional value specifying broken reset
2419 signal implementations.
2420 The default behaviour if no option given is @option{separate},
2421 indicating everything behaves normally.
2422 @option{srst_pulls_trst} states that the
2423 test logic is reset together with the reset of the system (e.g. Philips
2424 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2425 the system is reset together with the test logic (only hypothetical, I
2426 haven't seen hardware with such a bug, and can be worked around).
2427 @option{combined} implies both @option{srst_pulls_trst} and
2428 @option{trst_pulls_srst}.
2431 The @var{gates} tokens control flags that describe some cases where
2432 JTAG may be unvailable during reset.
2433 @option{srst_gates_jtag} (default)
2434 indicates that asserting SRST gates the
2435 JTAG clock. This means that no communication can happen on JTAG
2436 while SRST is asserted.
2437 Its converse is @option{srst_nogate}, indicating that JTAG commands
2438 can safely be issued while SRST is active.
2441 The optional @var{trst_type} and @var{srst_type} parameters allow the
2442 driver mode of each reset line to be specified. These values only affect
2443 JTAG interfaces with support for different driver modes, like the Amontec
2444 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2445 relevant signal (TRST or SRST) is not connected.
2449 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2450 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2451 Most boards connect this signal to a pulldown, so the JTAG TAPs
2452 never leave reset unless they are hooked up to a JTAG adapter.
2455 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2456 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2457 Most boards connect this signal to a pullup, and allow the
2458 signal to be pulled low by various events including system
2459 powerup and pressing a reset button.
2463 @section Custom Reset Handling
2466 OpenOCD has several ways to help support the various reset
2467 mechanisms provided by chip and board vendors.
2468 The commands shown in the previous section give standard parameters.
2469 There are also @emph{event handlers} associated with TAPs or Targets.
2470 Those handlers are Tcl procedures you can provide, which are invoked
2471 at particular points in the reset sequence.
2473 @emph{When SRST is not an option} you must set
2474 up a @code{reset-assert} event handler for your target.
2475 For example, some JTAG adapters don't include the SRST signal;
2476 and some boards have multiple targets, and you won't always
2477 want to reset everything at once.
2479 After configuring those mechanisms, you might still
2480 find your board doesn't start up or reset correctly.
2481 For example, maybe it needs a slightly different sequence
2482 of SRST and/or TRST manipulations, because of quirks that
2483 the @command{reset_config} mechanism doesn't address;
2484 or asserting both might trigger a stronger reset, which
2485 needs special attention.
2487 Experiment with lower level operations, such as @command{jtag_reset}
2488 and the @command{jtag arp_*} operations shown here,
2489 to find a sequence of operations that works.
2490 @xref{JTAG Commands}.
2491 When you find a working sequence, it can be used to override
2492 @command{jtag_init}, which fires during OpenOCD startup
2493 (@pxref{Configuration Stage});
2494 or @command{init_reset}, which fires during reset processing.
2496 You might also want to provide some project-specific reset
2497 schemes. For example, on a multi-target board the standard
2498 @command{reset} command would reset all targets, but you
2499 may need the ability to reset only one target at time and
2500 thus want to avoid using the board-wide SRST signal.
2502 @deffn {Overridable Procedure} init_reset mode
2503 This is invoked near the beginning of the @command{reset} command,
2504 usually to provide as much of a cold (power-up) reset as practical.
2505 By default it is also invoked from @command{jtag_init} if
2506 the scan chain does not respond to pure JTAG operations.
2507 The @var{mode} parameter is the parameter given to the
2508 low level reset command (@option{halt},
2509 @option{init}, or @option{run}), @option{setup},
2510 or potentially some other value.
2512 The default implementation just invokes @command{jtag arp_init-reset}.
2513 Replacements will normally build on low level JTAG
2514 operations such as @command{jtag_reset}.
2515 Operations here must not address individual TAPs
2516 (or their associated targets)
2517 until the JTAG scan chain has first been verified to work.
2519 Implementations must have verified the JTAG scan chain before
2521 This is done by calling @command{jtag arp_init}
2522 (or @command{jtag arp_init-reset}).
2525 @deffn Command {jtag arp_init}
2526 This validates the scan chain using just the four
2527 standard JTAG signals (TMS, TCK, TDI, TDO).
2528 It starts by issuing a JTAG-only reset.
2529 Then it performs checks to verify that the scan chain configuration
2530 matches the TAPs it can observe.
2531 Those checks include checking IDCODE values for each active TAP,
2532 and verifying the length of their instruction registers using
2533 TAP @code{-ircapture} and @code{-irmask} values.
2534 If these tests all pass, TAP @code{setup} events are
2535 issued to all TAPs with handlers for that event.
2538 @deffn Command {jtag arp_init-reset}
2539 This uses TRST and SRST to try resetting
2540 everything on the JTAG scan chain
2541 (and anything else connected to SRST).
2542 It then invokes the logic of @command{jtag arp_init}.
2546 @node TAP Declaration
2547 @chapter TAP Declaration
2548 @cindex TAP declaration
2549 @cindex TAP configuration
2551 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2552 TAPs serve many roles, including:
2555 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2556 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2557 Others do it indirectly, making a CPU do it.
2558 @item @b{Program Download} Using the same CPU support GDB uses,
2559 you can initialize a DRAM controller, download code to DRAM, and then
2560 start running that code.
2561 @item @b{Boundary Scan} Most chips support boundary scan, which
2562 helps test for board assembly problems like solder bridges
2563 and missing connections
2566 OpenOCD must know about the active TAPs on your board(s).
2567 Setting up the TAPs is the core task of your configuration files.
2568 Once those TAPs are set up, you can pass their names to code
2569 which sets up CPUs and exports them as GDB targets,
2570 probes flash memory, performs low-level JTAG operations, and more.
2572 @section Scan Chains
2575 TAPs are part of a hardware @dfn{scan chain},
2576 which is daisy chain of TAPs.
2577 They also need to be added to
2578 OpenOCD's software mirror of that hardware list,
2579 giving each member a name and associating other data with it.
2580 Simple scan chains, with a single TAP, are common in
2581 systems with a single microcontroller or microprocessor.
2582 More complex chips may have several TAPs internally.
2583 Very complex scan chains might have a dozen or more TAPs:
2584 several in one chip, more in the next, and connecting
2585 to other boards with their own chips and TAPs.
2587 You can display the list with the @command{scan_chain} command.
2588 (Don't confuse this with the list displayed by the @command{targets}
2589 command, presented in the next chapter.
2590 That only displays TAPs for CPUs which are configured as
2592 Here's what the scan chain might look like for a chip more than one TAP:
2595 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2596 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2597 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2598 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2599 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2602 Unfortunately those TAPs can't always be autoconfigured,
2603 because not all devices provide good support for that.
2604 JTAG doesn't require supporting IDCODE instructions, and
2605 chips with JTAG routers may not link TAPs into the chain
2606 until they are told to do so.
2608 The configuration mechanism currently supported by OpenOCD
2609 requires explicit configuration of all TAP devices using
2610 @command{jtag newtap} commands, as detailed later in this chapter.
2611 A command like this would declare one tap and name it @code{chip1.cpu}:
2614 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
2617 Each target configuration file lists the TAPs provided
2619 Board configuration files combine all the targets on a board,
2621 Note that @emph{the order in which TAPs are declared is very important.}
2622 It must match the order in the JTAG scan chain, both inside
2623 a single chip and between them.
2624 @xref{FAQ TAP Order}.
2626 For example, the ST Microsystems STR912 chip has
2627 three separate TAPs@footnote{See the ST
2628 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2629 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2630 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2631 To configure those taps, @file{target/str912.cfg}
2632 includes commands something like this:
2635 jtag newtap str912 flash ... params ...
2636 jtag newtap str912 cpu ... params ...
2637 jtag newtap str912 bs ... params ...
2640 Actual config files use a variable instead of literals like
2641 @option{str912}, to support more than one chip of each type.
2642 @xref{Config File Guidelines}.
2644 @deffn Command {jtag names}
2645 Returns the names of all current TAPs in the scan chain.
2646 Use @command{jtag cget} or @command{jtag tapisenabled}
2647 to examine attributes and state of each TAP.
2649 foreach t [jtag names] @{
2650 puts [format "TAP: %s\n" $t]
2655 @deffn Command {scan_chain}
2656 Displays the TAPs in the scan chain configuration,
2658 The set of TAPs listed by this command is fixed by
2659 exiting the OpenOCD configuration stage,
2660 but systems with a JTAG router can
2661 enable or disable TAPs dynamically.
2662 In addition to the enable/disable status, the contents of
2663 each TAP's instruction register can also change.
2666 @c FIXME! "jtag cget" should be able to return all TAP
2667 @c attributes, like "$target_name cget" does for targets.
2669 @c Probably want "jtag eventlist", and a "tap-reset" event
2670 @c (on entry to RESET state).
2675 When TAP objects are declared with @command{jtag newtap},
2676 a @dfn{dotted.name} is created for the TAP, combining the
2677 name of a module (usually a chip) and a label for the TAP.
2678 For example: @code{xilinx.tap}, @code{str912.flash},
2679 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2680 Many other commands use that dotted.name to manipulate or
2681 refer to the TAP. For example, CPU configuration uses the
2682 name, as does declaration of NAND or NOR flash banks.
2684 The components of a dotted name should follow ``C'' symbol
2685 name rules: start with an alphabetic character, then numbers
2686 and underscores are OK; while others (including dots!) are not.
2689 In older code, JTAG TAPs were numbered from 0..N.
2690 This feature is still present.
2691 However its use is highly discouraged, and
2692 should not be relied on; it will be removed by mid-2010.
2693 Update all of your scripts to use TAP names rather than numbers,
2694 by paying attention to the runtime warnings they trigger.
2695 Using TAP numbers in target configuration scripts prevents
2696 reusing those scripts on boards with multiple targets.
2699 @section TAP Declaration Commands
2701 @c shouldn't this be(come) a {Config Command}?
2702 @anchor{jtag newtap}
2703 @deffn Command {jtag newtap} chipname tapname configparams...
2704 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2705 and configured according to the various @var{configparams}.
2707 The @var{chipname} is a symbolic name for the chip.
2708 Conventionally target config files use @code{$_CHIPNAME},
2709 defaulting to the model name given by the chip vendor but
2712 @cindex TAP naming convention
2713 The @var{tapname} reflects the role of that TAP,
2714 and should follow this convention:
2717 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2718 @item @code{cpu} -- The main CPU of the chip, alternatively
2719 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2720 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2721 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2722 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2723 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2724 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2725 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2727 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2728 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2729 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2730 a JTAG TAP; that TAP should be named @code{sdma}.
2733 Every TAP requires at least the following @var{configparams}:
2736 @item @code{-irlen} @var{NUMBER}
2737 @*The length in bits of the
2738 instruction register, such as 4 or 5 bits.
2741 A TAP may also provide optional @var{configparams}:
2744 @item @code{-disable} (or @code{-enable})
2745 @*Use the @code{-disable} parameter to flag a TAP which is not
2746 linked in to the scan chain after a reset using either TRST
2747 or the JTAG state machine's @sc{reset} state.
2748 You may use @code{-enable} to highlight the default state
2749 (the TAP is linked in).
2750 @xref{Enabling and Disabling TAPs}.
2751 @item @code{-expected-id} @var{number}
2752 @*A non-zero @var{number} represents a 32-bit IDCODE
2753 which you expect to find when the scan chain is examined.
2754 These codes are not required by all JTAG devices.
2755 @emph{Repeat the option} as many times as required if more than one
2756 ID code could appear (for example, multiple versions).
2757 Specify @var{number} as zero to suppress warnings about IDCODE
2758 values that were found but not included in the list.
2760 Provide this value if at all possible, since it lets OpenOCD
2761 tell when the scan chain it sees isn't right. These values
2762 are provided in vendors' chip documentation, usually a technical
2763 reference manual. Sometimes you may need to probe the JTAG
2764 hardware to find these values.
2766 @item @code{-ircapture} @var{NUMBER}
2767 @*The bit pattern loaded by the TAP into the JTAG shift register
2768 on entry to the @sc{ircapture} state, such as 0x01.
2769 JTAG requires the two LSBs of this value to be 01.
2770 By default, @code{-ircapture} and @code{-irmask} are set
2771 up to verify that two-bit value. You may provide
2772 additional bits, if you know them, or indicate that
2773 a TAP doesn't conform to the JTAG specification.
2774 @item @code{-irmask} @var{NUMBER}
2775 @*A mask used with @code{-ircapture}
2776 to verify that instruction scans work correctly.
2777 Such scans are not used by OpenOCD except to verify that
2778 there seems to be no problems with JTAG scan chain operations.
2782 @section Other TAP commands
2784 @deffn Command {jtag cget} dotted.name @option{-event} name
2785 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2786 At this writing this TAP attribute
2787 mechanism is used only for event handling.
2788 (It is not a direct analogue of the @code{cget}/@code{configure}
2789 mechanism for debugger targets.)
2790 See the next section for information about the available events.
2792 The @code{configure} subcommand assigns an event handler,
2793 a TCL string which is evaluated when the event is triggered.
2794 The @code{cget} subcommand returns that handler.
2802 OpenOCD includes two event mechanisms.
2803 The one presented here applies to all JTAG TAPs.
2804 The other applies to debugger targets,
2805 which are associated with certain TAPs.
2807 The TAP events currently defined are:
2810 @item @b{post-reset}
2811 @* The TAP has just completed a JTAG reset.
2812 The tap may still be in the JTAG @sc{reset} state.
2813 Handlers for these events might perform initialization sequences
2814 such as issuing TCK cycles, TMS sequences to ensure
2815 exit from the ARM SWD mode, and more.
2817 Because the scan chain has not yet been verified, handlers for these events
2818 @emph{should not issue commands which scan the JTAG IR or DR registers}
2819 of any particular target.
2820 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2822 @* The scan chain has been reset and verified.
2823 This handler may enable TAPs as needed.
2824 @item @b{tap-disable}
2825 @* The TAP needs to be disabled. This handler should
2826 implement @command{jtag tapdisable}
2827 by issuing the relevant JTAG commands.
2828 @item @b{tap-enable}
2829 @* The TAP needs to be enabled. This handler should
2830 implement @command{jtag tapenable}
2831 by issuing the relevant JTAG commands.
2834 If you need some action after each JTAG reset, which isn't actually
2835 specific to any TAP (since you can't yet trust the scan chain's
2836 contents to be accurate), you might:
2839 jtag configure CHIP.jrc -event post-reset @{
2840 echo "JTAG Reset done"
2841 ... non-scan jtag operations to be done after reset
2846 @anchor{Enabling and Disabling TAPs}
2847 @section Enabling and Disabling TAPs
2848 @cindex JTAG Route Controller
2851 In some systems, a @dfn{JTAG Route Controller} (JRC)
2852 is used to enable and/or disable specific JTAG TAPs.
2853 Many ARM based chips from Texas Instruments include
2854 an ``ICEpick'' module, which is a JRC.
2855 Such chips include DaVinci and OMAP3 processors.
2857 A given TAP may not be visible until the JRC has been
2858 told to link it into the scan chain; and if the JRC
2859 has been told to unlink that TAP, it will no longer
2861 Such routers address problems that JTAG ``bypass mode''
2865 @item The scan chain can only go as fast as its slowest TAP.
2866 @item Having many TAPs slows instruction scans, since all
2867 TAPs receive new instructions.
2868 @item TAPs in the scan chain must be powered up, which wastes
2869 power and prevents debugging some power management mechanisms.
2872 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2873 as implied by the existence of JTAG routers.
2874 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2875 does include a kind of JTAG router functionality.
2877 @c (a) currently the event handlers don't seem to be able to
2878 @c fail in a way that could lead to no-change-of-state.
2880 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2881 shown below, and is implemented using TAP event handlers.
2882 So for example, when defining a TAP for a CPU connected to
2883 a JTAG router, your @file{target.cfg} file
2884 should define TAP event handlers using
2885 code that looks something like this:
2888 jtag configure CHIP.cpu -event tap-enable @{
2889 ... jtag operations using CHIP.jrc
2891 jtag configure CHIP.cpu -event tap-disable @{
2892 ... jtag operations using CHIP.jrc
2896 Then you might want that CPU's TAP enabled almost all the time:
2899 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2902 Note how that particular setup event handler declaration
2903 uses quotes to evaluate @code{$CHIP} when the event is configured.
2904 Using brackets @{ @} would cause it to be evaluated later,
2905 at runtime, when it might have a different value.
2907 @deffn Command {jtag tapdisable} dotted.name
2908 If necessary, disables the tap
2909 by sending it a @option{tap-disable} event.
2910 Returns the string "1" if the tap
2911 specified by @var{dotted.name} is enabled,
2912 and "0" if it is disabled.
2915 @deffn Command {jtag tapenable} dotted.name
2916 If necessary, enables the tap
2917 by sending it a @option{tap-enable} event.
2918 Returns the string "1" if the tap
2919 specified by @var{dotted.name} is enabled,
2920 and "0" if it is disabled.
2923 @deffn Command {jtag tapisenabled} dotted.name
2924 Returns the string "1" if the tap
2925 specified by @var{dotted.name} is enabled,
2926 and "0" if it is disabled.
2929 Humans will find the @command{scan_chain} command more helpful
2930 for querying the state of the JTAG taps.
2934 @anchor{Autoprobing}
2935 @section Autoprobing
2937 @cindex JTAG autoprobe
2939 TAP configuration is the first thing that needs to be done
2940 after interface and reset configuration. Sometimes it's
2941 hard finding out what TAPs exist, or how they are identified.
2942 Vendor documentation is not always easy to find and use.
2944 To help you get past such problems, OpenOCD has a limited
2945 @emph{autoprobing} ability to look at the scan chain, doing
2946 a @dfn{blind interrogation} and then reporting the TAPs it finds.
2947 To use this mechanism, start the OpenOCD server with only data
2948 that configures your JTAG interface, and arranges to come up
2949 with a slow clock (many devices don't support fast JTAG clocks
2950 right when they come out of reset).
2952 For example, your @file{openocd.cfg} file might have:
2955 source [find interface/olimex-arm-usb-tiny-h.cfg]
2956 reset_config trst_and_srst
2960 When you start the server without any TAPs configured, it will
2961 attempt to autoconfigure the TAPs. There are two parts to this:
2964 @item @emph{TAP discovery} ...
2965 After a JTAG reset (sometimes a system reset may be needed too),
2966 each TAP's data registers will hold the contents of either the
2967 IDCODE or BYPASS register.
2968 If JTAG communication is working, OpenOCD will see each TAP,
2969 and report what @option{-expected-id} to use with it.
2970 @item @emph{IR Length discovery} ...
2971 Unfortunately JTAG does not provide a reliable way to find out
2972 the value of the @option{-irlen} parameter to use with a TAP
2974 If OpenOCD can discover the length of a TAP's instruction
2975 register, it will report it.
2976 Otherwise you may need to consult vendor documentation, such
2977 as chip data sheets or BSDL files.
2980 In many cases your board will have a simple scan chain with just
2981 a single device. Here's what OpenOCD reported with one board
2982 that's a bit more complex:
2986 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
2987 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
2988 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
2989 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
2990 AUTO auto0.tap - use "... -irlen 4"
2991 AUTO auto1.tap - use "... -irlen 4"
2992 AUTO auto2.tap - use "... -irlen 6"
2993 no gdb ports allocated as no target has been specified
2996 Given that information, you should be able to either find some existing
2997 config files to use, or create your own. If you create your own, you
2998 would configure from the bottom up: first a @file{target.cfg} file
2999 with these TAPs, any targets associated with them, and any on-chip
3000 resources; then a @file{board.cfg} with off-chip resources, clocking,
3003 @node CPU Configuration
3004 @chapter CPU Configuration
3007 This chapter discusses how to set up GDB debug targets for CPUs.
3008 You can also access these targets without GDB
3009 (@pxref{Architecture and Core Commands},
3010 and @ref{Target State handling}) and
3011 through various kinds of NAND and NOR flash commands.
3012 If you have multiple CPUs you can have multiple such targets.
3014 We'll start by looking at how to examine the targets you have,
3015 then look at how to add one more target and how to configure it.
3017 @section Target List
3018 @cindex target, current
3019 @cindex target, list
3021 All targets that have been set up are part of a list,
3022 where each member has a name.
3023 That name should normally be the same as the TAP name.
3024 You can display the list with the @command{targets}
3026 This display often has only one CPU; here's what it might
3027 look like with more than one:
3029 TargetName Type Endian TapName State
3030 -- ------------------ ---------- ------ ------------------ ------------
3031 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3032 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3035 One member of that list is the @dfn{current target}, which
3036 is implicitly referenced by many commands.
3037 It's the one marked with a @code{*} near the target name.
3038 In particular, memory addresses often refer to the address
3039 space seen by that current target.
3040 Commands like @command{mdw} (memory display words)
3041 and @command{flash erase_address} (erase NOR flash blocks)
3042 are examples; and there are many more.
3044 Several commands let you examine the list of targets:
3046 @deffn Command {target count}
3047 @emph{Note: target numbers are deprecated; don't use them.
3048 They will be removed shortly after August 2010, including this command.
3049 Iterate target using @command{target names}, not by counting.}
3051 Returns the number of targets, @math{N}.
3052 The highest numbered target is @math{N - 1}.
3054 set c [target count]
3055 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3056 # Assuming you have created this function
3057 print_target_details $x
3062 @deffn Command {target current}
3063 Returns the name of the current target.
3066 @deffn Command {target names}
3067 Lists the names of all current targets in the list.
3069 foreach t [target names] @{
3070 puts [format "Target: %s\n" $t]
3075 @deffn Command {target number} number
3076 @emph{Note: target numbers are deprecated; don't use them.
3077 They will be removed shortly after August 2010, including this command.}
3079 The list of targets is numbered starting at zero.
3080 This command returns the name of the target at index @var{number}.
3082 set thename [target number $x]
3083 puts [format "Target %d is: %s\n" $x $thename]
3087 @c yep, "target list" would have been better.
3088 @c plus maybe "target setdefault".
3090 @deffn Command targets [name]
3091 @emph{Note: the name of this command is plural. Other target
3092 command names are singular.}
3094 With no parameter, this command displays a table of all known
3095 targets in a user friendly form.
3097 With a parameter, this command sets the current target to
3098 the given target with the given @var{name}; this is
3099 only relevant on boards which have more than one target.
3102 @section Target CPU Types and Variants
3107 Each target has a @dfn{CPU type}, as shown in the output of
3108 the @command{targets} command. You need to specify that type
3109 when calling @command{target create}.
3110 The CPU type indicates more than just the instruction set.
3111 It also indicates how that instruction set is implemented,
3112 what kind of debug support it integrates,
3113 whether it has an MMU (and if so, what kind),
3114 what core-specific commands may be available
3115 (@pxref{Architecture and Core Commands}),
3118 For some CPU types, OpenOCD also defines @dfn{variants} which
3119 indicate differences that affect their handling.
3120 For example, a particular implementation bug might need to be
3121 worked around in some chip versions.
3123 It's easy to see what target types are supported,
3124 since there's a command to list them.
3125 However, there is currently no way to list what target variants
3126 are supported (other than by reading the OpenOCD source code).
3128 @anchor{target types}
3129 @deffn Command {target types}
3130 Lists all supported target types.
3131 At this writing, the supported CPU types and variants are:
3134 @item @code{arm11} -- this is a generation of ARMv6 cores
3135 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3136 @item @code{arm7tdmi} -- this is an ARMv4 core
3137 @item @code{arm920t} -- this is an ARMv5 core with an MMU
3138 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3139 @item @code{arm966e} -- this is an ARMv5 core
3140 @item @code{arm9tdmi} -- this is an ARMv4 core
3141 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3142 (Support for this is preliminary and incomplete.)
3143 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3144 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3145 compact Thumb2 instruction set. It supports one variant:
3147 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
3148 This will cause OpenOCD to use a software reset rather than asserting
3149 SRST, to avoid a issue with clearing the debug registers.
3150 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
3151 be detected and the normal reset behaviour used.
3153 @item @code{dragonite} -- resembles arm966e
3154 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3155 @item @code{feroceon} -- resembles arm926
3156 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3158 @item @code{ejtag_srst} ... Use this when debugging targets that do not
3159 provide a functional SRST line on the EJTAG connector. This causes
3160 OpenOCD to instead use an EJTAG software reset command to reset the
3162 You still need to enable @option{srst} on the @command{reset_config}
3163 command to enable OpenOCD hardware reset functionality.
3165 @item @code{xscale} -- this is actually an architecture,
3166 not a CPU type. It is based on the ARMv5 architecture.
3167 There are several variants defined:
3169 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3170 @code{pxa27x} ... instruction register length is 7 bits
3171 @item @code{pxa250}, @code{pxa255},
3172 @code{pxa26x} ... instruction register length is 5 bits
3173 @item @code{pxa3xx} ... instruction register length is 11 bits
3178 To avoid being confused by the variety of ARM based cores, remember
3179 this key point: @emph{ARM is a technology licencing company}.
3180 (See: @url{http://www.arm.com}.)
3181 The CPU name used by OpenOCD will reflect the CPU design that was
3182 licenced, not a vendor brand which incorporates that design.
3183 Name prefixes like arm7, arm9, arm11, and cortex
3184 reflect design generations;
3185 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3186 reflect an architecture version implemented by a CPU design.
3188 @anchor{Target Configuration}
3189 @section Target Configuration
3191 Before creating a ``target'', you must have added its TAP to the scan chain.
3192 When you've added that TAP, you will have a @code{dotted.name}
3193 which is used to set up the CPU support.
3194 The chip-specific configuration file will normally configure its CPU(s)
3195 right after it adds all of the chip's TAPs to the scan chain.
3197 Although you can set up a target in one step, it's often clearer if you
3198 use shorter commands and do it in two steps: create it, then configure
3200 All operations on the target after it's created will use a new
3201 command, created as part of target creation.
3203 The two main things to configure after target creation are
3204 a work area, which usually has target-specific defaults even
3205 if the board setup code overrides them later;
3206 and event handlers (@pxref{Target Events}), which tend
3207 to be much more board-specific.
3208 The key steps you use might look something like this
3211 target create MyTarget cortex_m3 -chain-position mychip.cpu
3212 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3213 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3214 $MyTarget configure -event reset-init @{ myboard_reinit @}
3217 You should specify a working area if you can; typically it uses some
3219 Such a working area can speed up many things, including bulk
3220 writes to target memory;
3221 flash operations like checking to see if memory needs to be erased;
3222 GDB memory checksumming;
3226 On more complex chips, the work area can become
3227 inaccessible when application code
3228 (such as an operating system)
3229 enables or disables the MMU.
3230 For example, the particular MMU context used to acess the virtual
3231 address will probably matter ... and that context might not have
3232 easy access to other addresses needed.
3233 At this writing, OpenOCD doesn't have much MMU intelligence.
3236 It's often very useful to define a @code{reset-init} event handler.
3237 For systems that are normally used with a boot loader,
3238 common tasks include updating clocks and initializing memory
3240 That may be needed to let you write the boot loader into flash,
3241 in order to ``de-brick'' your board; or to load programs into
3242 external DDR memory without having run the boot loader.
3244 @deffn Command {target create} target_name type configparams...
3245 This command creates a GDB debug target that refers to a specific JTAG tap.
3246 It enters that target into a list, and creates a new
3247 command (@command{@var{target_name}}) which is used for various
3248 purposes including additional configuration.
3251 @item @var{target_name} ... is the name of the debug target.
3252 By convention this should be the same as the @emph{dotted.name}
3253 of the TAP associated with this target, which must be specified here
3254 using the @code{-chain-position @var{dotted.name}} configparam.
3256 This name is also used to create the target object command,
3257 referred to here as @command{$target_name},
3258 and in other places the target needs to be identified.
3259 @item @var{type} ... specifies the target type. @xref{target types}.
3260 @item @var{configparams} ... all parameters accepted by
3261 @command{$target_name configure} are permitted.
3262 If the target is big-endian, set it here with @code{-endian big}.
3263 If the variant matters, set it here with @code{-variant}.
3265 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3269 @deffn Command {$target_name configure} configparams...
3270 The options accepted by this command may also be
3271 specified as parameters to @command{target create}.
3272 Their values can later be queried one at a time by
3273 using the @command{$target_name cget} command.
3275 @emph{Warning:} changing some of these after setup is dangerous.
3276 For example, moving a target from one TAP to another;
3277 and changing its endianness or variant.
3281 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3282 used to access this target.
3284 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3285 whether the CPU uses big or little endian conventions
3287 @item @code{-event} @var{event_name} @var{event_body} --
3288 @xref{Target Events}.
3289 Note that this updates a list of named event handlers.
3290 Calling this twice with two different event names assigns
3291 two different handlers, but calling it twice with the
3292 same event name assigns only one handler.
3294 @item @code{-variant} @var{name} -- specifies a variant of the target,
3295 which OpenOCD needs to know about.
3297 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3298 whether the work area gets backed up; by default,
3299 @emph{it is not backed up.}
3300 When possible, use a working_area that doesn't need to be backed up,
3301 since performing a backup slows down operations.
3302 For example, the beginning of an SRAM block is likely to
3303 be used by most build systems, but the end is often unused.
3305 @item @code{-work-area-size} @var{size} -- specify work are size,
3306 in bytes. The same size applies regardless of whether its physical
3307 or virtual address is being used.
3309 @item @code{-work-area-phys} @var{address} -- set the work area
3310 base @var{address} to be used when no MMU is active.
3312 @item @code{-work-area-virt} @var{address} -- set the work area
3313 base @var{address} to be used when an MMU is active.
3314 @emph{Do not specify a value for this except on targets with an MMU.}
3315 The value should normally correspond to a static mapping for the
3316 @code{-work-area-phys} address, set up by the current operating system.
3321 @section Other $target_name Commands
3322 @cindex object command
3324 The Tcl/Tk language has the concept of object commands,
3325 and OpenOCD adopts that same model for targets.
3327 A good Tk example is a on screen button.
3328 Once a button is created a button
3329 has a name (a path in Tk terms) and that name is useable as a first
3330 class command. For example in Tk, one can create a button and later
3331 configure it like this:
3335 button .foobar -background red -command @{ foo @}
3337 .foobar configure -foreground blue
3339 set x [.foobar cget -background]
3341 puts [format "The button is %s" $x]
3344 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3345 button, and its object commands are invoked the same way.
3348 str912.cpu mww 0x1234 0x42
3349 omap3530.cpu mww 0x5555 123
3352 The commands supported by OpenOCD target objects are:
3354 @deffn Command {$target_name arp_examine}
3355 @deffnx Command {$target_name arp_halt}
3356 @deffnx Command {$target_name arp_poll}
3357 @deffnx Command {$target_name arp_reset}
3358 @deffnx Command {$target_name arp_waitstate}
3359 Internal OpenOCD scripts (most notably @file{startup.tcl})
3360 use these to deal with specific reset cases.
3361 They are not otherwise documented here.
3364 @deffn Command {$target_name array2mem} arrayname width address count
3365 @deffnx Command {$target_name mem2array} arrayname width address count
3366 These provide an efficient script-oriented interface to memory.
3367 The @code{array2mem} primitive writes bytes, halfwords, or words;
3368 while @code{mem2array} reads them.
3369 In both cases, the TCL side uses an array, and
3370 the target side uses raw memory.
3372 The efficiency comes from enabling the use of
3373 bulk JTAG data transfer operations.
3374 The script orientation comes from working with data
3375 values that are packaged for use by TCL scripts;
3376 @command{mdw} type primitives only print data they retrieve,
3377 and neither store nor return those values.
3380 @item @var{arrayname} ... is the name of an array variable
3381 @item @var{width} ... is 8/16/32 - indicating the memory access size
3382 @item @var{address} ... is the target memory address
3383 @item @var{count} ... is the number of elements to process
3387 @deffn Command {$target_name cget} queryparm
3388 Each configuration parameter accepted by
3389 @command{$target_name configure}
3390 can be individually queried, to return its current value.
3391 The @var{queryparm} is a parameter name
3392 accepted by that command, such as @code{-work-area-phys}.
3393 There are a few special cases:
3396 @item @code{-event} @var{event_name} -- returns the handler for the
3397 event named @var{event_name}.
3398 This is a special case because setting a handler requires
3400 @item @code{-type} -- returns the target type.
3401 This is a special case because this is set using
3402 @command{target create} and can't be changed
3403 using @command{$target_name configure}.
3406 For example, if you wanted to summarize information about
3407 all the targets you might use something like this:
3410 foreach name [target names] @{
3411 set y [$name cget -endian]
3412 set z [$name cget -type]
3413 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3419 @anchor{target curstate}
3420 @deffn Command {$target_name curstate}
3421 Displays the current target state:
3422 @code{debug-running},
3425 @code{running}, or @code{unknown}.
3426 (Also, @pxref{Event Polling}.)
3429 @deffn Command {$target_name eventlist}
3430 Displays a table listing all event handlers
3431 currently associated with this target.
3432 @xref{Target Events}.
3435 @deffn Command {$target_name invoke-event} event_name
3436 Invokes the handler for the event named @var{event_name}.
3437 (This is primarily intended for use by OpenOCD framework
3438 code, for example by the reset code in @file{startup.tcl}.)
3441 @deffn Command {$target_name mdw} addr [count]
3442 @deffnx Command {$target_name mdh} addr [count]
3443 @deffnx Command {$target_name mdb} addr [count]
3444 Display contents of address @var{addr}, as
3445 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3446 or 8-bit bytes (@command{mdb}).
3447 If @var{count} is specified, displays that many units.
3448 (If you want to manipulate the data instead of displaying it,
3449 see the @code{mem2array} primitives.)
3452 @deffn Command {$target_name mww} addr word
3453 @deffnx Command {$target_name mwh} addr halfword
3454 @deffnx Command {$target_name mwb} addr byte
3455 Writes the specified @var{word} (32 bits),
3456 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3457 at the specified address @var{addr}.
3460 @anchor{Target Events}
3461 @section Target Events
3462 @cindex target events
3464 At various times, certain things can happen, or you want them to happen.
3467 @item What should happen when GDB connects? Should your target reset?
3468 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3469 @item Is using SRST appropriate (and possible) on your system?
3470 Or instead of that, do you need to issue JTAG commands to trigger reset?
3471 SRST usually resets everything on the scan chain, which can be inappropriate.
3472 @item During reset, do you need to write to certain memory locations
3473 to set up system clocks or
3474 to reconfigure the SDRAM?
3475 How about configuring the watchdog timer, or other peripherals,
3476 to stop running while you hold the core stopped for debugging?
3479 All of the above items can be addressed by target event handlers.
3480 These are set up by @command{$target_name configure -event} or
3481 @command{target create ... -event}.
3483 The programmer's model matches the @code{-command} option used in Tcl/Tk
3484 buttons and events. The two examples below act the same, but one creates
3485 and invokes a small procedure while the other inlines it.
3488 proc my_attach_proc @{ @} @{
3492 mychip.cpu configure -event gdb-attach my_attach_proc
3493 mychip.cpu configure -event gdb-attach @{
3499 The following target events are defined:
3502 @item @b{debug-halted}
3503 @* The target has halted for debug reasons (i.e.: breakpoint)
3504 @item @b{debug-resumed}
3505 @* The target has resumed (i.e.: gdb said run)
3506 @item @b{early-halted}
3507 @* Occurs early in the halt process
3509 @item @b{examine-end}
3510 @* Currently not used (goal: when JTAG examine completes)
3511 @item @b{examine-start}
3512 @* Currently not used (goal: when JTAG examine starts)
3514 @item @b{gdb-attach}
3515 @* When GDB connects
3516 @item @b{gdb-detach}
3517 @* When GDB disconnects
3519 @* When the target has halted and GDB is not doing anything (see early halt)
3520 @item @b{gdb-flash-erase-start}
3521 @* Before the GDB flash process tries to erase the flash
3522 @item @b{gdb-flash-erase-end}
3523 @* After the GDB flash process has finished erasing the flash
3524 @item @b{gdb-flash-write-start}
3525 @* Before GDB writes to the flash
3526 @item @b{gdb-flash-write-end}
3527 @* After GDB writes to the flash
3529 @* Before the target steps, gdb is trying to start/resume the target
3531 @* The target has halted
3533 @item @b{old-gdb_program_config}
3534 @* DO NOT USE THIS: Used internally
3535 @item @b{old-pre_resume}
3536 @* DO NOT USE THIS: Used internally
3538 @item @b{reset-assert-pre}
3539 @* Issued as part of @command{reset} processing
3540 after @command{reset_init} was triggered
3541 but before either SRST alone is re-asserted on the scan chain,
3542 or @code{reset-assert} is triggered.
3543 @item @b{reset-assert}
3544 @* Issued as part of @command{reset} processing
3545 after @command{reset-assert-pre} was triggered.
3546 When such a handler is present, cores which support this event will use
3547 it instead of asserting SRST.
3548 This support is essential for debugging with JTAG interfaces which
3549 don't include an SRST line (JTAG doesn't require SRST), and for
3550 selective reset on scan chains that have multiple targets.
3551 @item @b{reset-assert-post}
3552 @* Issued as part of @command{reset} processing
3553 after @code{reset-assert} has been triggered.
3554 or the target asserted SRST on the entire scan chain.
3555 @item @b{reset-deassert-pre}
3556 @* Issued as part of @command{reset} processing
3557 after @code{reset-assert-post} has been triggered.
3558 @item @b{reset-deassert-post}
3559 @* Issued as part of @command{reset} processing
3560 after @code{reset-deassert-pre} has been triggered
3561 and (if the target is using it) after SRST has been
3562 released on the scan chain.
3564 @* Issued as the final step in @command{reset} processing.
3566 @item @b{reset-halt-post}
3567 @* Currently not used
3568 @item @b{reset-halt-pre}
3569 @* Currently not used
3571 @item @b{reset-init}
3572 @* Used by @b{reset init} command for board-specific initialization.
3573 This event fires after @emph{reset-deassert-post}.
3575 This is where you would configure PLLs and clocking, set up DRAM so
3576 you can download programs that don't fit in on-chip SRAM, set up pin
3577 multiplexing, and so on.
3578 (You may be able to switch to a fast JTAG clock rate here, after
3579 the target clocks are fully set up.)
3580 @item @b{reset-start}
3581 @* Issued as part of @command{reset} processing
3582 before @command{reset_init} is called.
3584 This is the most robust place to use @command{jtag_rclk}
3585 or @command{jtag_khz} to switch to a low JTAG clock rate,
3586 when reset disables PLLs needed to use a fast clock.
3588 @item @b{reset-wait-pos}
3589 @* Currently not used
3590 @item @b{reset-wait-pre}
3591 @* Currently not used
3593 @item @b{resume-start}
3594 @* Before any target is resumed
3595 @item @b{resume-end}
3596 @* After all targets have resumed
3600 @* Target has resumed
3604 @node Flash Commands
3605 @chapter Flash Commands
3607 OpenOCD has different commands for NOR and NAND flash;
3608 the ``flash'' command works with NOR flash, while
3609 the ``nand'' command works with NAND flash.
3610 This partially reflects different hardware technologies:
3611 NOR flash usually supports direct CPU instruction and data bus access,
3612 while data from a NAND flash must be copied to memory before it can be
3613 used. (SPI flash must also be copied to memory before use.)
3614 However, the documentation also uses ``flash'' as a generic term;
3615 for example, ``Put flash configuration in board-specific files''.
3619 @item Configure via the command @command{flash bank}
3620 @* Do this in a board-specific configuration file,
3621 passing parameters as needed by the driver.
3622 @item Operate on the flash via @command{flash subcommand}
3623 @* Often commands to manipulate the flash are typed by a human, or run
3624 via a script in some automated way. Common tasks include writing a
3625 boot loader, operating system, or other data.
3627 @* Flashing via GDB requires the flash be configured via ``flash
3628 bank'', and the GDB flash features be enabled.
3629 @xref{GDB Configuration}.
3632 Many CPUs have the ablity to ``boot'' from the first flash bank.
3633 This means that misprogramming that bank can ``brick'' a system,
3634 so that it can't boot.
3635 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3636 board by (re)installing working boot firmware.
3638 @anchor{NOR Configuration}
3639 @section Flash Configuration Commands
3640 @cindex flash configuration
3642 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
3643 Configures a flash bank which provides persistent storage
3644 for addresses from @math{base} to @math{base + size - 1}.
3645 These banks will often be visible to GDB through the target's memory map.
3646 In some cases, configuring a flash bank will activate extra commands;
3647 see the driver-specific documentation.
3650 @item @var{name} ... may be used to reference the flash bank
3651 in other flash commands.
3652 @item @var{driver} ... identifies the controller driver
3653 associated with the flash bank being declared.
3654 This is usually @code{cfi} for external flash, or else
3655 the name of a microcontroller with embedded flash memory.
3656 @xref{Flash Driver List}.
3657 @item @var{base} ... Base address of the flash chip.
3658 @item @var{size} ... Size of the chip, in bytes.
3659 For some drivers, this value is detected from the hardware.
3660 @item @var{chip_width} ... Width of the flash chip, in bytes;
3661 ignored for most microcontroller drivers.
3662 @item @var{bus_width} ... Width of the data bus used to access the
3663 chip, in bytes; ignored for most microcontroller drivers.
3664 @item @var{target} ... Names the target used to issue
3665 commands to the flash controller.
3666 @comment Actually, it's currently a controller-specific parameter...
3667 @item @var{driver_options} ... drivers may support, or require,
3668 additional parameters. See the driver-specific documentation
3669 for more information.
3672 This command is not available after OpenOCD initialization has completed.
3673 Use it in board specific configuration files, not interactively.
3677 @comment the REAL name for this command is "ocd_flash_banks"
3678 @comment less confusing would be: "flash list" (like "nand list")
3679 @deffn Command {flash banks}
3680 Prints a one-line summary of each device that was
3681 declared using @command{flash bank}, numbered from zero.
3682 Note that this is the @emph{plural} form;
3683 the @emph{singular} form is a very different command.
3686 @deffn Command {flash list}
3687 Retrieves a list of associative arrays for each device that was
3688 declared using @command{flash bank}, numbered from zero.
3689 This returned list can be manipulated easily from within scripts.
3692 @deffn Command {flash probe} num
3693 Identify the flash, or validate the parameters of the configured flash. Operation
3694 depends on the flash type.
3695 The @var{num} parameter is a value shown by @command{flash banks}.
3696 Most flash commands will implicitly @emph{autoprobe} the bank;
3697 flash drivers can distinguish between probing and autoprobing,
3698 but most don't bother.
3701 @section Erasing, Reading, Writing to Flash
3702 @cindex flash erasing
3703 @cindex flash reading
3704 @cindex flash writing
3705 @cindex flash programming
3707 One feature distinguishing NOR flash from NAND or serial flash technologies
3708 is that for read access, it acts exactly like any other addressible memory.
3709 This means you can use normal memory read commands like @command{mdw} or
3710 @command{dump_image} with it, with no special @command{flash} subcommands.
3711 @xref{Memory access}, and @ref{Image access}.
3713 Write access works differently. Flash memory normally needs to be erased
3714 before it's written. Erasing a sector turns all of its bits to ones, and
3715 writing can turn ones into zeroes. This is why there are special commands
3716 for interactive erasing and writing, and why GDB needs to know which parts
3717 of the address space hold NOR flash memory.
3720 Most of these erase and write commands leverage the fact that NOR flash
3721 chips consume target address space. They implicitly refer to the current
3722 JTAG target, and map from an address in that target's address space
3723 back to a flash bank.
3724 @comment In May 2009, those mappings may fail if any bank associated
3725 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3726 A few commands use abstract addressing based on bank and sector numbers,
3727 and don't depend on searching the current target and its address space.
3728 Avoid confusing the two command models.
3731 Some flash chips implement software protection against accidental writes,
3732 since such buggy writes could in some cases ``brick'' a system.
3733 For such systems, erasing and writing may require sector protection to be
3735 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3736 and AT91SAM7 on-chip flash.
3737 @xref{flash protect}.
3739 @anchor{flash erase_sector}
3740 @deffn Command {flash erase_sector} num first last
3741 Erase sectors in bank @var{num}, starting at sector @var{first}
3742 up to and including @var{last}.
3743 Sector numbering starts at 0.
3744 Providing a @var{last} sector of @option{last}
3745 specifies "to the end of the flash bank".
3746 The @var{num} parameter is a value shown by @command{flash banks}.
3749 @deffn Command {flash erase_address} address length
3750 Erase sectors starting at @var{address} for @var{length} bytes.
3751 The flash bank to use is inferred from the @var{address}, and
3752 the specified length must stay within that bank.
3753 As a special case, when @var{length} is zero and @var{address} is
3754 the start of the bank, the whole flash is erased.
3757 @deffn Command {flash fillw} address word length
3758 @deffnx Command {flash fillh} address halfword length
3759 @deffnx Command {flash fillb} address byte length
3760 Fills flash memory with the specified @var{word} (32 bits),
3761 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3762 starting at @var{address} and continuing
3763 for @var{length} units (word/halfword/byte).
3764 No erasure is done before writing; when needed, that must be done
3765 before issuing this command.
3766 Writes are done in blocks of up to 1024 bytes, and each write is
3767 verified by reading back the data and comparing it to what was written.
3768 The flash bank to use is inferred from the @var{address} of
3769 each block, and the specified length must stay within that bank.
3771 @comment no current checks for errors if fill blocks touch multiple banks!
3773 @anchor{flash write_bank}
3774 @deffn Command {flash write_bank} num filename offset
3775 Write the binary @file{filename} to flash bank @var{num},
3776 starting at @var{offset} bytes from the beginning of the bank.
3777 The @var{num} parameter is a value shown by @command{flash banks}.
3780 @anchor{flash write_image}
3781 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
3782 Write the image @file{filename} to the current target's flash bank(s).
3783 A relocation @var{offset} may be specified, in which case it is added
3784 to the base address for each section in the image.
3785 The file [@var{type}] can be specified
3786 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3787 @option{elf} (ELF file), @option{s19} (Motorola s19).
3788 @option{mem}, or @option{builder}.
3789 The relevant flash sectors will be erased prior to programming
3790 if the @option{erase} parameter is given. If @option{unlock} is
3791 provided, then the flash banks are unlocked before erase and
3792 program. The flash bank to use is inferred from the @var{address} of
3796 @section Other Flash commands
3797 @cindex flash protection
3799 @deffn Command {flash erase_check} num
3800 Check erase state of sectors in flash bank @var{num},
3801 and display that status.
3802 The @var{num} parameter is a value shown by @command{flash banks}.
3803 This is the only operation that
3804 updates the erase state information displayed by @option{flash info}. That means you have
3805 to issue a @command{flash erase_check} command after erasing or programming the device
3806 to get updated information.
3807 (Code execution may have invalidated any state records kept by OpenOCD.)
3810 @deffn Command {flash info} num
3811 Print info about flash bank @var{num}
3812 The @var{num} parameter is a value shown by @command{flash banks}.
3813 The information includes per-sector protect status.
3816 @anchor{flash protect}
3817 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3818 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3819 in flash bank @var{num}, starting at sector @var{first}
3820 and continuing up to and including @var{last}.
3821 Providing a @var{last} sector of @option{last}
3822 specifies "to the end of the flash bank".
3823 The @var{num} parameter is a value shown by @command{flash banks}.
3826 @deffn Command {flash protect_check} num
3827 Check protection state of sectors in flash bank @var{num}.
3828 The @var{num} parameter is a value shown by @command{flash banks}.
3829 @comment @option{flash erase_sector} using the same syntax.
3832 @anchor{Flash Driver List}
3833 @section Flash Driver List
3834 As noted above, the @command{flash bank} command requires a driver name,
3835 and allows driver-specific options and behaviors.
3836 Some drivers also activate driver-specific commands.
3838 @subsection External Flash
3840 @deffn {Flash Driver} cfi
3841 @cindex Common Flash Interface
3843 The ``Common Flash Interface'' (CFI) is the main standard for
3844 external NOR flash chips, each of which connects to a
3845 specific external chip select on the CPU.
3846 Frequently the first such chip is used to boot the system.
3847 Your board's @code{reset-init} handler might need to
3848 configure additional chip selects using other commands (like: @command{mww} to
3849 configure a bus and its timings), or
3850 perhaps configure a GPIO pin that controls the ``write protect'' pin
3852 The CFI driver can use a target-specific working area to significantly
3855 The CFI driver can accept the following optional parameters, in any order:
3858 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3859 like AM29LV010 and similar types.
3860 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3863 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3864 wide on a sixteen bit bus:
3867 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3868 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3871 To configure one bank of 32 MBytes
3872 built from two sixteen bit (two byte) wide parts wired in parallel
3873 to create a thirty-two bit (four byte) bus with doubled throughput:
3876 flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
3879 @c "cfi part_id" disabled
3882 @subsection Internal Flash (Microcontrollers)
3884 @deffn {Flash Driver} aduc702x
3885 The ADUC702x analog microcontrollers from Analog Devices
3886 include internal flash and use ARM7TDMI cores.
3887 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3888 The setup command only requires the @var{target} argument
3889 since all devices in this family have the same memory layout.
3892 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3896 @deffn {Flash Driver} at91sam3
3898 All members of the AT91SAM3 microcontroller family from
3899 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3900 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3901 that the driver was orginaly developed and tested using the
3902 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3903 the family was cribbed from the data sheet. @emph{Note to future
3904 readers/updaters: Please remove this worrysome comment after other
3905 chips are confirmed.}
3907 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3908 have one flash bank. In all cases the flash banks are at
3909 the following fixed locations:
3912 # Flash bank 0 - all chips
3913 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3914 # Flash bank 1 - only 256K chips
3915 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3918 Internally, the AT91SAM3 flash memory is organized as follows.
3919 Unlike the AT91SAM7 chips, these are not used as parameters
3920 to the @command{flash bank} command:
3923 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3924 @item @emph{Bank Size:} 128K/64K Per flash bank
3925 @item @emph{Sectors:} 16 or 8 per bank
3926 @item @emph{SectorSize:} 8K Per Sector
3927 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3930 The AT91SAM3 driver adds some additional commands:
3932 @deffn Command {at91sam3 gpnvm}
3933 @deffnx Command {at91sam3 gpnvm clear} number
3934 @deffnx Command {at91sam3 gpnvm set} number
3935 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3936 With no parameters, @command{show} or @command{show all},
3937 shows the status of all GPNVM bits.
3938 With @command{show} @var{number}, displays that bit.
3940 With @command{set} @var{number} or @command{clear} @var{number},
3941 modifies that GPNVM bit.
3944 @deffn Command {at91sam3 info}
3945 This command attempts to display information about the AT91SAM3
3946 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3947 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3948 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3949 various clock configuration registers and attempts to display how it
3950 believes the chip is configured. By default, the SLOWCLK is assumed to
3951 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3954 @deffn Command {at91sam3 slowclk} [value]
3955 This command shows/sets the slow clock frequency used in the
3956 @command{at91sam3 info} command calculations above.
3960 @deffn {Flash Driver} at91sam7
3961 All members of the AT91SAM7 microcontroller family from Atmel include
3962 internal flash and use ARM7TDMI cores. The driver automatically
3963 recognizes a number of these chips using the chip identification
3964 register, and autoconfigures itself.
3967 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3970 For chips which are not recognized by the controller driver, you must
3971 provide additional parameters in the following order:
3974 @item @var{chip_model} ... label used with @command{flash info}
3976 @item @var{sectors_per_bank}
3977 @item @var{pages_per_sector}
3978 @item @var{pages_size}
3979 @item @var{num_nvm_bits}
3980 @item @var{freq_khz} ... required if an external clock is provided,
3981 optional (but recommended) when the oscillator frequency is known
3984 It is recommended that you provide zeroes for all of those values
3985 except the clock frequency, so that everything except that frequency
3986 will be autoconfigured.
3987 Knowing the frequency helps ensure correct timings for flash access.
3989 The flash controller handles erases automatically on a page (128/256 byte)
3990 basis, so explicit erase commands are not necessary for flash programming.
3991 However, there is an ``EraseAll`` command that can erase an entire flash
3992 plane (of up to 256KB), and it will be used automatically when you issue
3993 @command{flash erase_sector} or @command{flash erase_address} commands.
3995 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3996 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3997 bit for the processor. Each processor has a number of such bits,
3998 used for controlling features such as brownout detection (so they
3999 are not truly general purpose).
4001 This assumes that the first flash bank (number 0) is associated with
4002 the appropriate at91sam7 target.
4007 @deffn {Flash Driver} avr
4008 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
4009 @emph{The current implementation is incomplete.}
4010 @comment - defines mass_erase ... pointless given flash_erase_address
4013 @deffn {Flash Driver} ecosflash
4014 @emph{No idea what this is...}
4015 The @var{ecosflash} driver defines one mandatory parameter,
4016 the name of a modules of target code which is downloaded
4020 @deffn {Flash Driver} lpc2000
4021 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
4022 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
4025 There are LPC2000 devices which are not supported by the @var{lpc2000}
4027 The LPC2888 is supported by the @var{lpc288x} driver.
4028 The LPC29xx family is supported by the @var{lpc2900} driver.
4031 The @var{lpc2000} driver defines two mandatory and one optional parameters,
4032 which must appear in the following order:
4035 @item @var{variant} ... required, may be
4036 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
4037 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
4038 or @var{lpc1700} (LPC175x and LPC176x)
4039 @item @var{clock_kHz} ... the frequency, in kiloHertz,
4040 at which the core is running
4041 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
4042 telling the driver to calculate a valid checksum for the exception vector table.
4045 LPC flashes don't require the chip and bus width to be specified.
4048 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
4049 lpc2000_v2 14765 calc_checksum
4052 @deffn {Command} {lpc2000 part_id} bank
4053 Displays the four byte part identifier associated with
4054 the specified flash @var{bank}.
4058 @deffn {Flash Driver} lpc288x
4059 The LPC2888 microcontroller from NXP needs slightly different flash
4060 support from its lpc2000 siblings.
4061 The @var{lpc288x} driver defines one mandatory parameter,
4062 the programming clock rate in Hz.
4063 LPC flashes don't require the chip and bus width to be specified.
4066 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
4070 @deffn {Flash Driver} lpc2900
4071 This driver supports the LPC29xx ARM968E based microcontroller family
4074 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
4075 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
4076 sector layout are auto-configured by the driver.
4077 The driver has one additional mandatory parameter: The CPU clock rate
4078 (in kHz) at the time the flash operations will take place. Most of the time this
4079 will not be the crystal frequency, but a higher PLL frequency. The
4080 @code{reset-init} event handler in the board script is usually the place where
4083 The driver rejects flashless devices (currently the LPC2930).
4085 The EEPROM in LPC2900 devices is not mapped directly into the address space.
4086 It must be handled much more like NAND flash memory, and will therefore be
4087 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
4089 Sector protection in terms of the LPC2900 is handled transparently. Every time a
4090 sector needs to be erased or programmed, it is automatically unprotected.
4091 What is shown as protection status in the @code{flash info} command, is
4092 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
4093 sector from ever being erased or programmed again. As this is an irreversible
4094 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
4095 and not by the standard @code{flash protect} command.
4097 Example for a 125 MHz clock frequency:
4099 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
4102 Some @code{lpc2900}-specific commands are defined. In the following command list,
4103 the @var{bank} parameter is the bank number as obtained by the
4104 @code{flash banks} command.
4106 @deffn Command {lpc2900 signature} bank
4107 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
4108 content. This is a hardware feature of the flash block, hence the calculation is
4109 very fast. You may use this to verify the content of a programmed device against
4114 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
4118 @deffn Command {lpc2900 read_custom} bank filename
4119 Reads the 912 bytes of customer information from the flash index sector, and
4120 saves it to a file in binary format.
4123 lpc2900 read_custom 0 /path_to/customer_info.bin
4127 The index sector of the flash is a @emph{write-only} sector. It cannot be
4128 erased! In order to guard against unintentional write access, all following
4129 commands need to be preceeded by a successful call to the @code{password}
4132 @deffn Command {lpc2900 password} bank password
4133 You need to use this command right before each of the following commands:
4134 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
4135 @code{lpc2900 secure_jtag}.
4137 The password string is fixed to "I_know_what_I_am_doing".
4140 lpc2900 password 0 I_know_what_I_am_doing
4141 Potentially dangerous operation allowed in next command!
4145 @deffn Command {lpc2900 write_custom} bank filename type
4146 Writes the content of the file into the customer info space of the flash index
4147 sector. The filetype can be specified with the @var{type} field. Possible values
4148 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4149 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4150 contain a single section, and the contained data length must be exactly
4152 @quotation Attention
4153 This cannot be reverted! Be careful!
4157 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4161 @deffn Command {lpc2900 secure_sector} bank first last
4162 Secures the sector range from @var{first} to @var{last} (including) against
4163 further program and erase operations. The sector security will be effective
4164 after the next power cycle.
4165 @quotation Attention
4166 This cannot be reverted! Be careful!
4168 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4171 lpc2900 secure_sector 0 1 1
4173 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4174 # 0: 0x00000000 (0x2000 8kB) not protected
4175 # 1: 0x00002000 (0x2000 8kB) protected
4176 # 2: 0x00004000 (0x2000 8kB) not protected
4180 @deffn Command {lpc2900 secure_jtag} bank
4181 Irreversibly disable the JTAG port. The new JTAG security setting will be
4182 effective after the next power cycle.
4183 @quotation Attention
4184 This cannot be reverted! Be careful!
4188 lpc2900 secure_jtag 0
4193 @deffn {Flash Driver} ocl
4194 @emph{No idea what this is, other than using some arm7/arm9 core.}
4197 flash bank ocl 0 0 0 0 $_TARGETNAME
4201 @deffn {Flash Driver} pic32mx
4202 The PIC32MX microcontrollers are based on the MIPS 4K cores,
4203 and integrate flash memory.
4204 @emph{The current implementation is incomplete.}
4207 flash bank pix32mx 0 0 0 0 $_TARGETNAME
4210 @comment numerous *disabled* commands are defined:
4211 @comment - chip_erase ... pointless given flash_erase_address
4212 @comment - lock, unlock ... pointless given protect on/off (yes?)
4213 @comment - pgm_word ... shouldn't bank be deduced from address??
4214 Some pic32mx-specific commands are defined:
4215 @deffn Command {pic32mx pgm_word} address value bank
4216 Programs the specified 32-bit @var{value} at the given @var{address}
4217 in the specified chip @var{bank}.
4221 @deffn {Flash Driver} stellaris
4222 All members of the Stellaris LM3Sxxx microcontroller family from
4224 include internal flash and use ARM Cortex M3 cores.
4225 The driver automatically recognizes a number of these chips using
4226 the chip identification register, and autoconfigures itself.
4227 @footnote{Currently there is a @command{stellaris mass_erase} command.
4228 That seems pointless since the same effect can be had using the
4229 standard @command{flash erase_address} command.}
4232 flash bank stellaris 0 0 0 0 $_TARGETNAME
4236 @deffn {Flash Driver} stm32x
4237 All members of the STM32 microcontroller family from ST Microelectronics
4238 include internal flash and use ARM Cortex M3 cores.
4239 The driver automatically recognizes a number of these chips using
4240 the chip identification register, and autoconfigures itself.
4243 flash bank stm32x 0 0 0 0 $_TARGETNAME
4246 Some stm32x-specific commands
4247 @footnote{Currently there is a @command{stm32x mass_erase} command.
4248 That seems pointless since the same effect can be had using the
4249 standard @command{flash erase_address} command.}
4252 @deffn Command {stm32x lock} num
4253 Locks the entire stm32 device.
4254 The @var{num} parameter is a value shown by @command{flash banks}.
4257 @deffn Command {stm32x unlock} num
4258 Unlocks the entire stm32 device.
4259 The @var{num} parameter is a value shown by @command{flash banks}.
4262 @deffn Command {stm32x options_read} num
4263 Read and display the stm32 option bytes written by
4264 the @command{stm32x options_write} command.
4265 The @var{num} parameter is a value shown by @command{flash banks}.
4268 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4269 Writes the stm32 option byte with the specified values.
4270 The @var{num} parameter is a value shown by @command{flash banks}.
4274 @deffn {Flash Driver} str7x
4275 All members of the STR7 microcontroller family from ST Microelectronics
4276 include internal flash and use ARM7TDMI cores.
4277 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4278 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4281 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4284 @deffn Command {str7x disable_jtag} bank
4285 Activate the Debug/Readout protection mechanism
4286 for the specified flash bank.
4290 @deffn {Flash Driver} str9x
4291 Most members of the STR9 microcontroller family from ST Microelectronics
4292 include internal flash and use ARM966E cores.
4293 The str9 needs the flash controller to be configured using
4294 the @command{str9x flash_config} command prior to Flash programming.
4297 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4298 str9x flash_config 0 4 2 0 0x80000
4301 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4302 Configures the str9 flash controller.
4303 The @var{num} parameter is a value shown by @command{flash banks}.
4306 @item @var{bbsr} - Boot Bank Size register
4307 @item @var{nbbsr} - Non Boot Bank Size register
4308 @item @var{bbadr} - Boot Bank Start Address register
4309 @item @var{nbbadr} - Boot Bank Start Address register
4315 @deffn {Flash Driver} tms470
4316 Most members of the TMS470 microcontroller family from Texas Instruments
4317 include internal flash and use ARM7TDMI cores.
4318 This driver doesn't require the chip and bus width to be specified.
4320 Some tms470-specific commands are defined:
4322 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
4323 Saves programming keys in a register, to enable flash erase and write commands.
4326 @deffn Command {tms470 osc_mhz} clock_mhz
4327 Reports the clock speed, which is used to calculate timings.
4330 @deffn Command {tms470 plldis} (0|1)
4331 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
4336 @subsection str9xpec driver
4339 Here is some background info to help
4340 you better understand how this driver works. OpenOCD has two flash drivers for
4344 Standard driver @option{str9x} programmed via the str9 core. Normally used for
4345 flash programming as it is faster than the @option{str9xpec} driver.
4347 Direct programming @option{str9xpec} using the flash controller. This is an
4348 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
4349 core does not need to be running to program using this flash driver. Typical use
4350 for this driver is locking/unlocking the target and programming the option bytes.
4353 Before we run any commands using the @option{str9xpec} driver we must first disable
4354 the str9 core. This example assumes the @option{str9xpec} driver has been
4355 configured for flash bank 0.
4357 # assert srst, we do not want core running
4358 # while accessing str9xpec flash driver
4360 # turn off target polling
4363 str9xpec enable_turbo 0
4365 str9xpec options_read 0
4366 # re-enable str9 core
4367 str9xpec disable_turbo 0
4371 The above example will read the str9 option bytes.
4372 When performing a unlock remember that you will not be able to halt the str9 - it
4373 has been locked. Halting the core is not required for the @option{str9xpec} driver
4374 as mentioned above, just issue the commands above manually or from a telnet prompt.
4376 @deffn {Flash Driver} str9xpec
4377 Only use this driver for locking/unlocking the device or configuring the option bytes.
4378 Use the standard str9 driver for programming.
4379 Before using the flash commands the turbo mode must be enabled using the
4380 @command{str9xpec enable_turbo} command.
4382 Several str9xpec-specific commands are defined:
4384 @deffn Command {str9xpec disable_turbo} num
4385 Restore the str9 into JTAG chain.
4388 @deffn Command {str9xpec enable_turbo} num
4389 Enable turbo mode, will simply remove the str9 from the chain and talk
4390 directly to the embedded flash controller.
4393 @deffn Command {str9xpec lock} num
4394 Lock str9 device. The str9 will only respond to an unlock command that will
4398 @deffn Command {str9xpec part_id} num
4399 Prints the part identifier for bank @var{num}.
4402 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4403 Configure str9 boot bank.
4406 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4407 Configure str9 lvd source.
4410 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4411 Configure str9 lvd threshold.
4414 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4415 Configure str9 lvd reset warning source.
4418 @deffn Command {str9xpec options_read} num
4419 Read str9 option bytes.
4422 @deffn Command {str9xpec options_write} num
4423 Write str9 option bytes.
4426 @deffn Command {str9xpec unlock} num
4435 @subsection mFlash Configuration
4436 @cindex mFlash Configuration
4438 @deffn {Config Command} {mflash bank} soc base RST_pin target
4439 Configures a mflash for @var{soc} host bank at
4441 The pin number format depends on the host GPIO naming convention.
4442 Currently, the mflash driver supports s3c2440 and pxa270.
4444 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4447 mflash bank s3c2440 0x10000000 1b 0
4450 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4453 mflash bank pxa270 0x08000000 43 0
4457 @subsection mFlash commands
4458 @cindex mFlash commands
4460 @deffn Command {mflash config pll} frequency
4461 Configure mflash PLL.
4462 The @var{frequency} is the mflash input frequency, in Hz.
4463 Issuing this command will erase mflash's whole internal nand and write new pll.
4464 After this command, mflash needs power-on-reset for normal operation.
4465 If pll was newly configured, storage and boot(optional) info also need to be update.
4468 @deffn Command {mflash config boot}
4469 Configure bootable option.
4470 If bootable option is set, mflash offer the first 8 sectors
4474 @deffn Command {mflash config storage}
4475 Configure storage information.
4476 For the normal storage operation, this information must be
4480 @deffn Command {mflash dump} num filename offset size
4481 Dump @var{size} bytes, starting at @var{offset} bytes from the
4482 beginning of the bank @var{num}, to the file named @var{filename}.
4485 @deffn Command {mflash probe}
4489 @deffn Command {mflash write} num filename offset
4490 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4491 @var{offset} bytes from the beginning of the bank.
4494 @node NAND Flash Commands
4495 @chapter NAND Flash Commands
4498 Compared to NOR or SPI flash, NAND devices are inexpensive
4499 and high density. Today's NAND chips, and multi-chip modules,
4500 commonly hold multiple GigaBytes of data.
4502 NAND chips consist of a number of ``erase blocks'' of a given
4503 size (such as 128 KBytes), each of which is divided into a
4504 number of pages (of perhaps 512 or 2048 bytes each). Each
4505 page of a NAND flash has an ``out of band'' (OOB) area to hold
4506 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4507 of OOB for every 512 bytes of page data.
4509 One key characteristic of NAND flash is that its error rate
4510 is higher than that of NOR flash. In normal operation, that
4511 ECC is used to correct and detect errors. However, NAND
4512 blocks can also wear out and become unusable; those blocks
4513 are then marked "bad". NAND chips are even shipped from the
4514 manufacturer with a few bad blocks. The highest density chips
4515 use a technology (MLC) that wears out more quickly, so ECC
4516 support is increasingly important as a way to detect blocks
4517 that have begun to fail, and help to preserve data integrity
4518 with techniques such as wear leveling.
4520 Software is used to manage the ECC. Some controllers don't
4521 support ECC directly; in those cases, software ECC is used.
4522 Other controllers speed up the ECC calculations with hardware.
4523 Single-bit error correction hardware is routine. Controllers
4524 geared for newer MLC chips may correct 4 or more errors for
4525 every 512 bytes of data.
4527 You will need to make sure that any data you write using
4528 OpenOCD includes the apppropriate kind of ECC. For example,
4529 that may mean passing the @code{oob_softecc} flag when
4530 writing NAND data, or ensuring that the correct hardware
4533 The basic steps for using NAND devices include:
4535 @item Declare via the command @command{nand device}
4536 @* Do this in a board-specific configuration file,
4537 passing parameters as needed by the controller.
4538 @item Configure each device using @command{nand probe}.
4539 @* Do this only after the associated target is set up,
4540 such as in its reset-init script or in procures defined
4541 to access that device.
4542 @item Operate on the flash via @command{nand subcommand}
4543 @* Often commands to manipulate the flash are typed by a human, or run
4544 via a script in some automated way. Common task include writing a
4545 boot loader, operating system, or other data needed to initialize or
4549 @b{NOTE:} At the time this text was written, the largest NAND
4550 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4551 This is because the variables used to hold offsets and lengths
4552 are only 32 bits wide.
4553 (Larger chips may work in some cases, unless an offset or length
4554 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4555 Some larger devices will work, since they are actually multi-chip
4556 modules with two smaller chips and individual chipselect lines.
4558 @anchor{NAND Configuration}
4559 @section NAND Configuration Commands
4560 @cindex NAND configuration
4562 NAND chips must be declared in configuration scripts,
4563 plus some additional configuration that's done after
4564 OpenOCD has initialized.
4566 @deffn {Config Command} {nand device} name controller target [configparams...]
4567 Declares a NAND device, which can be read and written to
4568 after it has been configured through @command{nand probe}.
4569 In OpenOCD, devices are single chips; this is unlike some
4570 operating systems, which may manage multiple chips as if
4571 they were a single (larger) device.
4572 In some cases, configuring a device will activate extra
4573 commands; see the controller-specific documentation.
4575 @b{NOTE:} This command is not available after OpenOCD
4576 initialization has completed. Use it in board specific
4577 configuration files, not interactively.
4580 @item @var{name} ... may be used to reference the NAND bank
4582 @item @var{controller} ... identifies the controller driver
4583 associated with the NAND device being declared.
4584 @xref{NAND Driver List}.
4585 @item @var{target} ... names the target used when issuing
4586 commands to the NAND controller.
4587 @comment Actually, it's currently a controller-specific parameter...
4588 @item @var{configparams} ... controllers may support, or require,
4589 additional parameters. See the controller-specific documentation
4590 for more information.
4594 @deffn Command {nand list}
4595 Prints a summary of each device declared
4596 using @command{nand device}, numbered from zero.
4597 Note that un-probed devices show no details.
4600 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4601 blocksize: 131072, blocks: 8192
4602 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4603 blocksize: 131072, blocks: 8192
4608 @deffn Command {nand probe} num
4609 Probes the specified device to determine key characteristics
4610 like its page and block sizes, and how many blocks it has.
4611 The @var{num} parameter is the value shown by @command{nand list}.
4612 You must (successfully) probe a device before you can use
4613 it with most other NAND commands.
4616 @section Erasing, Reading, Writing to NAND Flash
4618 @deffn Command {nand dump} num filename offset length [oob_option]
4619 @cindex NAND reading
4620 Reads binary data from the NAND device and writes it to the file,
4621 starting at the specified offset.
4622 The @var{num} parameter is the value shown by @command{nand list}.
4624 Use a complete path name for @var{filename}, so you don't depend
4625 on the directory used to start the OpenOCD server.
4627 The @var{offset} and @var{length} must be exact multiples of the
4628 device's page size. They describe a data region; the OOB data
4629 associated with each such page may also be accessed.
4631 @b{NOTE:} At the time this text was written, no error correction
4632 was done on the data that's read, unless raw access was disabled
4633 and the underlying NAND controller driver had a @code{read_page}
4634 method which handled that error correction.
4636 By default, only page data is saved to the specified file.
4637 Use an @var{oob_option} parameter to save OOB data:
4639 @item no oob_* parameter
4640 @*Output file holds only page data; OOB is discarded.
4641 @item @code{oob_raw}
4642 @*Output file interleaves page data and OOB data;
4643 the file will be longer than "length" by the size of the
4644 spare areas associated with each data page.
4645 Note that this kind of "raw" access is different from
4646 what's implied by @command{nand raw_access}, which just
4647 controls whether a hardware-aware access method is used.
4648 @item @code{oob_only}
4649 @*Output file has only raw OOB data, and will
4650 be smaller than "length" since it will contain only the
4651 spare areas associated with each data page.
4655 @deffn Command {nand erase} num [offset length]
4656 @cindex NAND erasing
4657 @cindex NAND programming
4658 Erases blocks on the specified NAND device, starting at the
4659 specified @var{offset} and continuing for @var{length} bytes.
4660 Both of those values must be exact multiples of the device's
4661 block size, and the region they specify must fit entirely in the chip.
4662 If those parameters are not specified,
4663 the whole NAND chip will be erased.
4664 The @var{num} parameter is the value shown by @command{nand list}.
4666 @b{NOTE:} This command will try to erase bad blocks, when told
4667 to do so, which will probably invalidate the manufacturer's bad
4669 For the remainder of the current server session, @command{nand info}
4670 will still report that the block ``is'' bad.
4673 @deffn Command {nand write} num filename offset [option...]
4674 @cindex NAND writing
4675 @cindex NAND programming
4676 Writes binary data from the file into the specified NAND device,
4677 starting at the specified offset. Those pages should already
4678 have been erased; you can't change zero bits to one bits.
4679 The @var{num} parameter is the value shown by @command{nand list}.
4681 Use a complete path name for @var{filename}, so you don't depend
4682 on the directory used to start the OpenOCD server.
4684 The @var{offset} must be an exact multiple of the device's page size.
4685 All data in the file will be written, assuming it doesn't run
4686 past the end of the device.
4687 Only full pages are written, and any extra space in the last
4688 page will be filled with 0xff bytes. (That includes OOB data,
4689 if that's being written.)
4691 @b{NOTE:} At the time this text was written, bad blocks are
4692 ignored. That is, this routine will not skip bad blocks,
4693 but will instead try to write them. This can cause problems.
4695 Provide at most one @var{option} parameter. With some
4696 NAND drivers, the meanings of these parameters may change
4697 if @command{nand raw_access} was used to disable hardware ECC.
4699 @item no oob_* parameter
4700 @*File has only page data, which is written.
4701 If raw acccess is in use, the OOB area will not be written.
4702 Otherwise, if the underlying NAND controller driver has
4703 a @code{write_page} routine, that routine may write the OOB
4704 with hardware-computed ECC data.
4705 @item @code{oob_only}
4706 @*File has only raw OOB data, which is written to the OOB area.
4707 Each page's data area stays untouched. @i{This can be a dangerous
4708 option}, since it can invalidate the ECC data.
4709 You may need to force raw access to use this mode.
4710 @item @code{oob_raw}
4711 @*File interleaves data and OOB data, both of which are written
4712 If raw access is enabled, the data is written first, then the
4714 Otherwise, if the underlying NAND controller driver has
4715 a @code{write_page} routine, that routine may modify the OOB
4716 before it's written, to include hardware-computed ECC data.
4717 @item @code{oob_softecc}
4718 @*File has only page data, which is written.
4719 The OOB area is filled with 0xff, except for a standard 1-bit
4720 software ECC code stored in conventional locations.
4721 You might need to force raw access to use this mode, to prevent
4722 the underlying driver from applying hardware ECC.
4723 @item @code{oob_softecc_kw}
4724 @*File has only page data, which is written.
4725 The OOB area is filled with 0xff, except for a 4-bit software ECC
4726 specific to the boot ROM in Marvell Kirkwood SoCs.
4727 You might need to force raw access to use this mode, to prevent
4728 the underlying driver from applying hardware ECC.
4732 @deffn Command {nand verify} num filename offset [option...]
4733 @cindex NAND verification
4734 @cindex NAND programming
4735 Verify the binary data in the file has been programmed to the
4736 specified NAND device, starting at the specified offset.
4737 The @var{num} parameter is the value shown by @command{nand list}.
4739 Use a complete path name for @var{filename}, so you don't depend
4740 on the directory used to start the OpenOCD server.
4742 The @var{offset} must be an exact multiple of the device's page size.
4743 All data in the file will be read and compared to the contents of the
4744 flash, assuming it doesn't run past the end of the device.
4745 As with @command{nand write}, only full pages are verified, so any extra
4746 space in the last page will be filled with 0xff bytes.
4748 The same @var{options} accepted by @command{nand write},
4749 and the file will be processed similarly to produce the buffers that
4750 can be compared against the contents produced from @command{nand dump}.
4752 @b{NOTE:} This will not work when the underlying NAND controller
4753 driver's @code{write_page} routine must update the OOB with a
4754 hardward-computed ECC before the data is written. This limitation may
4755 be removed in a future release.
4758 @section Other NAND commands
4759 @cindex NAND other commands
4761 @deffn Command {nand check_bad_blocks} [offset length]
4762 Checks for manufacturer bad block markers on the specified NAND
4763 device. If no parameters are provided, checks the whole
4764 device; otherwise, starts at the specified @var{offset} and
4765 continues for @var{length} bytes.
4766 Both of those values must be exact multiples of the device's
4767 block size, and the region they specify must fit entirely in the chip.
4768 The @var{num} parameter is the value shown by @command{nand list}.
4770 @b{NOTE:} Before using this command you should force raw access
4771 with @command{nand raw_access enable} to ensure that the underlying
4772 driver will not try to apply hardware ECC.
4775 @deffn Command {nand info} num
4776 The @var{num} parameter is the value shown by @command{nand list}.
4777 This prints the one-line summary from "nand list", plus for
4778 devices which have been probed this also prints any known
4779 status for each block.
4782 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4783 Sets or clears an flag affecting how page I/O is done.
4784 The @var{num} parameter is the value shown by @command{nand list}.
4786 This flag is cleared (disabled) by default, but changing that
4787 value won't affect all NAND devices. The key factor is whether
4788 the underlying driver provides @code{read_page} or @code{write_page}
4789 methods. If it doesn't provide those methods, the setting of
4790 this flag is irrelevant; all access is effectively ``raw''.
4792 When those methods exist, they are normally used when reading
4793 data (@command{nand dump} or reading bad block markers) or
4794 writing it (@command{nand write}). However, enabling
4795 raw access (setting the flag) prevents use of those methods,
4796 bypassing hardware ECC logic.
4797 @i{This can be a dangerous option}, since writing blocks
4798 with the wrong ECC data can cause them to be marked as bad.
4801 @anchor{NAND Driver List}
4802 @section NAND Driver List
4803 As noted above, the @command{nand device} command allows
4804 driver-specific options and behaviors.
4805 Some controllers also activate controller-specific commands.
4807 @deffn {NAND Driver} davinci
4808 This driver handles the NAND controllers found on DaVinci family
4809 chips from Texas Instruments.
4810 It takes three extra parameters:
4811 address of the NAND chip;
4812 hardware ECC mode to use (@option{hwecc1},
4813 @option{hwecc4}, @option{hwecc4_infix});
4814 address of the AEMIF controller on this processor.
4816 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4818 All DaVinci processors support the single-bit ECC hardware,
4819 and newer ones also support the four-bit ECC hardware.
4820 The @code{write_page} and @code{read_page} methods are used
4821 to implement those ECC modes, unless they are disabled using
4822 the @command{nand raw_access} command.
4825 @deffn {NAND Driver} lpc3180
4826 These controllers require an extra @command{nand device}
4827 parameter: the clock rate used by the controller.
4828 @deffn Command {lpc3180 select} num [mlc|slc]
4829 Configures use of the MLC or SLC controller mode.
4830 MLC implies use of hardware ECC.
4831 The @var{num} parameter is the value shown by @command{nand list}.
4834 At this writing, this driver includes @code{write_page}
4835 and @code{read_page} methods. Using @command{nand raw_access}
4836 to disable those methods will prevent use of hardware ECC
4837 in the MLC controller mode, but won't change SLC behavior.
4839 @comment current lpc3180 code won't issue 5-byte address cycles
4841 @deffn {NAND Driver} orion
4842 These controllers require an extra @command{nand device}
4843 parameter: the address of the controller.
4845 nand device orion 0xd8000000
4847 These controllers don't define any specialized commands.
4848 At this writing, their drivers don't include @code{write_page}
4849 or @code{read_page} methods, so @command{nand raw_access} won't
4850 change any behavior.
4853 @deffn {NAND Driver} s3c2410
4854 @deffnx {NAND Driver} s3c2412
4855 @deffnx {NAND Driver} s3c2440
4856 @deffnx {NAND Driver} s3c2443
4857 These S3C24xx family controllers don't have any special
4858 @command{nand device} options, and don't define any
4859 specialized commands.
4860 At this writing, their drivers don't include @code{write_page}
4861 or @code{read_page} methods, so @command{nand raw_access} won't
4862 change any behavior.
4865 @node PLD/FPGA Commands
4866 @chapter PLD/FPGA Commands
4870 Programmable Logic Devices (PLDs) and the more flexible
4871 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4872 OpenOCD can support programming them.
4873 Although PLDs are generally restrictive (cells are less functional, and
4874 there are no special purpose cells for memory or computational tasks),
4875 they share the same OpenOCD infrastructure.
4876 Accordingly, both are called PLDs here.
4878 @section PLD/FPGA Configuration and Commands
4880 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4881 OpenOCD maintains a list of PLDs available for use in various commands.
4882 Also, each such PLD requires a driver.
4884 They are referenced by the number shown by the @command{pld devices} command,
4885 and new PLDs are defined by @command{pld device driver_name}.
4887 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4888 Defines a new PLD device, supported by driver @var{driver_name},
4889 using the TAP named @var{tap_name}.
4890 The driver may make use of any @var{driver_options} to configure its
4894 @deffn {Command} {pld devices}
4895 Lists the PLDs and their numbers.
4898 @deffn {Command} {pld load} num filename
4899 Loads the file @file{filename} into the PLD identified by @var{num}.
4900 The file format must be inferred by the driver.
4903 @section PLD/FPGA Drivers, Options, and Commands
4905 Drivers may support PLD-specific options to the @command{pld device}
4906 definition command, and may also define commands usable only with
4907 that particular type of PLD.
4909 @deffn {FPGA Driver} virtex2
4910 Virtex-II is a family of FPGAs sold by Xilinx.
4911 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4912 No driver-specific PLD definition options are used,
4913 and one driver-specific command is defined.
4915 @deffn {Command} {virtex2 read_stat} num
4916 Reads and displays the Virtex-II status register (STAT)
4921 @node General Commands
4922 @chapter General Commands
4925 The commands documented in this chapter here are common commands that
4926 you, as a human, may want to type and see the output of. Configuration type
4927 commands are documented elsewhere.
4931 @item @b{Source Of Commands}
4932 @* OpenOCD commands can occur in a configuration script (discussed
4933 elsewhere) or typed manually by a human or supplied programatically,
4934 or via one of several TCP/IP Ports.
4936 @item @b{From the human}
4937 @* A human should interact with the telnet interface (default port: 4444)
4938 or via GDB (default port 3333).
4940 To issue commands from within a GDB session, use the @option{monitor}
4941 command, e.g. use @option{monitor poll} to issue the @option{poll}
4942 command. All output is relayed through the GDB session.
4944 @item @b{Machine Interface}
4945 The Tcl interface's intent is to be a machine interface. The default Tcl
4950 @section Daemon Commands
4952 @deffn {Command} exit
4953 Exits the current telnet session.
4956 @c note EXTREMELY ANNOYING word wrap at column 75
4957 @c even when lines are e.g. 100+ columns ...
4958 @c coded in startup.tcl
4959 @deffn {Command} help [string]
4960 With no parameters, prints help text for all commands.
4961 Otherwise, prints each helptext containing @var{string}.
4962 Not every command provides helptext.
4965 @deffn Command sleep msec [@option{busy}]
4966 Wait for at least @var{msec} milliseconds before resuming.
4967 If @option{busy} is passed, busy-wait instead of sleeping.
4968 (This option is strongly discouraged.)
4969 Useful in connection with script files
4970 (@command{script} command and @command{target_name} configuration).
4973 @deffn Command shutdown
4974 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4977 @anchor{debug_level}
4978 @deffn Command debug_level [n]
4979 @cindex message level
4980 Display debug level.
4981 If @var{n} (from 0..3) is provided, then set it to that level.
4982 This affects the kind of messages sent to the server log.
4983 Level 0 is error messages only;
4984 level 1 adds warnings;
4985 level 2 adds informational messages;
4986 and level 3 adds debugging messages.
4987 The default is level 2, but that can be overridden on
4988 the command line along with the location of that log
4989 file (which is normally the server's standard output).
4993 @deffn Command fast (@option{enable}|@option{disable})
4995 Set default behaviour of OpenOCD to be "fast and dangerous".
4997 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4998 fast memory access, and DCC downloads. Those parameters may still be
4999 individually overridden.
5001 The target specific "dangerous" optimisation tweaking options may come and go
5002 as more robust and user friendly ways are found to ensure maximum throughput
5003 and robustness with a minimum of configuration.
5005 Typically the "fast enable" is specified first on the command line:
5008 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
5012 @deffn Command echo message
5013 Logs a message at "user" priority.
5014 Output @var{message} to stdout.
5016 echo "Downloading kernel -- please wait"
5020 @deffn Command log_output [filename]
5021 Redirect logging to @var{filename};
5022 the initial log output channel is stderr.
5025 @anchor{Target State handling}
5026 @section Target State handling
5029 @cindex target initialization
5031 In this section ``target'' refers to a CPU configured as
5032 shown earlier (@pxref{CPU Configuration}).
5033 These commands, like many, implicitly refer to
5034 a current target which is used to perform the
5035 various operations. The current target may be changed
5036 by using @command{targets} command with the name of the
5037 target which should become current.
5039 @deffn Command reg [(number|name) [value]]
5040 Access a single register by @var{number} or by its @var{name}.
5041 The target must generally be halted before access to CPU core
5042 registers is allowed. Depending on the hardware, some other
5043 registers may be accessible while the target is running.
5045 @emph{With no arguments}:
5046 list all available registers for the current target,
5047 showing number, name, size, value, and cache status.
5048 For valid entries, a value is shown; valid entries
5049 which are also dirty (and will be written back later)
5050 are flagged as such.
5052 @emph{With number/name}: display that register's value.
5054 @emph{With both number/name and value}: set register's value.
5055 Writes may be held in a writeback cache internal to OpenOCD,
5056 so that setting the value marks the register as dirty instead
5057 of immediately flushing that value. Resuming CPU execution
5058 (including by single stepping) or otherwise activating the
5059 relevant module will flush such values.
5061 Cores may have surprisingly many registers in their
5062 Debug and trace infrastructure:
5067 (0) r0 (/32): 0x0000D3C2 (dirty)
5068 (1) r1 (/32): 0xFD61F31C
5071 (164) ETM_contextid_comparator_mask (/32)
5076 @deffn Command halt [ms]
5077 @deffnx Command wait_halt [ms]
5078 The @command{halt} command first sends a halt request to the target,
5079 which @command{wait_halt} doesn't.
5080 Otherwise these behave the same: wait up to @var{ms} milliseconds,
5081 or 5 seconds if there is no parameter, for the target to halt
5082 (and enter debug mode).
5083 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
5086 On ARM cores, software using the @emph{wait for interrupt} operation
5087 often blocks the JTAG access needed by a @command{halt} command.
5088 This is because that operation also puts the core into a low
5089 power mode by gating the core clock;
5090 but the core clock is needed to detect JTAG clock transitions.
5092 One partial workaround uses adaptive clocking: when the core is
5093 interrupted the operation completes, then JTAG clocks are accepted
5094 at least until the interrupt handler completes.
5095 However, this workaround is often unusable since the processor, board,
5096 and JTAG adapter must all support adaptive JTAG clocking.
5097 Also, it can't work until an interrupt is issued.
5099 A more complete workaround is to not use that operation while you
5100 work with a JTAG debugger.
5101 Tasking environments generaly have idle loops where the body is the
5102 @emph{wait for interrupt} operation.
5103 (On older cores, it is a coprocessor action;
5104 newer cores have a @option{wfi} instruction.)
5105 Such loops can just remove that operation, at the cost of higher
5106 power consumption (because the CPU is needlessly clocked).
5111 @deffn Command resume [address]
5112 Resume the target at its current code position,
5113 or the optional @var{address} if it is provided.
5114 OpenOCD will wait 5 seconds for the target to resume.
5117 @deffn Command step [address]
5118 Single-step the target at its current code position,
5119 or the optional @var{address} if it is provided.
5122 @anchor{Reset Command}
5123 @deffn Command reset
5124 @deffnx Command {reset run}
5125 @deffnx Command {reset halt}
5126 @deffnx Command {reset init}
5127 Perform as hard a reset as possible, using SRST if possible.
5128 @emph{All defined targets will be reset, and target
5129 events will fire during the reset sequence.}
5131 The optional parameter specifies what should
5132 happen after the reset.
5133 If there is no parameter, a @command{reset run} is executed.
5134 The other options will not work on all systems.
5135 @xref{Reset Configuration}.
5138 @item @b{run} Let the target run
5139 @item @b{halt} Immediately halt the target
5140 @item @b{init} Immediately halt the target, and execute the reset-init script
5144 @deffn Command soft_reset_halt
5145 Requesting target halt and executing a soft reset. This is often used
5146 when a target cannot be reset and halted. The target, after reset is
5147 released begins to execute code. OpenOCD attempts to stop the CPU and
5148 then sets the program counter back to the reset vector. Unfortunately
5149 the code that was executed may have left the hardware in an unknown
5153 @section I/O Utilities
5155 These commands are available when
5156 OpenOCD is built with @option{--enable-ioutil}.
5157 They are mainly useful on embedded targets,
5159 Hosts with operating systems have complementary tools.
5161 @emph{Note:} there are several more such commands.
5163 @deffn Command append_file filename [string]*
5164 Appends the @var{string} parameters to
5165 the text file @file{filename}.
5166 Each string except the last one is followed by one space.
5167 The last string is followed by a newline.
5170 @deffn Command cat filename
5171 Reads and displays the text file @file{filename}.
5174 @deffn Command cp src_filename dest_filename
5175 Copies contents from the file @file{src_filename}
5176 into @file{dest_filename}.
5180 @emph{No description provided.}
5184 @emph{No description provided.}
5188 @emph{No description provided.}
5191 @deffn Command meminfo
5192 Display available RAM memory on OpenOCD host.
5193 Used in OpenOCD regression testing scripts.
5197 @emph{No description provided.}
5201 @emph{No description provided.}
5204 @deffn Command rm filename
5205 @c "rm" has both normal and Jim-level versions??
5206 Unlinks the file @file{filename}.
5209 @deffn Command trunc filename
5210 Removes all data in the file @file{filename}.
5213 @anchor{Memory access}
5214 @section Memory access commands
5215 @cindex memory access
5217 These commands allow accesses of a specific size to the memory
5218 system. Often these are used to configure the current target in some
5219 special way. For example - one may need to write certain values to the
5220 SDRAM controller to enable SDRAM.
5223 @item Use the @command{targets} (plural) command
5224 to change the current target.
5225 @item In system level scripts these commands are deprecated.
5226 Please use their TARGET object siblings to avoid making assumptions
5227 about what TAP is the current target, or about MMU configuration.
5230 @deffn Command mdw [phys] addr [count]
5231 @deffnx Command mdh [phys] addr [count]
5232 @deffnx Command mdb [phys] addr [count]
5233 Display contents of address @var{addr}, as
5234 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5235 or 8-bit bytes (@command{mdb}).
5236 When the current target has an MMU which is present and active,
5237 @var{addr} is interpreted as a virtual address.
5238 Otherwise, or if the optional @var{phys} flag is specified,
5239 @var{addr} is interpreted as a physical address.
5240 If @var{count} is specified, displays that many units.
5241 (If you want to manipulate the data instead of displaying it,
5242 see the @code{mem2array} primitives.)
5245 @deffn Command mww [phys] addr word
5246 @deffnx Command mwh [phys] addr halfword
5247 @deffnx Command mwb [phys] addr byte
5248 Writes the specified @var{word} (32 bits),
5249 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5250 at the specified address @var{addr}.
5251 When the current target has an MMU which is present and active,
5252 @var{addr} is interpreted as a virtual address.
5253 Otherwise, or if the optional @var{phys} flag is specified,
5254 @var{addr} is interpreted as a physical address.
5258 @anchor{Image access}
5259 @section Image loading commands
5260 @cindex image loading
5261 @cindex image dumping
5264 @deffn Command {dump_image} filename address size
5265 Dump @var{size} bytes of target memory starting at @var{address} to the
5266 binary file named @var{filename}.
5269 @deffn Command {fast_load}
5270 Loads an image stored in memory by @command{fast_load_image} to the
5271 current target. Must be preceeded by fast_load_image.
5274 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5275 Normally you should be using @command{load_image} or GDB load. However, for
5276 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
5277 host), storing the image in memory and uploading the image to the target
5278 can be a way to upload e.g. multiple debug sessions when the binary does not change.
5279 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
5280 memory, i.e. does not affect target. This approach is also useful when profiling
5281 target programming performance as I/O and target programming can easily be profiled
5286 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5287 Load image from file @var{filename} to target memory at @var{address}.
5288 The file format may optionally be specified
5289 (@option{bin}, @option{ihex}, or @option{elf})
5292 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
5293 Displays image section sizes and addresses
5294 as if @var{filename} were loaded into target memory
5295 starting at @var{address} (defaults to zero).
5296 The file format may optionally be specified
5297 (@option{bin}, @option{ihex}, or @option{elf})
5300 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5301 Verify @var{filename} against target memory starting at @var{address}.
5302 The file format may optionally be specified
5303 (@option{bin}, @option{ihex}, or @option{elf})
5304 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
5308 @section Breakpoint and Watchpoint commands
5312 CPUs often make debug modules accessible through JTAG, with
5313 hardware support for a handful of code breakpoints and data
5315 In addition, CPUs almost always support software breakpoints.
5317 @deffn Command {bp} [address len [@option{hw}]]
5318 With no parameters, lists all active breakpoints.
5319 Else sets a breakpoint on code execution starting
5320 at @var{address} for @var{length} bytes.
5321 This is a software breakpoint, unless @option{hw} is specified
5322 in which case it will be a hardware breakpoint.
5324 (@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
5325 for similar mechanisms that do not consume hardware breakpoints.)
5328 @deffn Command {rbp} address
5329 Remove the breakpoint at @var{address}.
5332 @deffn Command {rwp} address
5333 Remove data watchpoint on @var{address}
5336 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
5337 With no parameters, lists all active watchpoints.
5338 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
5339 The watch point is an "access" watchpoint unless
5340 the @option{r} or @option{w} parameter is provided,
5341 defining it as respectively a read or write watchpoint.
5342 If a @var{value} is provided, that value is used when determining if
5343 the watchpoint should trigger. The value may be first be masked
5344 using @var{mask} to mark ``don't care'' fields.
5347 @section Misc Commands
5350 @deffn Command {profile} seconds filename
5351 Profiling samples the CPU's program counter as quickly as possible,
5352 which is useful for non-intrusive stochastic profiling.
5353 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
5356 @deffn Command {version}
5357 Displays a string identifying the version of this OpenOCD server.
5360 @deffn Command {virt2phys} virtual_address
5361 Requests the current target to map the specified @var{virtual_address}
5362 to its corresponding physical address, and displays the result.
5365 @node Architecture and Core Commands
5366 @chapter Architecture and Core Commands
5367 @cindex Architecture Specific Commands
5368 @cindex Core Specific Commands
5370 Most CPUs have specialized JTAG operations to support debugging.
5371 OpenOCD packages most such operations in its standard command framework.
5372 Some of those operations don't fit well in that framework, so they are
5373 exposed here as architecture or implementation (core) specific commands.
5375 @anchor{ARM Hardware Tracing}
5376 @section ARM Hardware Tracing
5381 CPUs based on ARM cores may include standard tracing interfaces,
5382 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
5383 address and data bus trace records to a ``Trace Port''.
5387 Development-oriented boards will sometimes provide a high speed
5388 trace connector for collecting that data, when the particular CPU
5389 supports such an interface.
5390 (The standard connector is a 38-pin Mictor, with both JTAG
5391 and trace port support.)
5392 Those trace connectors are supported by higher end JTAG adapters
5393 and some logic analyzer modules; frequently those modules can
5394 buffer several megabytes of trace data.
5395 Configuring an ETM coupled to such an external trace port belongs
5396 in the board-specific configuration file.
5398 If the CPU doesn't provide an external interface, it probably
5399 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
5400 dedicated SRAM. 4KBytes is one common ETB size.
5401 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
5402 (target) configuration file, since it works the same on all boards.
5405 ETM support in OpenOCD doesn't seem to be widely used yet.
5408 ETM support may be buggy, and at least some @command{etm config}
5409 parameters should be detected by asking the ETM for them.
5411 ETM trigger events could also implement a kind of complex
5412 hardware breakpoint, much more powerful than the simple
5413 watchpoint hardware exported by EmbeddedICE modules.
5414 @emph{Such breakpoints can be triggered even when using the
5415 dummy trace port driver}.
5417 It seems like a GDB hookup should be possible,
5418 as well as tracing only during specific states
5419 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
5421 There should be GUI tools to manipulate saved trace data and help
5422 analyse it in conjunction with the source code.
5423 It's unclear how much of a common interface is shared
5424 with the current XScale trace support, or should be
5425 shared with eventual Nexus-style trace module support.
5427 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
5428 for ETM modules is available. The code should be able to
5429 work with some newer cores; but not all of them support
5430 this original style of JTAG access.
5433 @subsection ETM Configuration
5434 ETM setup is coupled with the trace port driver configuration.
5436 @deffn {Config Command} {etm config} target width mode clocking driver
5437 Declares the ETM associated with @var{target}, and associates it
5438 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
5440 Several of the parameters must reflect the trace port capabilities,
5441 which are a function of silicon capabilties (exposed later
5442 using @command{etm info}) and of what hardware is connected to
5443 that port (such as an external pod, or ETB).
5444 The @var{width} must be either 4, 8, or 16,
5445 except with ETMv3.0 and newer modules which may also
5446 support 1, 2, 24, 32, 48, and 64 bit widths.
5447 (With those versions, @command{etm info} also shows whether
5448 the selected port width and mode are supported.)
5450 The @var{mode} must be @option{normal}, @option{multiplexed},
5451 or @option{demultiplexed}.
5452 The @var{clocking} must be @option{half} or @option{full}.
5455 With ETMv3.0 and newer, the bits set with the @var{mode} and
5456 @var{clocking} parameters both control the mode.
5457 This modified mode does not map to the values supported by
5458 previous ETM modules, so this syntax is subject to change.
5462 You can see the ETM registers using the @command{reg} command.
5463 Not all possible registers are present in every ETM.
5464 Most of the registers are write-only, and are used to configure
5465 what CPU activities are traced.
5469 @deffn Command {etm info}
5470 Displays information about the current target's ETM.
5471 This includes resource counts from the @code{ETM_CONFIG} register,
5472 as well as silicon capabilities (except on rather old modules).
5473 from the @code{ETM_SYS_CONFIG} register.
5476 @deffn Command {etm status}
5477 Displays status of the current target's ETM and trace port driver:
5478 is the ETM idle, or is it collecting data?
5479 Did trace data overflow?
5483 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
5484 Displays what data that ETM will collect.
5485 If arguments are provided, first configures that data.
5486 When the configuration changes, tracing is stopped
5487 and any buffered trace data is invalidated.
5490 @item @var{type} ... describing how data accesses are traced,
5491 when they pass any ViewData filtering that that was set up.
5493 @option{none} (save nothing),
5494 @option{data} (save data),
5495 @option{address} (save addresses),
5496 @option{all} (save data and addresses)
5497 @item @var{context_id_bits} ... 0, 8, 16, or 32
5498 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
5499 cycle-accurate instruction tracing.
5500 Before ETMv3, enabling this causes much extra data to be recorded.
5501 @item @var{branch_output} ... @option{enable} or @option{disable}.
5502 Disable this unless you need to try reconstructing the instruction
5503 trace stream without an image of the code.
5507 @deffn Command {etm trigger_percent} [percent]
5508 This displays, or optionally changes, the trace port driver's
5509 behavior after the ETM's configured @emph{trigger} event fires.
5510 It controls how much more trace data is saved after the (single)
5511 trace trigger becomes active.
5514 @item The default corresponds to @emph{trace around} usage,
5515 recording 50 percent data before the event and the rest
5517 @item The minimum value of @var{percent} is 2 percent,
5518 recording almost exclusively data before the trigger.
5519 Such extreme @emph{trace before} usage can help figure out
5520 what caused that event to happen.
5521 @item The maximum value of @var{percent} is 100 percent,
5522 recording data almost exclusively after the event.
5523 This extreme @emph{trace after} usage might help sort out
5524 how the event caused trouble.
5526 @c REVISIT allow "break" too -- enter debug mode.
5529 @subsection ETM Trace Operation
5531 After setting up the ETM, you can use it to collect data.
5532 That data can be exported to files for later analysis.
5533 It can also be parsed with OpenOCD, for basic sanity checking.
5535 To configure what is being traced, you will need to write
5536 various trace registers using @command{reg ETM_*} commands.
5537 For the definitions of these registers, read ARM publication
5538 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
5539 Be aware that most of the relevant registers are write-only,
5540 and that ETM resources are limited. There are only a handful
5541 of address comparators, data comparators, counters, and so on.
5543 Examples of scenarios you might arrange to trace include:
5546 @item Code flow within a function, @emph{excluding} subroutines
5547 it calls. Use address range comparators to enable tracing
5548 for instruction access within that function's body.
5549 @item Code flow within a function, @emph{including} subroutines
5550 it calls. Use the sequencer and address comparators to activate
5551 tracing on an ``entered function'' state, then deactivate it by
5552 exiting that state when the function's exit code is invoked.
5553 @item Code flow starting at the fifth invocation of a function,
5554 combining one of the above models with a counter.
5555 @item CPU data accesses to the registers for a particular device,
5556 using address range comparators and the ViewData logic.
5557 @item Such data accesses only during IRQ handling, combining the above
5558 model with sequencer triggers which on entry and exit to the IRQ handler.
5559 @item @emph{... more}
5562 At this writing, September 2009, there are no Tcl utility
5563 procedures to help set up any common tracing scenarios.
5565 @deffn Command {etm analyze}
5566 Reads trace data into memory, if it wasn't already present.
5567 Decodes and prints the data that was collected.
5570 @deffn Command {etm dump} filename
5571 Stores the captured trace data in @file{filename}.
5574 @deffn Command {etm image} filename [base_address] [type]
5575 Opens an image file.
5578 @deffn Command {etm load} filename
5579 Loads captured trace data from @file{filename}.
5582 @deffn Command {etm start}
5583 Starts trace data collection.
5586 @deffn Command {etm stop}
5587 Stops trace data collection.
5590 @anchor{Trace Port Drivers}
5591 @subsection Trace Port Drivers
5593 To use an ETM trace port it must be associated with a driver.
5595 @deffn {Trace Port Driver} dummy
5596 Use the @option{dummy} driver if you are configuring an ETM that's
5597 not connected to anything (on-chip ETB or off-chip trace connector).
5598 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
5599 any trace data collection.}
5600 @deffn {Config Command} {etm_dummy config} target
5601 Associates the ETM for @var{target} with a dummy driver.
5605 @deffn {Trace Port Driver} etb
5606 Use the @option{etb} driver if you are configuring an ETM
5607 to use on-chip ETB memory.
5608 @deffn {Config Command} {etb config} target etb_tap
5609 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
5610 You can see the ETB registers using the @command{reg} command.
5614 @deffn {Trace Port Driver} oocd_trace
5615 This driver isn't available unless OpenOCD was explicitly configured
5616 with the @option{--enable-oocd_trace} option. You probably don't want
5617 to configure it unless you've built the appropriate prototype hardware;
5618 it's @emph{proof-of-concept} software.
5620 Use the @option{oocd_trace} driver if you are configuring an ETM that's
5621 connected to an off-chip trace connector.
5623 @deffn {Config Command} {oocd_trace config} target tty
5624 Associates the ETM for @var{target} with a trace driver which
5625 collects data through the serial port @var{tty}.
5628 @deffn Command {oocd_trace resync}
5629 Re-synchronizes with the capture clock.
5632 @deffn Command {oocd_trace status}
5633 Reports whether the capture clock is locked or not.
5638 @section Generic ARM
5641 These commands should be available on all ARM processors.
5642 They are available in addition to other core-specific
5643 commands that may be available.
5645 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
5646 Displays the core_state, optionally changing it to process
5647 either @option{arm} or @option{thumb} instructions.
5648 The target may later be resumed in the currently set core_state.
5649 (Processors may also support the Jazelle state, but
5650 that is not currently supported in OpenOCD.)
5653 @deffn Command {arm disassemble} address [count [@option{thumb}]]
5655 Disassembles @var{count} instructions starting at @var{address}.
5656 If @var{count} is not specified, a single instruction is disassembled.
5657 If @option{thumb} is specified, or the low bit of the address is set,
5658 Thumb2 (mixed 16/32-bit) instructions are used;
5659 else ARM (32-bit) instructions are used.
5660 (Processors may also support the Jazelle state, but
5661 those instructions are not currently understood by OpenOCD.)
5663 Note that all Thumb instructions are Thumb2 instructions,
5664 so older processors (without Thumb2 support) will still
5665 see correct disassembly of Thumb code.
5666 Also, ThumbEE opcodes are the same as Thumb2,
5667 with a handful of exceptions.
5668 ThumbEE disassembly currently has no explicit support.
5671 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
5672 Write @var{value} to a coprocessor @var{pX} register
5673 passing parameters @var{CRn},
5674 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5675 and using the MCR instruction.
5676 (Parameter sequence matches the ARM instruction, but omits
5680 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
5681 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5682 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5683 and the MRC instruction.
5684 Returns the result so it can be manipulated by Jim scripts.
5685 (Parameter sequence matches the ARM instruction, but omits
5689 @deffn Command {arm reg}
5690 Display a table of all banked core registers, fetching the current value from every
5691 core mode if necessary.
5694 @section ARMv4 and ARMv5 Architecture
5698 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
5699 and introduced core parts of the instruction set in use today.
5700 That includes the Thumb instruction set, introduced in the ARMv4T
5703 @subsection ARM7 and ARM9 specific commands
5707 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5708 ARM9TDMI, ARM920T or ARM926EJ-S.
5709 They are available in addition to the ARM commands,
5710 and any other core-specific commands that may be available.
5712 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5713 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5714 instead of breakpoints. This should be
5715 safe for all but ARM7TDMI--S cores (like Philips LPC).
5716 This feature is enabled by default on most ARM9 cores,
5717 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5720 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5722 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5723 amounts of memory. DCC downloads offer a huge speed increase, but might be
5724 unsafe, especially with targets running at very low speeds. This command was introduced
5725 with OpenOCD rev. 60, and requires a few bytes of working area.
5728 @anchor{arm7_9 fast_memory_access}
5729 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5730 Enable or disable memory writes and reads that don't check completion of
5731 the operation. This provides a huge speed increase, especially with USB JTAG
5732 cables (FT2232), but might be unsafe if used with targets running at very low
5733 speeds, like the 32kHz startup clock of an AT91RM9200.
5736 @deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
5737 @cindex ARM semihosting
5738 Display status of semihosting, after optionally changing that status.
5740 Semihosting allows for code executing on an ARM target to use the
5741 I/O facilities on the host computer i.e. the system where OpenOCD
5742 is running. The target application must be linked against a library
5743 implementing the ARM semihosting convention that forwards operation
5744 requests by using a special SVC instruction that is trapped at the
5745 Supervisor Call vector by OpenOCD.
5748 @subsection ARM720T specific commands
5751 These commands are available to ARM720T based CPUs,
5752 which are implementations of the ARMv4T architecture
5753 based on the ARM7TDMI-S integer core.
5754 They are available in addition to the ARM and ARM7/ARM9 commands.
5756 @deffn Command {arm720t cp15} regnum [value]
5757 Display cp15 register @var{regnum};
5758 else if a @var{value} is provided, that value is written to that register.
5761 @subsection ARM9 specific commands
5764 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5766 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5768 @c 9-june-2009: tried this on arm920t, it didn't work.
5769 @c no-params always lists nothing caught, and that's how it acts.
5770 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
5771 @c versions have different rules about when they commit writes.
5773 @anchor{arm9 vector_catch}
5774 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
5775 @cindex vector_catch
5776 Vector Catch hardware provides a sort of dedicated breakpoint
5777 for hardware events such as reset, interrupt, and abort.
5778 You can use this to conserve normal breakpoint resources,
5779 so long as you're not concerned with code that branches directly
5780 to those hardware vectors.
5782 This always finishes by listing the current configuration.
5783 If parameters are provided, it first reconfigures the
5784 vector catch hardware to intercept
5785 @option{all} of the hardware vectors,
5786 @option{none} of them,
5787 or a list with one or more of the following:
5788 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
5789 @option{irq} @option{fiq}.
5792 @subsection ARM920T specific commands
5795 These commands are available to ARM920T based CPUs,
5796 which are implementations of the ARMv4T architecture
5797 built using the ARM9TDMI integer core.
5798 They are available in addition to the ARM, ARM7/ARM9,
5801 @deffn Command {arm920t cache_info}
5802 Print information about the caches found. This allows to see whether your target
5803 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5806 @deffn Command {arm920t cp15} regnum [value]
5807 Display cp15 register @var{regnum};
5808 else if a @var{value} is provided, that value is written to that register.
5811 @deffn Command {arm920t cp15i} opcode [value [address]]
5812 Interpreted access using cp15 @var{opcode}.
5813 If no @var{value} is provided, the result is displayed.
5814 Else if that value is written using the specified @var{address},
5815 or using zero if no other address is not provided.
5818 @deffn Command {arm920t read_cache} filename
5819 Dump the content of ICache and DCache to a file named @file{filename}.
5822 @deffn Command {arm920t read_mmu} filename
5823 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5826 @subsection ARM926ej-s specific commands
5829 These commands are available to ARM926ej-s based CPUs,
5830 which are implementations of the ARMv5TEJ architecture
5831 based on the ARM9EJ-S integer core.
5832 They are available in addition to the ARM, ARM7/ARM9,
5835 The Feroceon cores also support these commands, although
5836 they are not built from ARM926ej-s designs.
5838 @deffn Command {arm926ejs cache_info}
5839 Print information about the caches found.
5842 @subsection ARM966E specific commands
5845 These commands are available to ARM966 based CPUs,
5846 which are implementations of the ARMv5TE architecture.
5847 They are available in addition to the ARM, ARM7/ARM9,
5850 @deffn Command {arm966e cp15} regnum [value]
5851 Display cp15 register @var{regnum};
5852 else if a @var{value} is provided, that value is written to that register.
5855 @subsection XScale specific commands
5858 Some notes about the debug implementation on the XScale CPUs:
5860 The XScale CPU provides a special debug-only mini-instruction cache
5861 (mini-IC) in which exception vectors and target-resident debug handler
5862 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5863 must point vector 0 (the reset vector) to the entry of the debug
5864 handler. However, this means that the complete first cacheline in the
5865 mini-IC is marked valid, which makes the CPU fetch all exception
5866 handlers from the mini-IC, ignoring the code in RAM.
5868 OpenOCD currently does not sync the mini-IC entries with the RAM
5869 contents (which would fail anyway while the target is running), so
5870 the user must provide appropriate values using the @code{xscale
5871 vector_table} command.
5873 It is recommended to place a pc-relative indirect branch in the vector
5874 table, and put the branch destination somewhere in memory. Doing so
5875 makes sure the code in the vector table stays constant regardless of
5876 code layout in memory:
5879 ldr pc,[pc,#0x100-8]
5880 ldr pc,[pc,#0x100-8]
5881 ldr pc,[pc,#0x100-8]
5882 ldr pc,[pc,#0x100-8]
5883 ldr pc,[pc,#0x100-8]
5884 ldr pc,[pc,#0x100-8]
5885 ldr pc,[pc,#0x100-8]
5886 ldr pc,[pc,#0x100-8]
5888 .long real_reset_vector
5889 .long real_ui_handler
5890 .long real_swi_handler
5892 .long real_data_abort
5893 .long 0 /* unused */
5894 .long real_irq_handler
5895 .long real_fiq_handler
5898 The debug handler must be placed somewhere in the address space using
5899 the @code{xscale debug_handler} command. The allowed locations for the
5900 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5901 0xfffff800). The default value is 0xfe000800.
5904 These commands are available to XScale based CPUs,
5905 which are implementations of the ARMv5TE architecture.
5907 @deffn Command {xscale analyze_trace}
5908 Displays the contents of the trace buffer.
5911 @deffn Command {xscale cache_clean_address} address
5912 Changes the address used when cleaning the data cache.
5915 @deffn Command {xscale cache_info}
5916 Displays information about the CPU caches.
5919 @deffn Command {xscale cp15} regnum [value]
5920 Display cp15 register @var{regnum};
5921 else if a @var{value} is provided, that value is written to that register.
5924 @deffn Command {xscale debug_handler} target address
5925 Changes the address used for the specified target's debug handler.
5928 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5929 Enables or disable the CPU's data cache.
5932 @deffn Command {xscale dump_trace} filename
5933 Dumps the raw contents of the trace buffer to @file{filename}.
5936 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5937 Enables or disable the CPU's instruction cache.
5940 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5941 Enables or disable the CPU's memory management unit.
5944 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5945 Enables or disables the trace buffer,
5946 and controls how it is emptied.
5949 @deffn Command {xscale trace_image} filename [offset [type]]
5950 Opens a trace image from @file{filename}, optionally rebasing
5951 its segment addresses by @var{offset}.
5952 The image @var{type} may be one of
5953 @option{bin} (binary), @option{ihex} (Intel hex),
5954 @option{elf} (ELF file), @option{s19} (Motorola s19),
5955 @option{mem}, or @option{builder}.
5958 @anchor{xscale vector_catch}
5959 @deffn Command {xscale vector_catch} [mask]
5960 @cindex vector_catch
5961 Display a bitmask showing the hardware vectors to catch.
5962 If the optional parameter is provided, first set the bitmask to that value.
5964 The mask bits correspond with bit 16..23 in the DCSR:
5967 0x02 Trap Undefined Instructions
5968 0x04 Trap Software Interrupt
5969 0x08 Trap Prefetch Abort
5970 0x10 Trap Data Abort
5977 @anchor{xscale vector_table}
5978 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5979 @cindex vector_table
5981 Set an entry in the mini-IC vector table. There are two tables: one for
5982 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5983 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5984 points to the debug handler entry and can not be overwritten.
5985 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5987 Without arguments, the current settings are displayed.
5991 @section ARMv6 Architecture
5994 @subsection ARM11 specific commands
5997 @deffn Command {arm11 memwrite burst} [value]
5998 Displays the value of the memwrite burst-enable flag,
5999 which is enabled by default. Burst writes are only used
6000 for memory writes larger than 1 word. Single word writes
6001 are likely to be from reset init scripts and those writes
6002 are often to non-memory locations which could easily have
6003 many wait states, which could easily break burst writes.
6004 If @var{value} is defined, first assigns that.
6007 @deffn Command {arm11 memwrite error_fatal} [value]
6008 Displays the value of the memwrite error_fatal flag,
6009 which is enabled by default.
6010 If @var{value} is defined, first assigns that.
6013 @deffn Command {arm11 step_irq_enable} [value]
6014 Displays the value of the flag controlling whether
6015 IRQs are enabled during single stepping;
6016 they are disabled by default.
6017 If @var{value} is defined, first assigns that.
6020 @deffn Command {arm11 vcr} [value]
6021 @cindex vector_catch
6022 Displays the value of the @emph{Vector Catch Register (VCR)},
6023 coprocessor 14 register 7.
6024 If @var{value} is defined, first assigns that.
6026 Vector Catch hardware provides dedicated breakpoints
6027 for certain hardware events.
6028 The specific bit values are core-specific (as in fact is using
6029 coprocessor 14 register 7 itself) but all current ARM11
6030 cores @emph{except the ARM1176} use the same six bits.
6033 @section ARMv7 Architecture
6036 @subsection ARMv7 Debug Access Port (DAP) specific commands
6037 @cindex Debug Access Port
6039 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
6040 included on Cortex-M3 and Cortex-A8 systems.
6041 They are available in addition to other core-specific commands that may be available.
6043 @deffn Command {dap info} [num]
6044 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
6047 @deffn Command {dap apsel} [num]
6048 Select AP @var{num}, defaulting to 0.
6051 @deffn Command {dap apid} [num]
6052 Displays id register from AP @var{num},
6053 defaulting to the currently selected AP.
6056 @deffn Command {dap baseaddr} [num]
6057 Displays debug base address from AP @var{num},
6058 defaulting to the currently selected AP.
6061 @deffn Command {dap memaccess} [value]
6062 Displays the number of extra tck for mem-ap memory bus access [0-255].
6063 If @var{value} is defined, first assigns that.
6066 @subsection Cortex-M3 specific commands
6069 @deffn Command {cortex_m3 disassemble} address [count]
6071 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
6072 If @var{count} is not specified, a single instruction is disassembled.
6075 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
6076 Control masking (disabling) interrupts during target step/resume.
6079 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
6080 @cindex vector_catch
6081 Vector Catch hardware provides dedicated breakpoints
6082 for certain hardware events.
6084 Parameters request interception of
6085 @option{all} of these hardware event vectors,
6086 @option{none} of them,
6087 or one or more of the following:
6088 @option{hard_err} for a HardFault exception;
6089 @option{mm_err} for a MemManage exception;
6090 @option{bus_err} for a BusFault exception;
6093 @option{chk_err}, or
6094 @option{nocp_err} for various UsageFault exceptions; or
6096 If NVIC setup code does not enable them,
6097 MemManage, BusFault, and UsageFault exceptions
6098 are mapped to HardFault.
6099 UsageFault checks for
6100 divide-by-zero and unaligned access
6101 must also be explicitly enabled.
6103 This finishes by listing the current vector catch configuration.
6106 @anchor{Software Debug Messages and Tracing}
6107 @section Software Debug Messages and Tracing
6108 @cindex Linux-ARM DCC support
6112 OpenOCD can process certain requests from target software, when
6113 the target uses appropriate libraries.
6114 The most powerful mechanism is semihosting, but there is also
6115 a lighter weight mechanism using only the DCC channel.
6117 Currently @command{target_request debugmsgs}
6118 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
6119 These messages are received as part of target polling, so
6120 you need to have @command{poll on} active to receive them.
6121 They are intrusive in that they will affect program execution
6122 times. If that is a problem, @pxref{ARM Hardware Tracing}.
6124 See @file{libdcc} in the contrib dir for more details.
6125 In addition to sending strings, characters, and
6126 arrays of various size integers from the target,
6127 @file{libdcc} also exports a software trace point mechanism.
6128 The target being debugged may
6129 issue trace messages which include a 24-bit @dfn{trace point} number.
6130 Trace point support includes two distinct mechanisms,
6131 each supported by a command:
6134 @item @emph{History} ... A circular buffer of trace points
6135 can be set up, and then displayed at any time.
6136 This tracks where code has been, which can be invaluable in
6137 finding out how some fault was triggered.
6139 The buffer may overflow, since it collects records continuously.
6140 It may be useful to use some of the 24 bits to represent a
6141 particular event, and other bits to hold data.
6143 @item @emph{Counting} ... An array of counters can be set up,
6144 and then displayed at any time.
6145 This can help establish code coverage and identify hot spots.
6147 The array of counters is directly indexed by the trace point
6148 number, so trace points with higher numbers are not counted.
6151 Linux-ARM kernels have a ``Kernel low-level debugging
6152 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
6153 depends on CONFIG_DEBUG_LL) which uses this mechanism to
6154 deliver messages before a serial console can be activated.
6155 This is not the same format used by @file{libdcc}.
6156 Other software, such as the U-Boot boot loader, sometimes
6157 does the same thing.
6159 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
6160 Displays current handling of target DCC message requests.
6161 These messages may be sent to the debugger while the target is running.
6162 The optional @option{enable} and @option{charmsg} parameters
6163 both enable the messages, while @option{disable} disables them.
6165 With @option{charmsg} the DCC words each contain one character,
6166 as used by Linux with CONFIG_DEBUG_ICEDCC;
6167 otherwise the libdcc format is used.
6170 @deffn Command {trace history} [@option{clear}|count]
6171 With no parameter, displays all the trace points that have triggered
6172 in the order they triggered.
6173 With the parameter @option{clear}, erases all current trace history records.
6174 With a @var{count} parameter, allocates space for that many
6178 @deffn Command {trace point} [@option{clear}|identifier]
6179 With no parameter, displays all trace point identifiers and how many times
6180 they have been triggered.
6181 With the parameter @option{clear}, erases all current trace point counters.
6182 With a numeric @var{identifier} parameter, creates a new a trace point counter
6183 and associates it with that identifier.
6185 @emph{Important:} The identifier and the trace point number
6186 are not related except by this command.
6187 These trace point numbers always start at zero (from server startup,
6188 or after @command{trace point clear}) and count up from there.
6193 @chapter JTAG Commands
6194 @cindex JTAG Commands
6195 Most general purpose JTAG commands have been presented earlier.
6196 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
6197 Lower level JTAG commands, as presented here,
6198 may be needed to work with targets which require special
6199 attention during operations such as reset or initialization.
6201 To use these commands you will need to understand some
6202 of the basics of JTAG, including:
6205 @item A JTAG scan chain consists of a sequence of individual TAP
6206 devices such as a CPUs.
6207 @item Control operations involve moving each TAP through the same
6208 standard state machine (in parallel)
6209 using their shared TMS and clock signals.
6210 @item Data transfer involves shifting data through the chain of
6211 instruction or data registers of each TAP, writing new register values
6212 while the reading previous ones.
6213 @item Data register sizes are a function of the instruction active in
6214 a given TAP, while instruction register sizes are fixed for each TAP.
6215 All TAPs support a BYPASS instruction with a single bit data register.
6216 @item The way OpenOCD differentiates between TAP devices is by
6217 shifting different instructions into (and out of) their instruction
6221 @section Low Level JTAG Commands
6223 These commands are used by developers who need to access
6224 JTAG instruction or data registers, possibly controlling
6225 the order of TAP state transitions.
6226 If you're not debugging OpenOCD internals, or bringing up a
6227 new JTAG adapter or a new type of TAP device (like a CPU or
6228 JTAG router), you probably won't need to use these commands.
6230 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
6231 Loads the data register of @var{tap} with a series of bit fields
6232 that specify the entire register.
6233 Each field is @var{numbits} bits long with
6234 a numeric @var{value} (hexadecimal encouraged).
6235 The return value holds the original value of each
6238 For example, a 38 bit number might be specified as one
6239 field of 32 bits then one of 6 bits.
6240 @emph{For portability, never pass fields which are more
6241 than 32 bits long. Many OpenOCD implementations do not
6242 support 64-bit (or larger) integer values.}
6244 All TAPs other than @var{tap} must be in BYPASS mode.
6245 The single bit in their data registers does not matter.
6247 When @var{tap_state} is specified, the JTAG state machine is left
6249 For example @sc{drpause} might be specified, so that more
6250 instructions can be issued before re-entering the @sc{run/idle} state.
6251 If the end state is not specified, the @sc{run/idle} state is entered.
6254 OpenOCD does not record information about data register lengths,
6255 so @emph{it is important that you get the bit field lengths right}.
6256 Remember that different JTAG instructions refer to different
6257 data registers, which may have different lengths.
6258 Moreover, those lengths may not be fixed;
6259 the SCAN_N instruction can change the length of
6260 the register accessed by the INTEST instruction
6261 (by connecting a different scan chain).
6265 @deffn Command {flush_count}
6266 Returns the number of times the JTAG queue has been flushed.
6267 This may be used for performance tuning.
6269 For example, flushing a queue over USB involves a
6270 minimum latency, often several milliseconds, which does
6271 not change with the amount of data which is written.
6272 You may be able to identify performance problems by finding
6273 tasks which waste bandwidth by flushing small transfers too often,
6274 instead of batching them into larger operations.
6277 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
6278 For each @var{tap} listed, loads the instruction register
6279 with its associated numeric @var{instruction}.
6280 (The number of bits in that instruction may be displayed
6281 using the @command{scan_chain} command.)
6282 For other TAPs, a BYPASS instruction is loaded.
6284 When @var{tap_state} is specified, the JTAG state machine is left
6286 For example @sc{irpause} might be specified, so the data register
6287 can be loaded before re-entering the @sc{run/idle} state.
6288 If the end state is not specified, the @sc{run/idle} state is entered.
6291 OpenOCD currently supports only a single field for instruction
6292 register values, unlike data register values.
6293 For TAPs where the instruction register length is more than 32 bits,
6294 portable scripts currently must issue only BYPASS instructions.
6298 @deffn Command {jtag_reset} trst srst
6299 Set values of reset signals.
6300 The @var{trst} and @var{srst} parameter values may be
6301 @option{0}, indicating that reset is inactive (pulled or driven high),
6302 or @option{1}, indicating it is active (pulled or driven low).
6303 The @command{reset_config} command should already have been used
6304 to configure how the board and JTAG adapter treat these two
6305 signals, and to say if either signal is even present.
6306 @xref{Reset Configuration}.
6308 Note that TRST is specially handled.
6309 It actually signifies JTAG's @sc{reset} state.
6310 So if the board doesn't support the optional TRST signal,
6311 or it doesn't support it along with the specified SRST value,
6312 JTAG reset is triggered with TMS and TCK signals
6313 instead of the TRST signal.
6314 And no matter how that JTAG reset is triggered, once
6315 the scan chain enters @sc{reset} with TRST inactive,
6316 TAP @code{post-reset} events are delivered to all TAPs
6317 with handlers for that event.
6320 @deffn Command {pathmove} start_state [next_state ...]
6321 Start by moving to @var{start_state}, which
6322 must be one of the @emph{stable} states.
6323 Unless it is the only state given, this will often be the
6324 current state, so that no TCK transitions are needed.
6325 Then, in a series of single state transitions
6326 (conforming to the JTAG state machine) shift to
6327 each @var{next_state} in sequence, one per TCK cycle.
6328 The final state must also be stable.
6331 @deffn Command {runtest} @var{num_cycles}
6332 Move to the @sc{run/idle} state, and execute at least
6333 @var{num_cycles} of the JTAG clock (TCK).
6334 Instructions often need some time
6335 to execute before they take effect.
6338 @c tms_sequence (short|long)
6339 @c ... temporary, debug-only, other than USBprog bug workaround...
6341 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
6342 Verify values captured during @sc{ircapture} and returned
6343 during IR scans. Default is enabled, but this can be
6344 overridden by @command{verify_jtag}.
6345 This flag is ignored when validating JTAG chain configuration.
6348 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
6349 Enables verification of DR and IR scans, to help detect
6350 programming errors. For IR scans, @command{verify_ircapture}
6351 must also be enabled.
6355 @section TAP state names
6356 @cindex TAP state names
6358 The @var{tap_state} names used by OpenOCD in the @command{drscan},
6359 @command{irscan}, and @command{pathmove} commands are the same
6360 as those used in SVF boundary scan documents, except that
6361 SVF uses @sc{idle} instead of @sc{run/idle}.
6364 @item @b{RESET} ... @emph{stable} (with TMS high);
6365 acts as if TRST were pulsed
6366 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
6369 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
6370 through the data register
6372 @item @b{DRPAUSE} ... @emph{stable}; data register ready
6373 for update or more shifting
6378 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
6379 through the instruction register
6381 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
6382 for update or more shifting
6387 Note that only six of those states are fully ``stable'' in the
6388 face of TMS fixed (low except for @sc{reset})
6389 and a free-running JTAG clock. For all the
6390 others, the next TCK transition changes to a new state.
6393 @item From @sc{drshift} and @sc{irshift}, clock transitions will
6394 produce side effects by changing register contents. The values
6395 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
6396 may not be as expected.
6397 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
6398 choices after @command{drscan} or @command{irscan} commands,
6399 since they are free of JTAG side effects.
6400 @item @sc{run/idle} may have side effects that appear at non-JTAG
6401 levels, such as advancing the ARM9E-S instruction pipeline.
6402 Consult the documentation for the TAP(s) you are working with.
6405 @node Boundary Scan Commands
6406 @chapter Boundary Scan Commands
6408 One of the original purposes of JTAG was to support
6409 boundary scan based hardware testing.
6410 Although its primary focus is to support On-Chip Debugging,
6411 OpenOCD also includes some boundary scan commands.
6413 @section SVF: Serial Vector Format
6414 @cindex Serial Vector Format
6417 The Serial Vector Format, better known as @dfn{SVF}, is a
6418 way to represent JTAG test patterns in text files.
6419 OpenOCD supports running such test files.
6421 @deffn Command {svf} filename [@option{quiet}]
6422 This issues a JTAG reset (Test-Logic-Reset) and then
6423 runs the SVF script from @file{filename}.
6424 Unless the @option{quiet} option is specified,
6425 each command is logged before it is executed.
6428 @section XSVF: Xilinx Serial Vector Format
6429 @cindex Xilinx Serial Vector Format
6432 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
6433 binary representation of SVF which is optimized for use with
6435 OpenOCD supports running such test files.
6437 @quotation Important
6438 Not all XSVF commands are supported.
6441 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
6442 This issues a JTAG reset (Test-Logic-Reset) and then
6443 runs the XSVF script from @file{filename}.
6444 When a @var{tapname} is specified, the commands are directed at
6446 When @option{virt2} is specified, the @sc{xruntest} command counts
6447 are interpreted as TCK cycles instead of microseconds.
6448 Unless the @option{quiet} option is specified,
6449 messages are logged for comments and some retries.
6452 The OpenOCD sources also include two utility scripts
6453 for working with XSVF; they are not currently installed
6454 after building the software.
6455 You may find them useful:
6458 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
6459 syntax understood by the @command{xsvf} command; see notes below.
6460 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
6461 understands the OpenOCD extensions.
6464 The input format accepts a handful of non-standard extensions.
6465 These include three opcodes corresponding to SVF extensions
6466 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
6467 two opcodes supporting a more accurate translation of SVF
6468 (XTRST, XWAITSTATE).
6469 If @emph{xsvfdump} shows a file is using those opcodes, it
6470 probably will not be usable with other XSVF tools.
6476 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
6477 be used to access files on PCs (either the developer's PC or some other PC).
6479 The way this works on the ZY1000 is to prefix a filename by
6480 "/tftp/ip/" and append the TFTP path on the TFTP
6481 server (tftpd). For example,
6484 load_image /tftp/10.0.0.96/c:\temp\abc.elf
6487 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
6488 if the file was hosted on the embedded host.
6490 In order to achieve decent performance, you must choose a TFTP server
6491 that supports a packet size bigger than the default packet size (512 bytes). There
6492 are numerous TFTP servers out there (free and commercial) and you will have to do
6493 a bit of googling to find something that fits your requirements.
6495 @node GDB and OpenOCD
6496 @chapter GDB and OpenOCD
6498 OpenOCD complies with the remote gdbserver protocol, and as such can be used
6499 to debug remote targets.
6501 @anchor{Connecting to GDB}
6502 @section Connecting to GDB
6503 @cindex Connecting to GDB
6504 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
6505 instance GDB 6.3 has a known bug that produces bogus memory access
6506 errors, which has since been fixed: look up 1836 in
6507 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
6509 OpenOCD can communicate with GDB in two ways:
6513 A socket (TCP/IP) connection is typically started as follows:
6515 target remote localhost:3333
6517 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
6519 A pipe connection is typically started as follows:
6521 target remote | openocd --pipe
6523 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
6524 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
6528 To list the available OpenOCD commands type @command{monitor help} on the
6531 OpenOCD supports the gdb @option{qSupported} packet, this enables information
6532 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
6533 packet size and the device's memory map.
6535 Previous versions of OpenOCD required the following GDB options to increase
6536 the packet size and speed up GDB communication:
6538 set remote memory-write-packet-size 1024
6539 set remote memory-write-packet-size fixed
6540 set remote memory-read-packet-size 1024
6541 set remote memory-read-packet-size fixed
6543 This is now handled in the @option{qSupported} PacketSize and should not be required.
6545 @section Programming using GDB
6546 @cindex Programming using GDB
6548 By default the target memory map is sent to GDB. This can be disabled by
6549 the following OpenOCD configuration option:
6551 gdb_memory_map disable
6553 For this to function correctly a valid flash configuration must also be set
6554 in OpenOCD. For faster performance you should also configure a valid
6557 Informing GDB of the memory map of the target will enable GDB to protect any
6558 flash areas of the target and use hardware breakpoints by default. This means
6559 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
6560 using a memory map. @xref{gdb_breakpoint_override}.
6562 To view the configured memory map in GDB, use the GDB command @option{info mem}
6563 All other unassigned addresses within GDB are treated as RAM.
6565 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
6566 This can be changed to the old behaviour by using the following GDB command
6568 set mem inaccessible-by-default off
6571 If @command{gdb_flash_program enable} is also used, GDB will be able to
6572 program any flash memory using the vFlash interface.
6574 GDB will look at the target memory map when a load command is given, if any
6575 areas to be programmed lie within the target flash area the vFlash packets
6578 If the target needs configuring before GDB programming, an event
6579 script can be executed:
6581 $_TARGETNAME configure -event EVENTNAME BODY
6584 To verify any flash programming the GDB command @option{compare-sections}
6587 @node Tcl Scripting API
6588 @chapter Tcl Scripting API
6589 @cindex Tcl Scripting API
6593 The commands are stateless. E.g. the telnet command line has a concept
6594 of currently active target, the Tcl API proc's take this sort of state
6595 information as an argument to each proc.
6597 There are three main types of return values: single value, name value
6598 pair list and lists.
6600 Name value pair. The proc 'foo' below returns a name/value pair
6606 > set foo(you) Oyvind
6607 > set foo(mouse) Micky
6608 > set foo(duck) Donald
6616 me Duane you Oyvind mouse Micky duck Donald
6618 Thus, to get the names of the associative array is easy:
6620 foreach { name value } [set foo] {
6621 puts "Name: $name, Value: $value"
6625 Lists returned must be relatively small. Otherwise a range
6626 should be passed in to the proc in question.
6628 @section Internal low-level Commands
6630 By low-level, the intent is a human would not directly use these commands.
6632 Low-level commands are (should be) prefixed with "ocd_", e.g.
6633 @command{ocd_flash_banks}
6634 is the low level API upon which @command{flash banks} is implemented.
6637 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6639 Read memory and return as a Tcl array for script processing
6640 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6642 Convert a Tcl array to memory locations and write the values
6643 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6645 Return information about the flash banks
6648 OpenOCD commands can consist of two words, e.g. "flash banks". The
6649 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6650 called "flash_banks".
6652 @section OpenOCD specific Global Variables
6654 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6655 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
6656 holds one of the following values:
6659 @item @b{winxx} Built using Microsoft Visual Studio
6660 @item @b{linux} Linux is the underlying operating sytem
6661 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6662 @item @b{cygwin} Running under Cygwin
6663 @item @b{mingw32} Running under MingW32
6664 @item @b{other} Unknown, none of the above.
6667 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6670 We should add support for a variable like Tcl variable
6671 @code{tcl_platform(platform)}, it should be called
6672 @code{jim_platform} (because it
6673 is jim, not real tcl).
6681 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6683 @cindex adaptive clocking
6686 In digital circuit design it is often refered to as ``clock
6687 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6688 operating at some speed, your target is operating at another. The two
6689 clocks are not synchronised, they are ``asynchronous''
6691 In order for the two to work together they must be synchronised. Otherwise
6692 the two systems will get out of sync with each other and nothing will
6693 work. There are 2 basic options:
6696 Use a special circuit.
6698 One clock must be some multiple slower than the other.
6701 @b{Does this really matter?} For some chips and some situations, this
6702 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6703 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6704 program/enable the oscillators and eventually the main clock. It is in
6705 those critical times you must slow the JTAG clock to sometimes 1 to
6708 Imagine debugging a 500MHz ARM926 hand held battery powered device
6709 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6712 @b{Solution #1 - A special circuit}
6714 In order to make use of this, your JTAG dongle must support the RTCK
6715 feature. Not all dongles support this - keep reading!
6717 The RTCK signal often found in some ARM chips is used to help with
6718 this problem. ARM has a good description of the problem described at
6719 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6720 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6721 work? / how does adaptive clocking work?''.
6723 The nice thing about adaptive clocking is that ``battery powered hand
6724 held device example'' - the adaptiveness works perfectly all the
6725 time. One can set a break point or halt the system in the deep power
6726 down code, slow step out until the system speeds up.
6728 Note that adaptive clocking may also need to work at the board level,
6729 when a board-level scan chain has multiple chips.
6730 Parallel clock voting schemes are good way to implement this,
6731 both within and between chips, and can easily be implemented
6733 It's not difficult to have logic fan a module's input TCK signal out
6734 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6735 back with the right polarity before changing the output RTCK signal.
6736 Texas Instruments makes some clock voting logic available
6737 for free (with no support) in VHDL form; see
6738 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6740 @b{Solution #2 - Always works - but may be slower}
6742 Often this is a perfectly acceptable solution.
6744 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6745 the target clock speed. But what that ``magic division'' is varies
6746 depending on the chips on your board.
6747 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6748 ARM11 cores use an 8:1 division.
6749 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6751 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6753 You can still debug the 'low power' situations - you just need to
6754 manually adjust the clock speed at every step. While painful and
6755 tedious, it is not always practical.
6757 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6758 have a special debug mode in your application that does a ``high power
6759 sleep''. If you are careful - 98% of your problems can be debugged
6762 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6763 operation in your idle loops even if you don't otherwise change the CPU
6765 That operation gates the CPU clock, and thus the JTAG clock; which
6766 prevents JTAG access. One consequence is not being able to @command{halt}
6767 cores which are executing that @emph{wait for interrupt} operation.
6769 To set the JTAG frequency use the command:
6777 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6779 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6780 around Windows filenames.
6793 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6795 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6796 claims to come with all the necessary DLLs. When using Cygwin, try launching
6797 OpenOCD from the Cygwin shell.
6799 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6800 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6801 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6803 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6804 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6805 software breakpoints consume one of the two available hardware breakpoints.
6807 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6809 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6810 clock at the time you're programming the flash. If you've specified the crystal's
6811 frequency, make sure the PLL is disabled. If you've specified the full core speed
6812 (e.g. 60MHz), make sure the PLL is enabled.
6814 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6815 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6816 out while waiting for end of scan, rtck was disabled".
6818 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6819 settings in your PC BIOS (ECP, EPP, and different versions of those).
6821 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6822 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6823 memory read caused data abort".
6825 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6826 beyond the last valid frame. It might be possible to prevent this by setting up
6827 a proper "initial" stack frame, if you happen to know what exactly has to
6828 be done, feel free to add this here.
6830 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6831 stack before calling main(). What GDB is doing is ``climbing'' the run
6832 time stack by reading various values on the stack using the standard
6833 call frame for the target. GDB keeps going - until one of 2 things
6834 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6835 stackframes have been processed. By pushing zeros on the stack, GDB
6838 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6839 your C code, do the same - artifically push some zeros onto the stack,
6840 remember to pop them off when the ISR is done.
6842 @b{Also note:} If you have a multi-threaded operating system, they
6843 often do not @b{in the intrest of saving memory} waste these few
6847 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6848 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6850 This warning doesn't indicate any serious problem, as long as you don't want to
6851 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6852 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6853 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6854 independently. With this setup, it's not possible to halt the core right out of
6855 reset, everything else should work fine.
6857 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6858 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6859 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6860 quit with an error message. Is there a stability issue with OpenOCD?
6862 No, this is not a stability issue concerning OpenOCD. Most users have solved
6863 this issue by simply using a self-powered USB hub, which they connect their
6864 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6865 supply stable enough for the Amontec JTAGkey to be operated.
6867 @b{Laptops running on battery have this problem too...}
6869 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6870 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6871 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6872 What does that mean and what might be the reason for this?
6874 First of all, the reason might be the USB power supply. Try using a self-powered
6875 hub instead of a direct connection to your computer. Secondly, the error code 4
6876 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6877 chip ran into some sort of error - this points us to a USB problem.
6879 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6880 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6881 What does that mean and what might be the reason for this?
6883 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6884 has closed the connection to OpenOCD. This might be a GDB issue.
6886 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6887 are described, there is a parameter for specifying the clock frequency
6888 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6889 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6890 specified in kilohertz. However, I do have a quartz crystal of a
6891 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6892 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6895 No. The clock frequency specified here must be given as an integral number.
6896 However, this clock frequency is used by the In-Application-Programming (IAP)
6897 routines of the LPC2000 family only, which seems to be very tolerant concerning
6898 the given clock frequency, so a slight difference between the specified clock
6899 frequency and the actual clock frequency will not cause any trouble.
6901 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6903 Well, yes and no. Commands can be given in arbitrary order, yet the
6904 devices listed for the JTAG scan chain must be given in the right
6905 order (jtag newdevice), with the device closest to the TDO-Pin being
6906 listed first. In general, whenever objects of the same type exist
6907 which require an index number, then these objects must be given in the
6908 right order (jtag newtap, targets and flash banks - a target
6909 references a jtag newtap and a flash bank references a target).
6911 You can use the ``scan_chain'' command to verify and display the tap order.
6913 Also, some commands can't execute until after @command{init} has been
6914 processed. Such commands include @command{nand probe} and everything
6915 else that needs to write to controller registers, perhaps for setting
6916 up DRAM and loading it with code.
6918 @anchor{FAQ TAP Order}
6919 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6922 Yes; whenever you have more than one, you must declare them in
6923 the same order used by the hardware.
6925 Many newer devices have multiple JTAG TAPs. For example: ST
6926 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6927 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6928 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6929 connected to the boundary scan TAP, which then connects to the
6930 Cortex-M3 TAP, which then connects to the TDO pin.
6932 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6933 (2) The boundary scan TAP. If your board includes an additional JTAG
6934 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6935 place it before or after the STM32 chip in the chain. For example:
6938 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6939 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6940 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6941 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6942 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6945 The ``jtag device'' commands would thus be in the order shown below. Note:
6948 @item jtag newtap Xilinx tap -irlen ...
6949 @item jtag newtap stm32 cpu -irlen ...
6950 @item jtag newtap stm32 bs -irlen ...
6951 @item # Create the debug target and say where it is
6952 @item target create stm32.cpu -chain-position stm32.cpu ...
6956 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6957 log file, I can see these error messages: Error: arm7_9_common.c:561
6958 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6964 @node Tcl Crash Course
6965 @chapter Tcl Crash Course
6968 Not everyone knows Tcl - this is not intended to be a replacement for
6969 learning Tcl, the intent of this chapter is to give you some idea of
6970 how the Tcl scripts work.
6972 This chapter is written with two audiences in mind. (1) OpenOCD users
6973 who need to understand a bit more of how JIM-Tcl works so they can do
6974 something useful, and (2) those that want to add a new command to
6977 @section Tcl Rule #1
6978 There is a famous joke, it goes like this:
6980 @item Rule #1: The wife is always correct
6981 @item Rule #2: If you think otherwise, See Rule #1
6984 The Tcl equal is this:
6987 @item Rule #1: Everything is a string
6988 @item Rule #2: If you think otherwise, See Rule #1
6991 As in the famous joke, the consequences of Rule #1 are profound. Once
6992 you understand Rule #1, you will understand Tcl.
6994 @section Tcl Rule #1b
6995 There is a second pair of rules.
6997 @item Rule #1: Control flow does not exist. Only commands
6998 @* For example: the classic FOR loop or IF statement is not a control
6999 flow item, they are commands, there is no such thing as control flow
7001 @item Rule #2: If you think otherwise, See Rule #1
7002 @* Actually what happens is this: There are commands that by
7003 convention, act like control flow key words in other languages. One of
7004 those commands is the word ``for'', another command is ``if''.
7007 @section Per Rule #1 - All Results are strings
7008 Every Tcl command results in a string. The word ``result'' is used
7009 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
7010 Everything is a string}
7012 @section Tcl Quoting Operators
7013 In life of a Tcl script, there are two important periods of time, the
7014 difference is subtle.
7017 @item Evaluation Time
7020 The two key items here are how ``quoted things'' work in Tcl. Tcl has
7021 three primary quoting constructs, the [square-brackets] the
7022 @{curly-braces@} and ``double-quotes''
7024 By now you should know $VARIABLES always start with a $DOLLAR
7025 sign. BTW: To set a variable, you actually use the command ``set'', as
7026 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
7027 = 1'' statement, but without the equal sign.
7030 @item @b{[square-brackets]}
7031 @* @b{[square-brackets]} are command substitutions. It operates much
7032 like Unix Shell `back-ticks`. The result of a [square-bracket]
7033 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
7034 string}. These two statements are roughly identical:
7038 echo "The Date is: $X"
7041 puts "The Date is: $X"
7043 @item @b{``double-quoted-things''}
7044 @* @b{``double-quoted-things''} are just simply quoted
7045 text. $VARIABLES and [square-brackets] are expanded in place - the
7046 result however is exactly 1 string. @i{Remember Rule #1 - Everything
7050 puts "It is now \"[date]\", $x is in 1 hour"
7052 @item @b{@{Curly-Braces@}}
7053 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
7054 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
7055 'single-quote' operators in BASH shell scripts, with the added
7056 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
7057 nested 3 times@}@}@} NOTE: [date] is a bad example;
7058 at this writing, Jim/OpenOCD does not have a date command.
7061 @section Consequences of Rule 1/2/3/4
7063 The consequences of Rule 1 are profound.
7065 @subsection Tokenisation & Execution.
7067 Of course, whitespace, blank lines and #comment lines are handled in
7070 As a script is parsed, each (multi) line in the script file is
7071 tokenised and according to the quoting rules. After tokenisation, that
7072 line is immedatly executed.
7074 Multi line statements end with one or more ``still-open''
7075 @{curly-braces@} which - eventually - closes a few lines later.
7077 @subsection Command Execution
7079 Remember earlier: There are no ``control flow''
7080 statements in Tcl. Instead there are COMMANDS that simply act like
7081 control flow operators.
7083 Commands are executed like this:
7086 @item Parse the next line into (argc) and (argv[]).
7087 @item Look up (argv[0]) in a table and call its function.
7088 @item Repeat until End Of File.
7091 It sort of works like this:
7094 ReadAndParse( &argc, &argv );
7096 cmdPtr = LookupCommand( argv[0] );
7098 (*cmdPtr->Execute)( argc, argv );
7102 When the command ``proc'' is parsed (which creates a procedure
7103 function) it gets 3 parameters on the command line. @b{1} the name of
7104 the proc (function), @b{2} the list of parameters, and @b{3} the body
7105 of the function. Not the choice of words: LIST and BODY. The PROC
7106 command stores these items in a table somewhere so it can be found by
7109 @subsection The FOR command
7111 The most interesting command to look at is the FOR command. In Tcl,
7112 the FOR command is normally implemented in C. Remember, FOR is a
7113 command just like any other command.
7115 When the ascii text containing the FOR command is parsed, the parser
7116 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
7120 @item The ascii text 'for'
7121 @item The start text
7122 @item The test expression
7127 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
7128 Remember @i{Rule #1 - Everything is a string.} The key point is this:
7129 Often many of those parameters are in @{curly-braces@} - thus the
7130 variables inside are not expanded or replaced until later.
7132 Remember that every Tcl command looks like the classic ``main( argc,
7133 argv )'' function in C. In JimTCL - they actually look like this:
7137 MyCommand( Jim_Interp *interp,
7139 Jim_Obj * const *argvs );
7142 Real Tcl is nearly identical. Although the newer versions have
7143 introduced a byte-code parser and intepreter, but at the core, it
7144 still operates in the same basic way.
7146 @subsection FOR command implementation
7148 To understand Tcl it is perhaps most helpful to see the FOR
7149 command. Remember, it is a COMMAND not a control flow structure.
7151 In Tcl there are two underlying C helper functions.
7153 Remember Rule #1 - You are a string.
7155 The @b{first} helper parses and executes commands found in an ascii
7156 string. Commands can be seperated by semicolons, or newlines. While
7157 parsing, variables are expanded via the quoting rules.
7159 The @b{second} helper evaluates an ascii string as a numerical
7160 expression and returns a value.
7162 Here is an example of how the @b{FOR} command could be
7163 implemented. The pseudo code below does not show error handling.
7165 void Execute_AsciiString( void *interp, const char *string );
7167 int Evaluate_AsciiExpression( void *interp, const char *string );
7170 MyForCommand( void *interp,
7175 SetResult( interp, "WRONG number of parameters");
7179 // argv[0] = the ascii string just like C
7181 // Execute the start statement.
7182 Execute_AsciiString( interp, argv[1] );
7186 i = Evaluate_AsciiExpression(interp, argv[2]);
7191 Execute_AsciiString( interp, argv[3] );
7193 // Execute the LOOP part
7194 Execute_AsciiString( interp, argv[4] );
7198 SetResult( interp, "" );
7203 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
7204 in the same basic way.
7206 @section OpenOCD Tcl Usage
7208 @subsection source and find commands
7209 @b{Where:} In many configuration files
7210 @* Example: @b{ source [find FILENAME] }
7211 @*Remember the parsing rules
7213 @item The FIND command is in square brackets.
7214 @* The FIND command is executed with the parameter FILENAME. It should
7215 find the full path to the named file. The RESULT is a string, which is
7216 substituted on the orginal command line.
7217 @item The command source is executed with the resulting filename.
7218 @* SOURCE reads a file and executes as a script.
7220 @subsection format command
7221 @b{Where:} Generally occurs in numerous places.
7222 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
7228 puts [format "The answer: %d" [expr $x * $y]]
7231 @item The SET command creates 2 variables, X and Y.
7232 @item The double [nested] EXPR command performs math
7233 @* The EXPR command produces numerical result as a string.
7235 @item The format command is executed, producing a single string
7236 @* Refer to Rule #1.
7237 @item The PUTS command outputs the text.
7239 @subsection Body or Inlined Text
7240 @b{Where:} Various TARGET scripts.
7243 proc someproc @{@} @{
7244 ... multiple lines of stuff ...
7246 $_TARGETNAME configure -event FOO someproc
7247 #2 Good - no variables
7248 $_TARGETNAME confgure -event foo "this ; that;"
7249 #3 Good Curly Braces
7250 $_TARGETNAME configure -event FOO @{
7253 #4 DANGER DANGER DANGER
7254 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
7257 @item The $_TARGETNAME is an OpenOCD variable convention.
7258 @*@b{$_TARGETNAME} represents the last target created, the value changes
7259 each time a new target is created. Remember the parsing rules. When
7260 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
7261 the name of the target which happens to be a TARGET (object)
7263 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
7264 @*There are 4 examples:
7266 @item The TCLBODY is a simple string that happens to be a proc name
7267 @item The TCLBODY is several simple commands seperated by semicolons
7268 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
7269 @item The TCLBODY is a string with variables that get expanded.
7272 In the end, when the target event FOO occurs the TCLBODY is
7273 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
7274 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
7276 Remember the parsing rules. In case #3, @{curly-braces@} mean the
7277 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
7278 and the text is evaluated. In case #4, they are replaced before the
7279 ``Target Object Command'' is executed. This occurs at the same time
7280 $_TARGETNAME is replaced. In case #4 the date will never
7281 change. @{BTW: [date] is a bad example; at this writing,
7282 Jim/OpenOCD does not have a date command@}
7284 @subsection Global Variables
7285 @b{Where:} You might discover this when writing your own procs @* In
7286 simple terms: Inside a PROC, if you need to access a global variable
7287 you must say so. See also ``upvar''. Example:
7289 proc myproc @{ @} @{
7290 set y 0 #Local variable Y
7291 global x #Global variable X
7292 puts [format "X=%d, Y=%d" $x $y]
7295 @section Other Tcl Hacks
7296 @b{Dynamic variable creation}
7298 # Dynamically create a bunch of variables.
7299 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
7301 set vn [format "BIT%d" $x]
7305 set $vn [expr (1 << $x)]
7308 @b{Dynamic proc/command creation}
7310 # One "X" function - 5 uart functions.
7311 foreach who @{A B C D E@}
7312 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
7318 @node OpenOCD Concept Index
7319 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
7320 @comment case issue with ``Index.html'' and ``index.html''
7321 @comment Occurs when creating ``--html --no-split'' output
7322 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
7323 @unnumbered OpenOCD Concept Index
7327 @node Command and Driver Index
7328 @unnumbered Command and Driver Index