1 # The IMX27 ADS eval board has a single IMX27 chip
2 # Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
3 source [find target/imx27.cfg]
4 $_TARGETNAME configure -event gdb-attach { reset init }
5 $_TARGETNAME configure -event reset-init { imx27ads_init }
7 # The IMX27 ADS board has a NOR flash on CS0
8 set _FLASHNAME $_CHIPNAME.flash
9 flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
11 proc imx27ads_init { } {
12 # This setup puts RAM at 0xA0000000
14 # reset the board correctly
18 mww 0x10000000 0x20040304
19 mww 0x10020000 0x00000000
20 mww 0x10000004 0xDFFBFCFB
21 mww 0x10020004 0xFFFFFFFF
25 # ========================================
26 # Configure DDR on CSD0 -- initial reset
27 # ========================================
28 mww 0xD8001010 0x00000008
30 # ========================================
31 # Configure PSRAM on CS5
32 # ========================================
33 mww 0xd8002050 0x0000dcf6
34 mww 0xd8002054 0x444a4541
35 mww 0xd8002058 0x44443302
37 # ========================================
38 # Configure16 bit NorFlash on CS0
39 # ========================================
40 mww 0xd8002000 0x0000CC03
41 mww 0xd8002004 0xa0330D01
42 mww 0xd8002008 0x00220800
44 # ========================================
45 # Configure CPLD on CS4
46 # ========================================
47 mww 0xd8002040 0x0000DCF6
48 mww 0xd8002044 0x444A4541
49 mww 0xd8002048 0x44443302
51 # ========================================
52 # Configure DDR on CSD0 -- wait 5000 cycle
53 # ========================================
54 mww 0x10027828 0x55555555
55 mww 0x10027830 0x55555555
56 mww 0x10027834 0x55555555
57 mww 0x10027838 0x00005005
58 mww 0x1002783C 0x15555555
60 mww 0xD8001010 0x00000004
62 mww 0xD8001004 0x00795729
64 mww 0xD8001000 0x92200000
67 mww 0xD8001000 0xA2200000
71 mww 0xD8001000 0xB2200000
75 mww 0xD8001000 0x82228085