src/target/arm_dpm.h

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation, Inc.,
  17  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #ifndef __ARM_DPM_H
  21 #define __ARM_DPM_H
  22
  23 /**
  24  * @file
  25  * This is the interface to the Debug Programmers Model for ARMv6 and
  26  * ARMv7 processors.  ARMv6 processors (such as ARM11xx implementations)
  27  * introduced a model which became part of the ARMv7-AR architecture
  28  * which is most familiar through the Cortex-A series parts.  While
  29  * specific details differ (like how to write the instruction register),
  30  * the high level models easily support shared code because those
  31  * registers are compatible.
  32  */
  33
  34 struct dpm_bp {
  35         struct breakpoint *bp;
  36         /* bp->address == breakpoint value register
  37          * control == breakpoint control register
  38          */
  39         uint32_t control;
  40         /* true if hardware state needs flushing */
  41         bool dirty;
  42 };
  43
  44 struct dpm_wp {
  45         struct watchpoint *wp;
  46         /* wp->address == watchpoint value register
  47          * control == watchpoint control register
  48          */
  49         uint32_t control;
  50         /* true if hardware state needs flushing */
  51         bool dirty;
  52 };
  53
  54 /**
  55  * This wraps an implementation of DPM primitives.  Each interface
  56  * provider supplies a structure like this, which is the glue between
  57  * upper level code and the lower level hardware access.
  58  *
  59  * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
  60  * support for CPU register access.
  61  */
  62 struct arm_dpm {
  63         struct arm *arm;
  64
  65         /** Cache of DIDR */
  66         uint32_t didr;
  67
  68         /** Invoke before a series of instruction operations */
  69         int (*prepare)(struct arm_dpm *);
  70
  71         /** Invoke after a series of instruction operations */
  72         int (*finish)(struct arm_dpm *);
  73
  74         /* WRITE TO CPU */
  75
  76         /** Runs one instruction, writing data to DCC before execution. */
  77         int (*instr_write_data_dcc)(struct arm_dpm *,
  78                         uint32_t opcode, uint32_t data);
  79
  80         /** Runs one instruction, writing data to R0 before execution. */
  81         int (*instr_write_data_r0)(struct arm_dpm *,
  82                         uint32_t opcode, uint32_t data);
  83
  84         /** Optional core-specific operation invoked after CPSR writes. */
  85         int (*instr_cpsr_sync)(struct arm_dpm *dpm);
  86
  87         /* READ FROM CPU */
  88
  89         /** Runs one instruction, reading data from dcc after execution. */
  90         int (*instr_read_data_dcc)(struct arm_dpm *,
  91                         uint32_t opcode, uint32_t *data);
  92
  93         /** Runs one instruction, reading data from r0 after execution. */
  94         int (*instr_read_data_r0)(struct arm_dpm *,
  95                         uint32_t opcode, uint32_t *data);
  96
  97         /* BREAKPOINT/WATCHPOINT SUPPORT */
  98
  99         /**
 100          * Enables one breakpoint or watchpoint by writing to the
 101          * hardware registers.  The specified breakpoint/watchpoint
 102          * must currently be disabled.  Indices 0..15 are used for
 103          * breakpoints; indices 16..31 are for watchpoints.
 104          */
 105         int (*bpwp_enable)(struct arm_dpm *, unsigned index,
 106                         uint32_t addr, uint32_t control);
 107
 108         /**
 109          * Disables one breakpoint or watchpoint by clearing its
 110          * hardware control registers.  Indices are the same ones
 111          * accepted by bpwp_enable().
 112          */
 113         int (*bpwp_disable)(struct arm_dpm *, unsigned index);
 114
 115         /* The breakpoint and watchpoint arrays are private to the
 116          * DPM infrastructure.  There are nbp indices in the dbp
 117          * array.  There are nwp indices in the dwp array.
 118          */
 119
 120         unsigned nbp;
 121         unsigned nwp;
 122         struct dpm_bp *dbp;
 123         struct dpm_wp *dwp;
 124
 125         /** Address of the instruction which triggered a watchpoint. */
 126         uint32_t wp_pc;
 127
 128         // FIXME -- read/write DCSR methods and symbols
 129 };
 130
 131 int arm_dpm_setup(struct arm_dpm *dpm);
 132 int arm_dpm_initialize(struct arm_dpm *dpm);
 133
 134 int arm_dpm_read_current_registers(struct arm_dpm *);
 135 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 136
 137 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 138
 139 /* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
 140  * Not all v7 bits are valid in v6.
 141  */
 142 #define DSCR_CORE_HALTED        (1 << 0)
 143 #define DSCR_CORE_RESTARTED     (1 << 1)
 144 #define DSCR_INT_DIS            (1 << 11)
 145 #define DSCR_ITR_EN             (1 << 13)
 146 #define DSCR_HALT_DBG_MODE      (1 << 14)
 147 #define DSCR_MON_DBG_MODE       (1 << 15)
 148 #define DSCR_INSTR_COMP         (1 << 24)
 149 #define DSCR_DTR_TX_FULL        (1 << 29)
 150 #define DSCR_DTR_RX_FULL        (1 << 30)
 151
 152 #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
 153
 154 #endif /* __ARM_DPM_H */