zy1000: reconfigure FPGA upon reset instead of just the CPU
[openocd/jflash.git] / tcl / 
treec78f17df4d971d6224ab9abb94ae480cfafa605d
drwxr-xr-x   ..
-rw-r--r-- 1601 bitsbytes.tcl
drwxr-xr-x - board
drwxr-xr-x - chip
drwxr-xr-x - cpld
drwxr-xr-x - cpu
drwxr-xr-x - interface
-rw-r--r-- 3558 memory.tcl
-rw-r--r-- 1680 mmr_helpers.tcl
-rw-r--r-- 578 readable.tcl
drwxr-xr-x - target
drwxr-xr-x - test