zy1000: reconfigure FPGA upon reset instead of just the CPU
[openocd/jflash.git] / src / flash / 
treef508cb633862f102931d53a6dd2a75586cbaa1a0
drwxr-xr-x   ..
-rw-r--r-- 427 Makefile.am
-rw-r--r-- 2164 common.c
-rw-r--r-- 2488 common.h
-rw-r--r-- 36836 mflash.c
-rw-r--r-- 10220 mflash.h
drwxr-xr-x - nand
drwxr-xr-x - nor
drwxr-xr-x - ocl
-rw-r--r-- 52 startup.tcl