1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <target/arm.h>
33 #include <helper/binarybuffer.h>
34 #include <target/algorithm.h>
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
48 /* FLASH_CR0 register bits */
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
62 /* FLASH_CR1 register bits */
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
77 /* FLASH_ER register bits */
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
88 struct str7x_flash_bank
{
89 uint32_t *sector_bits
;
92 uint32_t register_base
;
93 struct working_area
*write_algorithm
;
96 struct str7x_mem_layout
{
97 uint32_t sector_start
;
102 enum str7x_status_codes
{
103 STR7X_CMD_SUCCESS
= 0,
104 STR7X_INVALID_COMMAND
= 1,
105 STR7X_SRC_ADDR_ERROR
= 2,
106 STR7X_DST_ADDR_ERROR
= 3,
107 STR7X_SRC_ADDR_NOT_MAPPED
= 4,
108 STR7X_DST_ADDR_NOT_MAPPED
= 5,
109 STR7X_COUNT_ERROR
= 6,
110 STR7X_INVALID_SECTOR
= 7,
111 STR7X_SECTOR_NOT_BLANK
= 8,
112 STR7X_SECTOR_NOT_PREPARED
= 9,
113 STR7X_COMPARE_ERROR
= 10,
117 static struct str7x_mem_layout mem_layout_str7bank0
[] = {
118 {0x00000000, 0x02000, 0x01},
119 {0x00002000, 0x02000, 0x02},
120 {0x00004000, 0x02000, 0x04},
121 {0x00006000, 0x02000, 0x08},
122 {0x00008000, 0x08000, 0x10},
123 {0x00010000, 0x10000, 0x20},
124 {0x00020000, 0x10000, 0x40},
125 {0x00030000, 0x10000, 0x80}
128 static struct str7x_mem_layout mem_layout_str7bank1
[] = {
129 {0x00000000, 0x02000, 0x10000},
130 {0x00002000, 0x02000, 0x20000}
133 static int str7x_get_flash_adr(struct flash_bank
*bank
, uint32_t reg
)
135 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
136 return str7x_info
->register_base
| reg
;
139 static int str7x_build_block_list(struct flash_bank
*bank
)
141 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
145 int b0_sectors
= 0, b1_sectors
= 0;
147 switch (bank
->size
) {
161 LOG_ERROR("BUG: unknown bank->size encountered");
165 num_sectors
= b0_sectors
+ b1_sectors
;
167 bank
->num_sectors
= num_sectors
;
168 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
169 str7x_info
->sector_bits
= malloc(sizeof(uint32_t) * num_sectors
);
173 for (i
= 0; i
< b0_sectors
; i
++) {
174 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank0
[i
].sector_start
;
175 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank0
[i
].sector_size
;
176 bank
->sectors
[num_sectors
].is_erased
= -1;
177 /* the reset_init handler marks all the sectors unprotected,
178 * matching hardware after reset; keep the driver in sync
180 bank
->sectors
[num_sectors
].is_protected
= 0;
181 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank0
[i
].sector_bit
;
184 for (i
= 0; i
< b1_sectors
; i
++) {
185 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank1
[i
].sector_start
;
186 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank1
[i
].sector_size
;
187 bank
->sectors
[num_sectors
].is_erased
= -1;
188 /* the reset_init handler marks all the sectors unprotected,
189 * matching hardware after reset; keep the driver in sync
191 bank
->sectors
[num_sectors
].is_protected
= 0;
192 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank1
[i
].sector_bit
;
198 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
200 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command
)
202 struct str7x_flash_bank
*str7x_info
;
205 return ERROR_COMMAND_SYNTAX_ERROR
;
207 str7x_info
= malloc(sizeof(struct str7x_flash_bank
));
208 bank
->driver_priv
= str7x_info
;
210 /* set default bits for str71x flash */
211 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA1
| FLASH_BSYA0
);
212 str7x_info
->disable_bit
= (1 << 1);
214 if (strcmp(CMD_ARGV
[6], "STR71x") == 0)
215 str7x_info
->register_base
= 0x40100000;
216 else if (strcmp(CMD_ARGV
[6], "STR73x") == 0) {
217 str7x_info
->register_base
= 0x80100000;
218 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA0
);
219 } else if (strcmp(CMD_ARGV
[6], "STR75x") == 0) {
220 str7x_info
->register_base
= 0x20100000;
221 str7x_info
->disable_bit
= (1 << 0);
223 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV
[6]);
225 return ERROR_FLASH_BANK_INVALID
;
228 str7x_build_block_list(bank
);
230 str7x_info
->write_algorithm
= NULL
;
235 /* wait for flash to become idle or report errors.
237 FIX!!! what's the maximum timeout??? The documentation doesn't
238 state any maximum time.... by inspection it seems > 1000ms is to be
241 10000ms is long enough that it should cover anything, yet not
242 quite be equivalent to an infinite loop.
245 static int str7x_waitbusy(struct flash_bank
*bank
)
249 struct target
*target
= bank
->target
;
250 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
252 for (i
= 0 ; i
< 10000; i
++) {
254 err
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), &retval
);
258 if ((retval
& str7x_info
->busy_bits
) == 0)
263 LOG_ERROR("Timed out waiting for str7x flash");
268 static int str7x_result(struct flash_bank
*bank
)
270 struct target
*target
= bank
->target
;
271 uint32_t flash_flags
;
274 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), &flash_flags
);
275 if (retval
!= ERROR_OK
)
278 if (flash_flags
& FLASH_WPF
) {
279 LOG_ERROR("str7x hw write protection set");
282 if (flash_flags
& FLASH_RESER
) {
283 LOG_ERROR("str7x suspended program erase not resumed");
286 if (flash_flags
& FLASH_10ER
) {
287 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
290 if (flash_flags
& FLASH_PGER
) {
291 LOG_ERROR("str7x program error");
294 if (flash_flags
& FLASH_ERER
) {
295 LOG_ERROR("str7x erase error");
298 if (retval
== ERROR_OK
) {
299 if (flash_flags
& FLASH_ERR
) {
300 /* this should always be set if one of the others are set... */
301 LOG_ERROR("str7x write operation failed / bad setup");
309 static int str7x_protect_check(struct flash_bank
*bank
)
311 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
312 struct target
*target
= bank
->target
;
315 uint32_t flash_flags
;
317 if (bank
->target
->state
!= TARGET_HALTED
) {
318 LOG_ERROR("Target not halted");
319 return ERROR_TARGET_NOT_HALTED
;
323 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVWPAR
), &flash_flags
);
324 if (retval
!= ERROR_OK
)
327 for (i
= 0; i
< bank
->num_sectors
; i
++) {
328 if (flash_flags
& str7x_info
->sector_bits
[i
])
329 bank
->sectors
[i
].is_protected
= 0;
331 bank
->sectors
[i
].is_protected
= 1;
337 static int str7x_erase(struct flash_bank
*bank
, int first
, int last
)
339 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
340 struct target
*target
= bank
->target
;
344 uint32_t sectors
= 0;
347 if (bank
->target
->state
!= TARGET_HALTED
) {
348 LOG_ERROR("Target not halted");
349 return ERROR_TARGET_NOT_HALTED
;
352 for (i
= first
; i
<= last
; i
++)
353 sectors
|= str7x_info
->sector_bits
[i
];
355 LOG_DEBUG("sectors: 0x%" PRIx32
"", sectors
);
357 /* clear FLASH_ER register */
358 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
363 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
368 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR1
), cmd
);
372 cmd
= FLASH_SER
| FLASH_WMS
;
373 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
377 err
= str7x_waitbusy(bank
);
381 err
= str7x_result(bank
);
385 for (i
= first
; i
<= last
; i
++)
386 bank
->sectors
[i
].is_erased
= 1;
391 static int str7x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
393 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
394 struct target
*target
= bank
->target
;
397 uint32_t protect_blocks
;
399 if (bank
->target
->state
!= TARGET_HALTED
) {
400 LOG_ERROR("Target not halted");
401 return ERROR_TARGET_NOT_HALTED
;
404 protect_blocks
= 0xFFFFFFFF;
407 for (i
= first
; i
<= last
; i
++)
408 protect_blocks
&= ~(str7x_info
->sector_bits
[i
]);
411 /* clear FLASH_ER register */
413 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
418 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
422 cmd
= str7x_get_flash_adr(bank
, FLASH_NVWPAR
);
423 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), cmd
);
427 cmd
= protect_blocks
;
428 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), cmd
);
432 cmd
= FLASH_SPR
| FLASH_WMS
;
433 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
437 err
= str7x_waitbusy(bank
);
441 err
= str7x_result(bank
);
448 static int str7x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
449 uint32_t offset
, uint32_t count
)
451 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
452 struct target
*target
= bank
->target
;
453 uint32_t buffer_size
= 32768;
454 struct working_area
*source
;
455 uint32_t address
= bank
->base
+ offset
;
456 struct reg_param reg_params
[6];
457 struct arm_algorithm arm_algo
;
458 int retval
= ERROR_OK
;
460 /* see contib/loaders/flash/str7x.s for src */
462 static const uint32_t str7x_flash_write_code
[] = {
464 0xe3a04201, /* mov r4, #0x10000000 */
465 0xe5824000, /* str r4, [r2, #0x0] */
466 0xe5821010, /* str r1, [r2, #0x10] */
467 0xe4904004, /* ldr r4, [r0], #4 */
468 0xe5824008, /* str r4, [r2, #0x8] */
469 0xe4904004, /* ldr r4, [r0], #4 */
470 0xe582400c, /* str r4, [r2, #0xc] */
471 0xe3a04209, /* mov r4, #0x90000000 */
472 0xe5824000, /* str r4, [r2, #0x0] */
474 0xe5924000, /* ldr r4, [r2, #0x0] */
475 0xe1140005, /* tst r4, r5 */
476 0x1afffffc, /* bne busy */
477 0xe5924014, /* ldr r4, [r2, #0x14] */
478 0xe31400ff, /* tst r4, #0xff */
479 0x03140c01, /* tsteq r4, #0x100 */
480 0x1a000002, /* bne exit */
481 0xe2811008, /* add r1, r1, #0x8 */
482 0xe2533001, /* subs r3, r3, #1 */
483 0x1affffec, /* bne write */
485 0xeafffffe, /* b exit */
488 /* flash write code */
489 if (target_alloc_working_area_try(target
, sizeof(str7x_flash_write_code
),
490 &str7x_info
->write_algorithm
) != ERROR_OK
) {
491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
494 target_write_buffer(target
, str7x_info
->write_algorithm
->address
,
495 sizeof(str7x_flash_write_code
),
496 (uint8_t *)str7x_flash_write_code
);
499 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
501 if (buffer_size
<= 256) {
502 /* if we already allocated the writing code, but failed to get a
503 * buffer, free the algorithm */
504 if (str7x_info
->write_algorithm
)
505 target_free_working_area(target
, str7x_info
->write_algorithm
);
507 LOG_WARNING("no large enough working area available, can't do block memory writes");
508 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
512 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
513 arm_algo
.core_mode
= ARM_MODE_SVC
;
514 arm_algo
.core_state
= ARM_STATE_ARM
;
516 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
517 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
518 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
519 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
520 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
521 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
524 uint32_t thisrun_count
= (count
> (buffer_size
/ 8)) ? (buffer_size
/ 8) : count
;
526 target_write_buffer(target
, source
->address
, thisrun_count
* 8, buffer
);
528 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
529 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
530 buf_set_u32(reg_params
[2].value
, 0, 32, str7x_get_flash_adr(bank
, FLASH_CR0
));
531 buf_set_u32(reg_params
[3].value
, 0, 32, thisrun_count
);
532 buf_set_u32(reg_params
[5].value
, 0, 32, str7x_info
->busy_bits
);
534 retval
= target_run_algorithm(target
, 0, NULL
, 6, reg_params
,
535 str7x_info
->write_algorithm
->address
,
536 str7x_info
->write_algorithm
->address
+ (sizeof(str7x_flash_write_code
) - 4),
538 if (retval
!= ERROR_OK
)
541 if (buf_get_u32(reg_params
[4].value
, 0, 32) != 0x00) {
542 retval
= str7x_result(bank
);
546 buffer
+= thisrun_count
* 8;
547 address
+= thisrun_count
* 8;
548 count
-= thisrun_count
;
551 target_free_working_area(target
, source
);
552 target_free_working_area(target
, str7x_info
->write_algorithm
);
554 destroy_reg_param(®_params
[0]);
555 destroy_reg_param(®_params
[1]);
556 destroy_reg_param(®_params
[2]);
557 destroy_reg_param(®_params
[3]);
558 destroy_reg_param(®_params
[4]);
559 destroy_reg_param(®_params
[5]);
564 static int str7x_write(struct flash_bank
*bank
, uint8_t *buffer
,
565 uint32_t offset
, uint32_t count
)
567 struct target
*target
= bank
->target
;
568 uint32_t dwords_remaining
= (count
/ 8);
569 uint32_t bytes_remaining
= (count
& 0x00000007);
570 uint32_t address
= bank
->base
+ offset
;
571 uint32_t bytes_written
= 0;
574 uint32_t check_address
= offset
;
577 if (bank
->target
->state
!= TARGET_HALTED
) {
578 LOG_ERROR("Target not halted");
579 return ERROR_TARGET_NOT_HALTED
;
583 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment", offset
);
584 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
587 for (i
= 0; i
< bank
->num_sectors
; i
++) {
588 uint32_t sec_start
= bank
->sectors
[i
].offset
;
589 uint32_t sec_end
= sec_start
+ bank
->sectors
[i
].size
;
591 /* check if destination falls within the current sector */
592 if ((check_address
>= sec_start
) && (check_address
< sec_end
)) {
593 /* check if destination ends in the current sector */
594 if (offset
+ count
< sec_end
)
595 check_address
= offset
+ count
;
597 check_address
= sec_end
;
601 if (check_address
!= offset
+ count
)
602 return ERROR_FLASH_DST_OUT_OF_BANK
;
604 /* clear FLASH_ER register */
605 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
607 /* multiple dwords (8-byte) to be programmed? */
608 if (dwords_remaining
> 0) {
609 /* try using a block write */
610 retval
= str7x_write_block(bank
, buffer
, offset
, dwords_remaining
);
611 if (retval
!= ERROR_OK
) {
612 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
613 /* if block write failed (no sufficient working area),
614 * we use normal (slow) single dword accesses */
615 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
620 buffer
+= dwords_remaining
* 8;
621 address
+= dwords_remaining
* 8;
622 dwords_remaining
= 0;
626 while (dwords_remaining
> 0) {
629 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
632 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
635 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
636 4, 1, buffer
+ bytes_written
);
640 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
641 4, 1, buffer
+ bytes_written
);
644 /* start programming cycle */
645 cmd
= FLASH_DWPG
| FLASH_WMS
;
646 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
649 err
= str7x_waitbusy(bank
);
653 err
= str7x_result(bank
);
661 if (bytes_remaining
) {
662 uint8_t last_dword
[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
664 /* copy the last remaining bytes into the write buffer */
665 memcpy(last_dword
, buffer
+bytes_written
, bytes_remaining
);
669 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
672 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
675 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
679 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
680 4, 1, last_dword
+ 4);
682 /* start programming cycle */
683 cmd
= FLASH_DWPG
| FLASH_WMS
;
684 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
687 err
= str7x_waitbusy(bank
);
691 err
= str7x_result(bank
);
699 static int str7x_probe(struct flash_bank
*bank
)
705 COMMAND_HANDLER(str7x_handle_part_id_command
)
711 static int get_str7x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
713 snprintf(buf
, buf_size
, "str7x flash driver info");
714 /* STR7x flash doesn't support sector protection interrogation.
715 * FLASH_NVWPAR acts as a write only register; its read value
716 * doesn't reflect the actual protection state of the sectors.
718 LOG_WARNING("STR7x flash lock information might not be correct "
719 "due to hardware limitations.");
723 COMMAND_HANDLER(str7x_handle_disable_jtag_command
)
725 struct target
*target
= NULL
;
726 struct str7x_flash_bank
*str7x_info
= NULL
;
729 uint16_t ProtectionLevel
= 0;
730 uint16_t ProtectionRegs
;
733 return ERROR_COMMAND_SYNTAX_ERROR
;
735 struct flash_bank
*bank
;
736 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
737 if (ERROR_OK
!= retval
)
740 str7x_info
= bank
->driver_priv
;
742 target
= bank
->target
;
744 if (target
->state
!= TARGET_HALTED
) {
745 LOG_ERROR("Target not halted");
746 return ERROR_TARGET_NOT_HALTED
;
749 /* first we get protection status */
751 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR0
), ®
);
753 if (!(reg
& str7x_info
->disable_bit
))
756 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR1
), ®
);
757 ProtectionRegs
= ~(reg
>> 16);
759 while (((ProtectionRegs
) != 0) && (ProtectionLevel
< 16)) {
760 ProtectionRegs
>>= 1;
764 if (ProtectionLevel
== 0) {
765 flash_cmd
= FLASH_SPR
;
766 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
767 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFB8);
768 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), 0xFFFFFFFD);
769 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
770 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
772 flash_cmd
= FLASH_SPR
;
773 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
774 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFBC);
775 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
776 ~(1 << (15 + ProtectionLevel
)));
777 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
778 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
784 static const struct command_registration str7x_exec_command_handlers
[] = {
786 .name
= "disable_jtag",
788 .handler
= str7x_handle_disable_jtag_command
,
789 .mode
= COMMAND_EXEC
,
790 .help
= "disable jtag access",
792 COMMAND_REGISTRATION_DONE
795 static const struct command_registration str7x_command_handlers
[] = {
799 .help
= "str7x flash command group",
801 .chain
= str7x_exec_command_handlers
,
803 COMMAND_REGISTRATION_DONE
806 struct flash_driver str7x_flash
= {
808 .commands
= str7x_command_handlers
,
809 .flash_bank_command
= str7x_flash_bank_command
,
810 .erase
= str7x_erase
,
811 .protect
= str7x_protect
,
812 .write
= str7x_write
,
813 .read
= default_flash_read
,
814 .probe
= str7x_probe
,
815 .auto_probe
= str7x_probe
,
816 .erase_check
= default_flash_blank_check
,
817 .protect_check
= str7x_protect_check
,
818 .info
= get_str7x_info
,