src/flash/nand/mx2.h

   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 /*
  24  * Freescale iMX OpenOCD NAND Flash controller support.
  25  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  26  *
  27  * Many thanks to Ben Dooks for writing s3c24xx driver.
  28  */
  29
  30 #define         MXC_NF_BUFSIZ                           (mxc_nf_info->mxc_regs_addr + 0x00)
  31 #define         MXC_NF_BUFADDR                          (mxc_nf_info->mxc_regs_addr + 0x04)
  32 #define         MXC_NF_FADDR                            (mxc_nf_info->mxc_regs_addr + 0x06)
  33 #define         MXC_NF_FCMD                                     (mxc_nf_info->mxc_regs_addr + 0x08)
  34 #define         MXC_NF_BUFCFG                           (mxc_nf_info->mxc_regs_addr + 0x0a)
  35 #define         MXC_NF_ECCSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x0c)
  36 #define         MXC_NF_ECCMAINPOS                       (mxc_nf_info->mxc_regs_addr + 0x0e)
  37 #define         MXC_NF_ECCSPAREPOS                      (mxc_nf_info->mxc_regs_addr + 0x10)
  38 #define         MXC_NF_FWP                                      (mxc_nf_info->mxc_regs_addr + 0x12)
  39 #define         MXC_NF_V1_UNLOCKSTART           (mxc_nf_info->mxc_regs_addr + 0x14)
  40 #define         MXC_NF_V1_UNLOCKEND                     (mxc_nf_info->mxc_regs_addr + 0x16)
  41 #define         MXC_NF_V2_UNLOCKSTART0          (mxc_nf_info->mxc_regs_addr + 0x20)
  42 #define         MXC_NF_V2_UNLOCKSTART1          (mxc_nf_info->mxc_regs_addr + 0x24)
  43 #define         MXC_NF_V2_UNLOCKSTART2          (mxc_nf_info->mxc_regs_addr + 0x28)
  44 #define         MXC_NF_V2_UNLOCKSTART3          (mxc_nf_info->mxc_regs_addr + 0x2c)
  45 #define         MXC_NF_V2_UNLOCKEND0            (mxc_nf_info->mxc_regs_addr + 0x22)
  46 #define         MXC_NF_V2_UNLOCKEND1            (mxc_nf_info->mxc_regs_addr + 0x26)
  47 #define         MXC_NF_V2_UNLOCKEND2            (mxc_nf_info->mxc_regs_addr + 0x2a)
  48 #define         MXC_NF_V2_UNLOCKEND3            (mxc_nf_info->mxc_regs_addr + 0x2e)
  49 #define         MXC_NF_FWPSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x18)
  50  /*
  51   * all bits not marked as self-clearing bit
  52   */
  53 #define         MXC_NF_CFG1                                     (mxc_nf_info->mxc_regs_addr + 0x1a)
  54 #define         MXC_NF_CFG2                                     (mxc_nf_info->mxc_regs_addr + 0x1c)
  55
  56 #define         MXC_NF_MAIN_BUFFER0                     (mxc_nf_info->mxc_base_addr + 0x0000)
  57 #define         MXC_NF_MAIN_BUFFER1                     (mxc_nf_info->mxc_base_addr + 0x0200)
  58 #define         MXC_NF_MAIN_BUFFER2                     (mxc_nf_info->mxc_base_addr + 0x0400)
  59 #define         MXC_NF_MAIN_BUFFER3                     (mxc_nf_info->mxc_base_addr + 0x0600)
  60 #define         MXC_NF_V1_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x0800)
  61 #define         MXC_NF_V1_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x0810)
  62 #define         MXC_NF_V1_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x0820)
  63 #define         MXC_NF_V1_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x0830)
  64 #define         MXC_NF_V2_MAIN_BUFFER4          (mxc_nf_info->mxc_base_addr + 0x0800)
  65 #define         MXC_NF_V2_MAIN_BUFFER5          (mxc_nf_info->mxc_base_addr + 0x0a00)
  66 #define         MXC_NF_V2_MAIN_BUFFER6          (mxc_nf_info->mxc_base_addr + 0x0c00)
  67 #define         MXC_NF_V2_MAIN_BUFFER7          (mxc_nf_info->mxc_base_addr + 0x0e00)
  68 #define         MXC_NF_V2_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x1000)
  69 #define         MXC_NF_V2_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x1040)
  70 #define         MXC_NF_V2_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x1080)
  71 #define         MXC_NF_V2_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x10c0)
  72 #define         MXC_NF_V2_SPARE_BUFFER4         (mxc_nf_info->mxc_base_addr + 0x1100)
  73 #define         MXC_NF_V2_SPARE_BUFFER5         (mxc_nf_info->mxc_base_addr + 0x1140)
  74 #define         MXC_NF_V2_SPARE_BUFFER6         (mxc_nf_info->mxc_base_addr + 0x1180)
  75 #define         MXC_NF_V2_SPARE_BUFFER7         (mxc_nf_info->mxc_base_addr + 0x11c0)
  76 #define         MXC_NF_MAIN_BUFFER_LEN          512
  77 #define         MXC_NF_SPARE_BUFFER_LEN         16
  78 #define         MXC_NF_SPARE_BUFFER_MAX         64
  79 #define         MXC_NF_V1_LAST_BUFFADDR         ((MXC_NF_V1_SPARE_BUFFER3) + \
  80         MXC_NF_SPARE_BUFFER_LEN - 2)
  81 #define         MXC_NF_V2_LAST_BUFFADDR         ((MXC_NF_V2_SPARE_BUFFER7) + \
  82         MXC_NF_SPARE_BUFFER_LEN - 2)
  83
  84 /* bits in MXC_NF_CFG1 register */
  85 #define         MXC_NF_BIT_ECC_4BIT                     (1<<0)
  86 #define         MXC_NF_BIT_SPARE_ONLY_EN        (1<<2)
  87 #define         MXC_NF_BIT_ECC_EN                       (1<<3)
  88 #define         MXC_NF_BIT_INT_DIS                      (1<<4)
  89 #define         MXC_NF_BIT_BE_EN                        (1<<5)
  90 #define         MXC_NF_BIT_RESET_EN                     (1<<6)
  91 #define         MXC_NF_BIT_FORCE_CE                     (1<<7)
  92 #define         MXC_NF_V2_CFG1_PPB(x)           (((x) & 0x3) << 9)
  93
  94 /* bits in MXC_NF_CFG2 register */
  95
  96 /*Flash Command Input*/
  97 #define         MXC_NF_BIT_OP_FCI                       (1<<0)
  98  /*
  99   * Flash Address Input
 100   */
 101 #define         MXC_NF_BIT_OP_FAI                       (1<<1)
 102  /*
 103   * Flash Data Input
 104   */
 105 #define         MXC_NF_BIT_OP_FDI                       (1<<2)
 106
 107 /* see "enum mx_dataout_type" below */
 108 #define         MXC_NF_BIT_DATAOUT_TYPE(x)      ((x)<<3)
 109 #define         MXC_NF_BIT_OP_DONE                      (1<<15)
 110
 111 #define         MXC_CCM_CGR2                            0x53f80028
 112 #define         MXC_GPR                                         0x43fac008
 113 #define         MX2_FMCR                                        0x10027814
 114 #define         MX2_FMCR_NF_16BIT_SEL           (1<<4)
 115 #define         MX2_FMCR_NF_FMS                         (1<<5)
 116 #define         MX3_PCSR                                        0x53f8000c
 117 #define         MX3_PCSR_NF_16BIT_SEL           (1<<31)
 118 #define         MX3_PCSR_NF_FMS                         (1<<30)
 119 #define         MX35_RCSR                                       0x53f80018
 120 #define         MX35_RCSR_NF_16BIT_SEL          (1<<14)
 121 #define         MX35_RCSR_NF_FMS                        (1<<8)
 122 #define         MX35_RCSR_NF_4K                         (1<<9)
 123
 124 enum mxc_version {
 125         MXC_VERSION_UKWN = 0,
 126         MXC_VERSION_MX27 = 1,
 127         MXC_VERSION_MX31 = 2,
 128         MXC_VERSION_MX35 = 4
 129 };
 130
 131 enum mxc_dataout_type {
 132         MXC_NF_DATAOUT_PAGE = 1,
 133         MXC_NF_DATAOUT_NANDID = 2,
 134         MXC_NF_DATAOUT_NANDSTATUS = 4,
 135 };
 136
 137 enum mxc_nf_finalize_action {
 138         MXC_NF_FIN_NONE,
 139         MXC_NF_FIN_DATAOUT,
 140 };
 141
 142 struct mxc_nf_flags {
 143         unsigned host_little_endian:1;
 144         unsigned target_little_endian:1;
 145         unsigned nand_readonly:1;
 146         unsigned one_kb_sram:1;
 147         unsigned hw_ecc_enabled:1;
 148         unsigned biswap_enabled:1;
 149 };
 150
 151 struct mxc_nf_controller {
 152         enum mxc_version mxc_version;
 153         uint32_t mxc_base_addr;
 154         uint32_t mxc_regs_addr;
 155         enum mxc_dataout_type optype;
 156         enum mxc_nf_finalize_action fin;
 157         struct mxc_nf_flags flags;
 158 };