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MIPS: remove unused arg from mips_ejtag_set_instr
[openocd/jflash.git] / src / target / etm.c
bloba1c77b0ff3392e77de20a5917eb09dcb48793c64
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_CTRL_DBGRQ
450 & ~ETM_PORT_CLOCK_MASK)
451 | etm_ctx->control;
452
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
455
456 etm_ctx->control = etm_ctrl_value;
457
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 return retval;
460
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
463 */
464
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
466 {
467 LOG_ERROR("ETM capture driver initialization failed");
468 return retval;
469 }
470 return ERROR_OK;
471 }
472
473 static int etm_get_reg(struct reg *reg)
474 {
475 int retval;
476
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
478 {
479 LOG_ERROR("BUG: error scheduling etm register read");
480 return retval;
481 }
482
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
484 {
485 LOG_ERROR("register read failed");
486 return retval;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
494 {
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
499
500 if (etm_reg->reg_info->mode == WO) {
501 LOG_ERROR("BUG: can't read write-only register %s", r->name);
502 return ERROR_INVALID_ARGUMENTS;
503 }
504
505 LOG_DEBUG("%s (%u)", r->name, reg_addr);
506
507 jtag_set_end_state(TAP_IDLE);
508 arm_jtag_scann(etm_reg->jtag_info, 0x6);
509 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
510
511 fields[0].num_bits = 32;
512 fields[0].out_value = reg->value;
513 fields[0].in_value = NULL;
514 fields[0].check_value = NULL;
515 fields[0].check_mask = NULL;
516
517 fields[1].num_bits = 7;
518 fields[1].out_value = malloc(1);
519 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
520 fields[1].in_value = NULL;
521 fields[1].check_value = NULL;
522 fields[1].check_mask = NULL;
523
524 fields[2].num_bits = 1;
525 fields[2].out_value = malloc(1);
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].in_value = NULL;
528 fields[2].check_value = NULL;
529 fields[2].check_mask = NULL;
530
531 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
532
533 fields[0].in_value = reg->value;
534 fields[0].check_value = check_value;
535 fields[0].check_mask = check_mask;
536
537 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
538
539 free(fields[1].out_value);
540 free(fields[2].out_value);
541
542 return ERROR_OK;
543 }
544
545 static int etm_set_reg(struct reg *reg, uint32_t value)
546 {
547 int retval;
548
549 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
550 {
551 LOG_ERROR("BUG: error scheduling etm register write");
552 return retval;
553 }
554
555 buf_set_u32(reg->value, 0, reg->size, value);
556 reg->valid = 1;
557 reg->dirty = 0;
558
559 return ERROR_OK;
560 }
561
562 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
563 {
564 int retval;
565
566 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
567
568 if ((retval = jtag_execute_queue()) != ERROR_OK)
569 {
570 LOG_ERROR("register write failed");
571 return retval;
572 }
573 return ERROR_OK;
574 }
575
576 static int etm_write_reg(struct reg *reg, uint32_t value)
577 {
578 struct etm_reg *etm_reg = reg->arch_info;
579 const struct etm_reg_info *r = etm_reg->reg_info;
580 uint8_t reg_addr = r->addr & 0x7f;
581 struct scan_field fields[3];
582
583 if (etm_reg->reg_info->mode == RO) {
584 LOG_ERROR("BUG: can't write read--only register %s", r->name);
585 return ERROR_INVALID_ARGUMENTS;
586 }
587
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
589
590 jtag_set_end_state(TAP_IDLE);
591 arm_jtag_scann(etm_reg->jtag_info, 0x6);
592 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
593
594 fields[0].num_bits = 32;
595 uint8_t tmp1[4];
596 fields[0].out_value = tmp1;
597 buf_set_u32(fields[0].out_value, 0, 32, value);
598 fields[0].in_value = NULL;
599
600 fields[1].num_bits = 7;
601 uint8_t tmp2;
602 fields[1].out_value = &tmp2;
603 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
604 fields[1].in_value = NULL;
605
606 fields[2].num_bits = 1;
607 uint8_t tmp3;
608 fields[2].out_value = &tmp3;
609 buf_set_u32(fields[2].out_value, 0, 1, 1);
610 fields[2].in_value = NULL;
611
612 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
613
614 return ERROR_OK;
615 }
616
617
618 /* ETM trace analysis functionality */
619
620 static struct etm_capture_driver *etm_capture_drivers[] =
621 {
622 &etb_capture_driver,
623 &etm_dummy_capture_driver,
624 #if BUILD_OOCD_TRACE == 1
625 &oocd_trace_capture_driver,
626 #endif
627 NULL
628 };
629
630 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
631 {
632 int i;
633 int section = -1;
634 size_t size_read;
635 uint32_t opcode;
636 int retval;
637
638 if (!ctx->image)
639 return ERROR_TRACE_IMAGE_UNAVAILABLE;
640
641 /* search for the section the current instruction belongs to */
642 for (i = 0; i < ctx->image->num_sections; i++)
643 {
644 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
645 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
646 {
647 section = i;
648 break;
649 }
650 }
651
652 if (section == -1)
653 {
654 /* current instruction couldn't be found in the image */
655 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
656 }
657
658 if (ctx->core_state == ARM_STATE_ARM)
659 {
660 uint8_t buf[4];
661 if ((retval = image_read_section(ctx->image, section,
662 ctx->current_pc - ctx->image->sections[section].base_address,
663 4, buf, &size_read)) != ERROR_OK)
664 {
665 LOG_ERROR("error while reading instruction: %i", retval);
666 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
667 }
668 opcode = target_buffer_get_u32(ctx->target, buf);
669 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
670 }
671 else if (ctx->core_state == ARM_STATE_THUMB)
672 {
673 uint8_t buf[2];
674 if ((retval = image_read_section(ctx->image, section,
675 ctx->current_pc - ctx->image->sections[section].base_address,
676 2, buf, &size_read)) != ERROR_OK)
677 {
678 LOG_ERROR("error while reading instruction: %i", retval);
679 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
680 }
681 opcode = target_buffer_get_u16(ctx->target, buf);
682 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
683 }
684 else if (ctx->core_state == ARM_STATE_JAZELLE)
685 {
686 LOG_ERROR("BUG: tracing of jazelle code not supported");
687 return ERROR_FAIL;
688 }
689 else
690 {
691 LOG_ERROR("BUG: unknown core state encountered");
692 return ERROR_FAIL;
693 }
694
695 return ERROR_OK;
696 }
697
698 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
699 {
700 while (ctx->data_index < ctx->trace_depth)
701 {
702 /* if the caller specified an address packet offset, skip until the
703 * we reach the n-th cycle marked with tracesync */
704 if (apo > 0)
705 {
706 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
707 apo--;
708
709 if (apo > 0)
710 {
711 ctx->data_index++;
712 ctx->data_half = 0;
713 }
714 continue;
715 }
716
717 /* no tracedata output during a TD cycle
718 * or in a trigger cycle */
719 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
720 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
721 {
722 ctx->data_index++;
723 ctx->data_half = 0;
724 continue;
725 }
726
727 /* FIXME there are more port widths than these... */
728 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
729 {
730 if (ctx->data_half == 0)
731 {
732 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
733 ctx->data_half = 1;
734 }
735 else
736 {
737 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
738 ctx->data_half = 0;
739 ctx->data_index++;
740 }
741 }
742 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
743 {
744 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
745 ctx->data_index++;
746 }
747 else
748 {
749 /* on a 4-bit port, a packet will be output during two consecutive cycles */
750 if (ctx->data_index > (ctx->trace_depth - 2))
751 return -1;
752
753 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
754 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
755 ctx->data_index += 2;
756 }
757
758 return 0;
759 }
760
761 return -1;
762 }
763
764 static int etmv1_branch_address(struct etm_context *ctx)
765 {
766 int retval;
767 uint8_t packet;
768 int shift = 0;
769 int apo;
770 uint32_t i;
771
772 /* quit analysis if less than two cycles are left in the trace
773 * because we can't extract the APO */
774 if (ctx->data_index > (ctx->trace_depth - 2))
775 return -1;
776
777 /* a BE could be output during an APO cycle, skip the current
778 * and continue with the new one */
779 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
780 return 1;
781 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
782 return 2;
783
784 /* address packet offset encoded in the next two cycles' pipestat bits */
785 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
786 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
787
788 /* count number of tracesync cycles between current pipe_index and data_index
789 * i.e. the number of tracesyncs that data_index already passed by
790 * to subtract them from the APO */
791 for (i = ctx->pipe_index; i < ctx->data_index; i++)
792 {
793 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
794 apo--;
795 }
796
797 /* extract up to four 7-bit packets */
798 do {
799 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
800 return -1;
801 ctx->last_branch &= ~(0x7f << shift);
802 ctx->last_branch |= (packet & 0x7f) << shift;
803 shift += 7;
804 } while ((packet & 0x80) && (shift < 28));
805
806 /* one last packet holding 4 bits of the address, plus the branch reason code */
807 if ((shift == 28) && (packet & 0x80))
808 {
809 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
810 return -1;
811 ctx->last_branch &= 0x0fffffff;
812 ctx->last_branch |= (packet & 0x0f) << 28;
813 ctx->last_branch_reason = (packet & 0x70) >> 4;
814 shift += 4;
815 }
816 else
817 {
818 ctx->last_branch_reason = 0;
819 }
820
821 if (shift == 32)
822 {
823 ctx->pc_ok = 1;
824 }
825
826 /* if a full address was output, we might have branched into Jazelle state */
827 if ((shift == 32) && (packet & 0x80))
828 {
829 ctx->core_state = ARM_STATE_JAZELLE;
830 }
831 else
832 {
833 /* if we didn't branch into Jazelle state, the current processor state is
834 * encoded in bit 0 of the branch target address */
835 if (ctx->last_branch & 0x1)
836 {
837 ctx->core_state = ARM_STATE_THUMB;
838 ctx->last_branch &= ~0x1;
839 }
840 else
841 {
842 ctx->core_state = ARM_STATE_ARM;
843 ctx->last_branch &= ~0x3;
844 }
845 }
846
847 return 0;
848 }
849
850 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
851 {
852 int j;
853 uint8_t buf[4];
854 int retval;
855
856 for (j = 0; j < size; j++)
857 {
858 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
859 return -1;
860 }
861
862 if (size == 8)
863 {
864 LOG_ERROR("TODO: add support for 64-bit values");
865 return -1;
866 }
867 else if (size == 4)
868 *data = target_buffer_get_u32(ctx->target, buf);
869 else if (size == 2)
870 *data = target_buffer_get_u16(ctx->target, buf);
871 else if (size == 1)
872 *data = buf[0];
873 else
874 return -1;
875
876 return 0;
877 }
878
879 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
880 {
881 int retval;
882 struct arm_instruction instruction;
883
884 /* read the trace data if it wasn't read already */
885 if (ctx->trace_depth == 0)
886 ctx->capture_driver->read_trace(ctx);
887
888 /* start at the beginning of the captured trace */
889 ctx->pipe_index = 0;
890 ctx->data_index = 0;
891 ctx->data_half = 0;
892
893 /* neither the PC nor the data pointer are valid */
894 ctx->pc_ok = 0;
895 ctx->ptr_ok = 0;
896
897 while (ctx->pipe_index < ctx->trace_depth)
898 {
899 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
900 uint32_t next_pc = ctx->current_pc;
901 uint32_t old_data_index = ctx->data_index;
902 uint32_t old_data_half = ctx->data_half;
903 uint32_t old_index = ctx->pipe_index;
904 uint32_t last_instruction = ctx->last_instruction;
905 uint32_t cycles = 0;
906 int current_pc_ok = ctx->pc_ok;
907
908 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
909 {
910 command_print(cmd_ctx, "--- trigger ---");
911 }
912
913 /* instructions execute in IE/D or BE/D cycles */
914 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
915 ctx->last_instruction = ctx->pipe_index;
916
917 /* if we don't have a valid pc skip until we reach an indirect branch */
918 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
919 {
920 ctx->pipe_index++;
921 continue;
922 }
923
924 /* any indirect branch could have interrupted instruction flow
925 * - the branch reason code could indicate a trace discontinuity
926 * - a branch to the exception vectors indicates an exception
927 */
928 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
929 {
930 /* backup current data index, to be able to consume the branch address
931 * before examining data address and values
932 */
933 old_data_index = ctx->data_index;
934 old_data_half = ctx->data_half;
935
936 ctx->last_instruction = ctx->pipe_index;
937
938 if ((retval = etmv1_branch_address(ctx)) != 0)
939 {
940 /* negative return value from etmv1_branch_address means we ran out of packets,
941 * quit analysing the trace */
942 if (retval < 0)
943 break;
944
945 /* a positive return values means the current branch was abandoned,
946 * and a new branch was encountered in cycle ctx->pipe_index + retval;
947 */
948 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
949 ctx->pipe_index += retval;
950 continue;
951 }
952
953 /* skip over APO cycles */
954 ctx->pipe_index += 2;
955
956 switch (ctx->last_branch_reason)
957 {
958 case 0x0: /* normal PC change */
959 next_pc = ctx->last_branch;
960 break;
961 case 0x1: /* tracing enabled */
962 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
963 ctx->current_pc = ctx->last_branch;
964 ctx->pipe_index++;
965 continue;
966 break;
967 case 0x2: /* trace restarted after FIFO overflow */
968 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
969 ctx->current_pc = ctx->last_branch;
970 ctx->pipe_index++;
971 continue;
972 break;
973 case 0x3: /* exit from debug state */
974 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
975 ctx->current_pc = ctx->last_branch;
976 ctx->pipe_index++;
977 continue;
978 break;
979 case 0x4: /* periodic synchronization point */
980 next_pc = ctx->last_branch;
981 /* if we had no valid PC prior to this synchronization point,
982 * we have to move on with the next trace cycle
983 */
984 if (!current_pc_ok)
985 {
986 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
987 ctx->current_pc = next_pc;
988 ctx->pipe_index++;
989 continue;
990 }
991 break;
992 default: /* reserved */
993 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
994 return ERROR_FAIL;
995 }
996
997 /* if we got here the branch was a normal PC change
998 * (or a periodic synchronization point, which means the same for that matter)
999 * if we didn't accquire a complete PC continue with the next cycle
1000 */
1001 if (!ctx->pc_ok)
1002 continue;
1003
1004 /* indirect branch to the exception vector means an exception occured */
1005 if ((ctx->last_branch <= 0x20)
1006 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1007 {
1008 if ((ctx->last_branch & 0xff) == 0x10)
1009 {
1010 command_print(cmd_ctx, "data abort");
1011 }
1012 else
1013 {
1014 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1015 ctx->current_pc = ctx->last_branch;
1016 ctx->pipe_index++;
1017 continue;
1018 }
1019 }
1020 }
1021
1022 /* an instruction was executed (or not, depending on the condition flags)
1023 * retrieve it from the image for displaying */
1024 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1025 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1026 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1027 {
1028 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1029 {
1030 /* can't continue tracing with no image available */
1031 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1032 {
1033 return retval;
1034 }
1035 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1036 {
1037 /* TODO: handle incomplete images
1038 * for now we just quit the analsysis*/
1039 return retval;
1040 }
1041 }
1042
1043 cycles = old_index - last_instruction;
1044 }
1045
1046 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1047 {
1048 uint32_t new_data_index = ctx->data_index;
1049 uint32_t new_data_half = ctx->data_half;
1050
1051 /* in case of a branch with data, the branch target address was consumed before
1052 * we temporarily go back to the saved data index */
1053 if (pipestat == STAT_BD)
1054 {
1055 ctx->data_index = old_data_index;
1056 ctx->data_half = old_data_half;
1057 }
1058
1059 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1060 {
1061 uint8_t packet;
1062 int shift = 0;
1063
1064 do {
1065 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1066 return ERROR_ETM_ANALYSIS_FAILED;
1067 ctx->last_ptr &= ~(0x7f << shift);
1068 ctx->last_ptr |= (packet & 0x7f) << shift;
1069 shift += 7;
1070 } while ((packet & 0x80) && (shift < 32));
1071
1072 if (shift >= 32)
1073 ctx->ptr_ok = 1;
1074
1075 if (ctx->ptr_ok)
1076 {
1077 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1078 }
1079 }
1080
1081 if (ctx->control & ETM_CTRL_TRACE_DATA)
1082 {
1083 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1084 {
1085 int i;
1086 for (i = 0; i < 16; i++)
1087 {
1088 if (instruction.info.load_store_multiple.register_list & (1 << i))
1089 {
1090 uint32_t data;
1091 if (etmv1_data(ctx, 4, &data) != 0)
1092 return ERROR_ETM_ANALYSIS_FAILED;
1093 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1094 }
1095 }
1096 }
1097 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1098 {
1099 uint32_t data;
1100 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1101 return ERROR_ETM_ANALYSIS_FAILED;
1102 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1103 }
1104 }
1105
1106 /* restore data index after consuming BD address and data */
1107 if (pipestat == STAT_BD)
1108 {
1109 ctx->data_index = new_data_index;
1110 ctx->data_half = new_data_half;
1111 }
1112 }
1113
1114 /* adjust PC */
1115 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1116 {
1117 if (((instruction.type == ARM_B) ||
1118 (instruction.type == ARM_BL) ||
1119 (instruction.type == ARM_BLX)) &&
1120 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1121 {
1122 next_pc = instruction.info.b_bl_bx_blx.target_address;
1123 }
1124 else
1125 {
1126 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1127 }
1128 }
1129 else if (pipestat == STAT_IN)
1130 {
1131 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1132 }
1133
1134 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1135 {
1136 char cycles_text[32] = "";
1137
1138 /* if the trace was captured with cycle accurate tracing enabled,
1139 * output the number of cycles since the last executed instruction
1140 */
1141 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1142 {
1143 snprintf(cycles_text, 32, " (%i %s)",
1144 (int)cycles,
1145 (cycles == 1) ? "cycle" : "cycles");
1146 }
1147
1148 command_print(cmd_ctx, "%s%s%s",
1149 instruction.text,
1150 (pipestat == STAT_IN) ? " (not executed)" : "",
1151 cycles_text);
1152
1153 ctx->current_pc = next_pc;
1154
1155 /* packets for an instruction don't start on or before the preceding
1156 * functional pipestat (i.e. other than WT or TD)
1157 */
1158 if (ctx->data_index <= ctx->pipe_index)
1159 {
1160 ctx->data_index = ctx->pipe_index + 1;
1161 ctx->data_half = 0;
1162 }
1163 }
1164
1165 ctx->pipe_index += 1;
1166 }
1167
1168 return ERROR_OK;
1169 }
1170
1171 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1172 uint32_t *mode)
1173 {
1174 uint32_t tracemode;
1175
1176 /* what parts of data access are traced? */
1177 if (strcmp(CMD_ARGV[0], "none") == 0)
1178 tracemode = 0;
1179 else if (strcmp(CMD_ARGV[0], "data") == 0)
1180 tracemode = ETM_CTRL_TRACE_DATA;
1181 else if (strcmp(CMD_ARGV[0], "address") == 0)
1182 tracemode = ETM_CTRL_TRACE_ADDR;
1183 else if (strcmp(CMD_ARGV[0], "all") == 0)
1184 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1185 else
1186 {
1187 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1188 return ERROR_INVALID_ARGUMENTS;
1189 }
1190
1191 uint8_t context_id;
1192 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1193 switch (context_id)
1194 {
1195 case 0:
1196 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1197 break;
1198 case 8:
1199 tracemode |= ETM_CTRL_CONTEXTID_8;
1200 break;
1201 case 16:
1202 tracemode |= ETM_CTRL_CONTEXTID_16;
1203 break;
1204 case 32:
1205 tracemode |= ETM_CTRL_CONTEXTID_32;
1206 break;
1207 default:
1208 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1209 return ERROR_INVALID_ARGUMENTS;
1210 }
1211
1212 bool etmv1_cycle_accurate;
1213 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1214 if (etmv1_cycle_accurate)
1215 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1216
1217 bool etmv1_branch_output;
1218 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1219 if (etmv1_branch_output)
1220 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1221
1222 /* IGNORED:
1223 * - CPRT tracing (coprocessor register transfers)
1224 * - debug request (causes debug entry on trigger)
1225 * - stall on FIFOFULL (preventing tracedata lossage)
1226 */
1227 *mode = tracemode;
1228
1229 return ERROR_OK;
1230 }
1231
1232 COMMAND_HANDLER(handle_etm_tracemode_command)
1233 {
1234 struct target *target = get_current_target(CMD_CTX);
1235 struct arm *arm = target_to_arm(target);
1236 struct etm_context *etm;
1237
1238 if (!is_arm(arm)) {
1239 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1240 return ERROR_FAIL;
1241 }
1242
1243 etm = arm->etm;
1244 if (!etm) {
1245 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1246 return ERROR_FAIL;
1247 }
1248
1249 uint32_t tracemode = etm->control;
1250
1251 switch (CMD_ARGC)
1252 {
1253 case 0:
1254 break;
1255 case 4:
1256 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1257 &tracemode);
1258 break;
1259 default:
1260 command_print(CMD_CTX, "usage: tracemode "
1261 "('none'|'data'|'address'|'all') "
1262 "context_id_bits "
1263 "('enable'|'disable') "
1264 "('enable'|'disable')"
1265 );
1266 return ERROR_FAIL;
1267 }
1268
1269 /**
1270 * todo: fail if parameters were invalid for this hardware,
1271 * or couldn't be written; display actual hardware state...
1272 */
1273
1274 command_print(CMD_CTX, "current tracemode configuration:");
1275
1276 switch (tracemode & ETM_CTRL_TRACE_MASK)
1277 {
1278 default:
1279 command_print(CMD_CTX, "data tracing: none");
1280 break;
1281 case ETM_CTRL_TRACE_DATA:
1282 command_print(CMD_CTX, "data tracing: data only");
1283 break;
1284 case ETM_CTRL_TRACE_ADDR:
1285 command_print(CMD_CTX, "data tracing: address only");
1286 break;
1287 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1288 command_print(CMD_CTX, "data tracing: address and data");
1289 break;
1290 }
1291
1292 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1293 {
1294 case ETM_CTRL_CONTEXTID_NONE:
1295 command_print(CMD_CTX, "contextid tracing: none");
1296 break;
1297 case ETM_CTRL_CONTEXTID_8:
1298 command_print(CMD_CTX, "contextid tracing: 8 bit");
1299 break;
1300 case ETM_CTRL_CONTEXTID_16:
1301 command_print(CMD_CTX, "contextid tracing: 16 bit");
1302 break;
1303 case ETM_CTRL_CONTEXTID_32:
1304 command_print(CMD_CTX, "contextid tracing: 32 bit");
1305 break;
1306 }
1307
1308 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1309 {
1310 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1311 }
1312 else
1313 {
1314 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1315 }
1316
1317 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1318 {
1319 command_print(CMD_CTX, "full branch address output enabled");
1320 }
1321 else
1322 {
1323 command_print(CMD_CTX, "full branch address output disabled");
1324 }
1325
1326 #define TRACEMODE_MASK ( \
1327 ETM_CTRL_CONTEXTID_MASK \
1328 | ETM_CTRL_BRANCH_OUTPUT \
1329 | ETM_CTRL_CYCLE_ACCURATE \
1330 | ETM_CTRL_TRACE_MASK \
1331 )
1332
1333 /* only update ETM_CTRL register if tracemode changed */
1334 if ((etm->control & TRACEMODE_MASK) != tracemode)
1335 {
1336 struct reg *etm_ctrl_reg;
1337
1338 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1339 if (!etm_ctrl_reg)
1340 return ERROR_FAIL;
1341
1342 etm->control &= ~TRACEMODE_MASK;
1343 etm->control |= tracemode & TRACEMODE_MASK;
1344
1345 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1346 etm_store_reg(etm_ctrl_reg);
1347
1348 /* invalidate old trace data */
1349 etm->capture_status = TRACE_IDLE;
1350 if (etm->trace_depth > 0)
1351 {
1352 free(etm->trace_data);
1353 etm->trace_data = NULL;
1354 }
1355 etm->trace_depth = 0;
1356 }
1357
1358 #undef TRACEMODE_MASK
1359
1360 return ERROR_OK;
1361 }
1362
1363 COMMAND_HANDLER(handle_etm_config_command)
1364 {
1365 struct target *target;
1366 struct arm *arm;
1367 uint32_t portmode = 0x0;
1368 struct etm_context *etm_ctx;
1369 int i;
1370
1371 if (CMD_ARGC != 5)
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1373
1374 target = get_target(CMD_ARGV[0]);
1375 if (!target)
1376 {
1377 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1378 return ERROR_FAIL;
1379 }
1380
1381 arm = target_to_arm(target);
1382 if (!is_arm(arm)) {
1383 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1384 target_name(target),
1385 target_type_name(target));
1386 return ERROR_FAIL;
1387 }
1388
1389 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1390 * version we'll be using!! -- so we can't know how to validate
1391 * params yet. "etm config" should likely be *AFTER* hookup...
1392 *
1393 * - Many more widths might be supported ... and we can easily
1394 * check whether our setting "took".
1395 *
1396 * - The "clock" and "mode" bits are interpreted differently.
1397 * See ARM IHI 0014O table 2-17 for the old behavior, and
1398 * table 2-18 for the new. With ETB it's best to specify
1399 * "normal full" ...
1400 */
1401 uint8_t port_width;
1402 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1403 switch (port_width)
1404 {
1405 /* before ETMv3.0 */
1406 case 4:
1407 portmode |= ETM_PORT_4BIT;
1408 break;
1409 case 8:
1410 portmode |= ETM_PORT_8BIT;
1411 break;
1412 case 16:
1413 portmode |= ETM_PORT_16BIT;
1414 break;
1415 /* ETMv3.0 and later*/
1416 case 24:
1417 portmode |= ETM_PORT_24BIT;
1418 break;
1419 case 32:
1420 portmode |= ETM_PORT_32BIT;
1421 break;
1422 case 48:
1423 portmode |= ETM_PORT_48BIT;
1424 break;
1425 case 64:
1426 portmode |= ETM_PORT_64BIT;
1427 break;
1428 case 1:
1429 portmode |= ETM_PORT_1BIT;
1430 break;
1431 case 2:
1432 portmode |= ETM_PORT_2BIT;
1433 break;
1434 default:
1435 command_print(CMD_CTX,
1436 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1437 return ERROR_FAIL;
1438 }
1439
1440 if (strcmp("normal", CMD_ARGV[2]) == 0)
1441 {
1442 portmode |= ETM_PORT_NORMAL;
1443 }
1444 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1445 {
1446 portmode |= ETM_PORT_MUXED;
1447 }
1448 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1449 {
1450 portmode |= ETM_PORT_DEMUXED;
1451 }
1452 else
1453 {
1454 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1455 return ERROR_FAIL;
1456 }
1457
1458 if (strcmp("half", CMD_ARGV[3]) == 0)
1459 {
1460 portmode |= ETM_PORT_HALF_CLOCK;
1461 }
1462 else if (strcmp("full", CMD_ARGV[3]) == 0)
1463 {
1464 portmode |= ETM_PORT_FULL_CLOCK;
1465 }
1466 else
1467 {
1468 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1469 return ERROR_FAIL;
1470 }
1471
1472 etm_ctx = calloc(1, sizeof(struct etm_context));
1473 if (!etm_ctx) {
1474 LOG_DEBUG("out of memory");
1475 return ERROR_FAIL;
1476 }
1477
1478 for (i = 0; etm_capture_drivers[i]; i++)
1479 {
1480 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1481 {
1482 int retval = register_commands(CMD_CTX, NULL,
1483 etm_capture_drivers[i]->commands);
1484 if (ERROR_OK != retval)
1485 {
1486 free(etm_ctx);
1487 return retval;
1488 }
1489
1490 etm_ctx->capture_driver = etm_capture_drivers[i];
1491
1492 break;
1493 }
1494 }
1495
1496 if (!etm_capture_drivers[i])
1497 {
1498 /* no supported capture driver found, don't register an ETM */
1499 free(etm_ctx);
1500 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1501 return ERROR_FAIL;
1502 }
1503
1504 etm_ctx->target = target;
1505 etm_ctx->trace_data = NULL;
1506 etm_ctx->control = portmode;
1507 etm_ctx->core_state = ARM_STATE_ARM;
1508
1509 arm->etm = etm_ctx;
1510
1511 return etm_register_user_commands(CMD_CTX);
1512 }
1513
1514 COMMAND_HANDLER(handle_etm_info_command)
1515 {
1516 struct target *target;
1517 struct arm *arm;
1518 struct etm_context *etm;
1519 struct reg *etm_sys_config_reg;
1520 int max_port_size;
1521 uint32_t config;
1522
1523 target = get_current_target(CMD_CTX);
1524 arm = target_to_arm(target);
1525 if (!is_arm(arm))
1526 {
1527 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1528 return ERROR_FAIL;
1529 }
1530
1531 etm = arm->etm;
1532 if (!etm)
1533 {
1534 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1535 return ERROR_FAIL;
1536 }
1537
1538 command_print(CMD_CTX, "ETM v%d.%d",
1539 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1540 command_print(CMD_CTX, "pairs of address comparators: %i",
1541 (int) (etm->config >> 0) & 0x0f);
1542 command_print(CMD_CTX, "data comparators: %i",
1543 (int) (etm->config >> 4) & 0x0f);
1544 command_print(CMD_CTX, "memory map decoders: %i",
1545 (int) (etm->config >> 8) & 0x1f);
1546 command_print(CMD_CTX, "number of counters: %i",
1547 (int) (etm->config >> 13) & 0x07);
1548 command_print(CMD_CTX, "sequencer %spresent",
1549 (int) (etm->config & (1 << 16)) ? "" : "not ");
1550 command_print(CMD_CTX, "number of ext. inputs: %i",
1551 (int) (etm->config >> 17) & 0x07);
1552 command_print(CMD_CTX, "number of ext. outputs: %i",
1553 (int) (etm->config >> 20) & 0x07);
1554 command_print(CMD_CTX, "FIFO full %spresent",
1555 (int) (etm->config & (1 << 23)) ? "" : "not ");
1556 if (etm->bcd_vers < 0x20)
1557 command_print(CMD_CTX, "protocol version: %i",
1558 (int) (etm->config >> 28) & 0x07);
1559 else {
1560 command_print(CMD_CTX,
1561 "coprocessor and memory access %ssupported",
1562 (etm->config & (1 << 26)) ? "" : "not ");
1563 command_print(CMD_CTX, "trace start/stop %spresent",
1564 (etm->config & (1 << 26)) ? "" : "not ");
1565 command_print(CMD_CTX, "number of context comparators: %i",
1566 (int) (etm->config >> 24) & 0x03);
1567 }
1568
1569 /* SYS_CONFIG isn't present before ETMv1.2 */
1570 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1571 if (!etm_sys_config_reg)
1572 return ERROR_OK;
1573
1574 etm_get_reg(etm_sys_config_reg);
1575 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1576
1577 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1578
1579 max_port_size = config & 0x7;
1580 if (etm->bcd_vers >= 0x30)
1581 max_port_size |= (config >> 6) & 0x08;
1582 switch (max_port_size)
1583 {
1584 /* before ETMv3.0 */
1585 case 0:
1586 max_port_size = 4;
1587 break;
1588 case 1:
1589 max_port_size = 8;
1590 break;
1591 case 2:
1592 max_port_size = 16;
1593 break;
1594 /* ETMv3.0 and later*/
1595 case 3:
1596 max_port_size = 24;
1597 break;
1598 case 4:
1599 max_port_size = 32;
1600 break;
1601 case 5:
1602 max_port_size = 48;
1603 break;
1604 case 6:
1605 max_port_size = 64;
1606 break;
1607 case 8:
1608 max_port_size = 1;
1609 break;
1610 case 9:
1611 max_port_size = 2;
1612 break;
1613 default:
1614 LOG_ERROR("Illegal max_port_size");
1615 return ERROR_FAIL;
1616 }
1617 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1618
1619 if (etm->bcd_vers < 0x30) {
1620 command_print(CMD_CTX, "half-rate clocking %ssupported",
1621 (config & (1 << 3)) ? "" : "not ");
1622 command_print(CMD_CTX, "full-rate clocking %ssupported",
1623 (config & (1 << 4)) ? "" : "not ");
1624 command_print(CMD_CTX, "normal trace format %ssupported",
1625 (config & (1 << 5)) ? "" : "not ");
1626 command_print(CMD_CTX, "multiplex trace format %ssupported",
1627 (config & (1 << 6)) ? "" : "not ");
1628 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1629 (config & (1 << 7)) ? "" : "not ");
1630 } else {
1631 /* REVISIT show which size and format are selected ... */
1632 command_print(CMD_CTX, "current port size %ssupported",
1633 (config & (1 << 10)) ? "" : "not ");
1634 command_print(CMD_CTX, "current trace format %ssupported",
1635 (config & (1 << 11)) ? "" : "not ");
1636 }
1637 if (etm->bcd_vers >= 0x21)
1638 command_print(CMD_CTX, "fetch comparisons %ssupported",
1639 (config & (1 << 17)) ? "not " : "");
1640 command_print(CMD_CTX, "FIFO full %ssupported",
1641 (config & (1 << 8)) ? "" : "not ");
1642
1643 return ERROR_OK;
1644 }
1645
1646 COMMAND_HANDLER(handle_etm_status_command)
1647 {
1648 struct target *target;
1649 struct arm *arm;
1650 struct etm_context *etm;
1651 trace_status_t trace_status;
1652
1653 target = get_current_target(CMD_CTX);
1654 arm = target_to_arm(target);
1655 if (!is_arm(arm))
1656 {
1657 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1658 return ERROR_FAIL;
1659 }
1660
1661 etm = arm->etm;
1662 if (!etm)
1663 {
1664 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1665 return ERROR_FAIL;
1666 }
1667
1668 /* ETM status */
1669 if (etm->bcd_vers >= 0x11) {
1670 struct reg *reg;
1671
1672 reg = etm_reg_lookup(etm, ETM_STATUS);
1673 if (!reg)
1674 return ERROR_FAIL;
1675 if (etm_get_reg(reg) == ERROR_OK) {
1676 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1677
1678 command_print(CMD_CTX, "etm: %s%s%s%s",
1679 /* bit(1) == progbit */
1680 (etm->bcd_vers >= 0x12)
1681 ? ((s & (1 << 1))
1682 ? "disabled" : "enabled")
1683 : "?",
1684 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1685 ? " triggered" : "",
1686 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1687 ? " start/stop" : "",
1688 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1689 ? " untraced-overflow" : "");
1690 } /* else ignore and try showing trace port status */
1691 }
1692
1693 /* Trace Port Driver status */
1694 trace_status = etm->capture_driver->status(etm);
1695 if (trace_status == TRACE_IDLE)
1696 {
1697 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1698 }
1699 else
1700 {
1701 static char *completed = " completed";
1702 static char *running = " is running";
1703 static char *overflowed = ", overflowed";
1704 static char *triggered = ", triggered";
1705
1706 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1707 etm->capture_driver->name,
1708 (trace_status & TRACE_RUNNING) ? running : completed,
1709 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1710 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1711
1712 if (etm->trace_depth > 0)
1713 {
1714 command_print(CMD_CTX, "%i frames of trace data read",
1715 (int)(etm->trace_depth));
1716 }
1717 }
1718
1719 return ERROR_OK;
1720 }
1721
1722 COMMAND_HANDLER(handle_etm_image_command)
1723 {
1724 struct target *target;
1725 struct arm *arm;
1726 struct etm_context *etm_ctx;
1727
1728 if (CMD_ARGC < 1)
1729 {
1730 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1731 return ERROR_FAIL;
1732 }
1733
1734 target = get_current_target(CMD_CTX);
1735 arm = target_to_arm(target);
1736 if (!is_arm(arm))
1737 {
1738 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1739 return ERROR_FAIL;
1740 }
1741
1742 etm_ctx = arm->etm;
1743 if (!etm_ctx)
1744 {
1745 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1746 return ERROR_FAIL;
1747 }
1748
1749 if (etm_ctx->image)
1750 {
1751 image_close(etm_ctx->image);
1752 free(etm_ctx->image);
1753 command_print(CMD_CTX, "previously loaded image found and closed");
1754 }
1755
1756 etm_ctx->image = malloc(sizeof(struct image));
1757 etm_ctx->image->base_address_set = 0;
1758 etm_ctx->image->start_address_set = 0;
1759
1760 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1761 if (CMD_ARGC >= 2)
1762 {
1763 etm_ctx->image->base_address_set = 1;
1764 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1765 }
1766 else
1767 {
1768 etm_ctx->image->base_address_set = 0;
1769 }
1770
1771 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1772 {
1773 free(etm_ctx->image);
1774 etm_ctx->image = NULL;
1775 return ERROR_FAIL;
1776 }
1777
1778 return ERROR_OK;
1779 }
1780
1781 COMMAND_HANDLER(handle_etm_dump_command)
1782 {
1783 struct fileio file;
1784 struct target *target;
1785 struct arm *arm;
1786 struct etm_context *etm_ctx;
1787 uint32_t i;
1788
1789 if (CMD_ARGC != 1)
1790 {
1791 command_print(CMD_CTX, "usage: etm dump <file>");
1792 return ERROR_FAIL;
1793 }
1794
1795 target = get_current_target(CMD_CTX);
1796 arm = target_to_arm(target);
1797 if (!is_arm(arm))
1798 {
1799 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1800 return ERROR_FAIL;
1801 }
1802
1803 etm_ctx = arm->etm;
1804 if (!etm_ctx)
1805 {
1806 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1807 return ERROR_FAIL;
1808 }
1809
1810 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1811 {
1812 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1813 return ERROR_OK;
1814 }
1815
1816 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1817 {
1818 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1819 command_print(CMD_CTX, "trace capture not completed");
1820 return ERROR_FAIL;
1821 }
1822
1823 /* read the trace data if it wasn't read already */
1824 if (etm_ctx->trace_depth == 0)
1825 etm_ctx->capture_driver->read_trace(etm_ctx);
1826
1827 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1828 {
1829 return ERROR_FAIL;
1830 }
1831
1832 fileio_write_u32(&file, etm_ctx->capture_status);
1833 fileio_write_u32(&file, etm_ctx->control);
1834 fileio_write_u32(&file, etm_ctx->trace_depth);
1835
1836 for (i = 0; i < etm_ctx->trace_depth; i++)
1837 {
1838 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1839 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1840 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1841 }
1842
1843 fileio_close(&file);
1844
1845 return ERROR_OK;
1846 }
1847
1848 COMMAND_HANDLER(handle_etm_load_command)
1849 {
1850 struct fileio file;
1851 struct target *target;
1852 struct arm *arm;
1853 struct etm_context *etm_ctx;
1854 uint32_t i;
1855
1856 if (CMD_ARGC != 1)
1857 {
1858 command_print(CMD_CTX, "usage: etm load <file>");
1859 return ERROR_FAIL;
1860 }
1861
1862 target = get_current_target(CMD_CTX);
1863 arm = target_to_arm(target);
1864 if (!is_arm(arm))
1865 {
1866 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1867 return ERROR_FAIL;
1868 }
1869
1870 etm_ctx = arm->etm;
1871 if (!etm_ctx)
1872 {
1873 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1874 return ERROR_FAIL;
1875 }
1876
1877 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1878 {
1879 command_print(CMD_CTX, "trace capture running, stop first");
1880 return ERROR_FAIL;
1881 }
1882
1883 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1884 {
1885 return ERROR_FAIL;
1886 }
1887
1888 if (file.size % 4)
1889 {
1890 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1891 fileio_close(&file);
1892 return ERROR_FAIL;
1893 }
1894
1895 if (etm_ctx->trace_depth > 0)
1896 {
1897 free(etm_ctx->trace_data);
1898 etm_ctx->trace_data = NULL;
1899 }
1900
1901 {
1902 uint32_t tmp;
1903 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1904 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1905 fileio_read_u32(&file, &etm_ctx->trace_depth);
1906 }
1907 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1908 if (etm_ctx->trace_data == NULL)
1909 {
1910 command_print(CMD_CTX, "not enough memory to perform operation");
1911 fileio_close(&file);
1912 return ERROR_FAIL;
1913 }
1914
1915 for (i = 0; i < etm_ctx->trace_depth; i++)
1916 {
1917 uint32_t pipestat, packet, flags;
1918 fileio_read_u32(&file, &pipestat);
1919 fileio_read_u32(&file, &packet);
1920 fileio_read_u32(&file, &flags);
1921 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1922 etm_ctx->trace_data[i].packet = packet & 0xffff;
1923 etm_ctx->trace_data[i].flags = flags;
1924 }
1925
1926 fileio_close(&file);
1927
1928 return ERROR_OK;
1929 }
1930
1931 COMMAND_HANDLER(handle_etm_start_command)
1932 {
1933 struct target *target;
1934 struct arm *arm;
1935 struct etm_context *etm_ctx;
1936 struct reg *etm_ctrl_reg;
1937
1938 target = get_current_target(CMD_CTX);
1939 arm = target_to_arm(target);
1940 if (!is_arm(arm))
1941 {
1942 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1943 return ERROR_FAIL;
1944 }
1945
1946 etm_ctx = arm->etm;
1947 if (!etm_ctx)
1948 {
1949 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1950 return ERROR_FAIL;
1951 }
1952
1953 /* invalidate old tracing data */
1954 etm_ctx->capture_status = TRACE_IDLE;
1955 if (etm_ctx->trace_depth > 0)
1956 {
1957 free(etm_ctx->trace_data);
1958 etm_ctx->trace_data = NULL;
1959 }
1960 etm_ctx->trace_depth = 0;
1961
1962 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1963 if (!etm_ctrl_reg)
1964 return ERROR_FAIL;
1965
1966 etm_get_reg(etm_ctrl_reg);
1967
1968 /* Clear programming bit (10), set port selection bit (11) */
1969 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1970
1971 etm_store_reg(etm_ctrl_reg);
1972 jtag_execute_queue();
1973
1974 etm_ctx->capture_driver->start_capture(etm_ctx);
1975
1976 return ERROR_OK;
1977 }
1978
1979 COMMAND_HANDLER(handle_etm_stop_command)
1980 {
1981 struct target *target;
1982 struct arm *arm;
1983 struct etm_context *etm_ctx;
1984 struct reg *etm_ctrl_reg;
1985
1986 target = get_current_target(CMD_CTX);
1987 arm = target_to_arm(target);
1988 if (!is_arm(arm))
1989 {
1990 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1991 return ERROR_FAIL;
1992 }
1993
1994 etm_ctx = arm->etm;
1995 if (!etm_ctx)
1996 {
1997 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1998 return ERROR_FAIL;
1999 }
2000
2001 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2002 if (!etm_ctrl_reg)
2003 return ERROR_FAIL;
2004
2005 etm_get_reg(etm_ctrl_reg);
2006
2007 /* Set programming bit (10), clear port selection bit (11) */
2008 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2009
2010 etm_store_reg(etm_ctrl_reg);
2011 jtag_execute_queue();
2012
2013 etm_ctx->capture_driver->stop_capture(etm_ctx);
2014
2015 return ERROR_OK;
2016 }
2017
2018 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2019 {
2020 struct target *target;
2021 struct arm *arm;
2022 struct etm_context *etm;
2023
2024 target = get_current_target(CMD_CTX);
2025 arm = target_to_arm(target);
2026 if (!is_arm(arm))
2027 {
2028 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2029 target_name(target));
2030 return ERROR_FAIL;
2031 }
2032
2033 etm = arm->etm;
2034 if (!etm)
2035 {
2036 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2037 target_name(target));
2038 return ERROR_FAIL;
2039 }
2040
2041 if (CMD_ARGC == 1) {
2042 struct reg *etm_ctrl_reg;
2043 bool dbgrq;
2044
2045 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2046 if (!etm_ctrl_reg)
2047 return ERROR_FAIL;
2048
2049 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2050 if (dbgrq)
2051 etm->control |= ETM_CTRL_DBGRQ;
2052 else
2053 etm->control &= ~ETM_CTRL_DBGRQ;
2054
2055 /* etm->control will be written to hardware
2056 * the next time an "etm start" is issued.
2057 */
2058 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2059 }
2060
2061 command_print(CMD_CTX, "ETM: %s debug halt",
2062 (etm->control & ETM_CTRL_DBGRQ)
2063 ? "triggers"
2064 : "does not trigger");
2065 return ERROR_OK;
2066 }
2067
2068 COMMAND_HANDLER(handle_etm_analyze_command)
2069 {
2070 struct target *target;
2071 struct arm *arm;
2072 struct etm_context *etm_ctx;
2073 int retval;
2074
2075 target = get_current_target(CMD_CTX);
2076 arm = target_to_arm(target);
2077 if (!is_arm(arm))
2078 {
2079 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2080 return ERROR_FAIL;
2081 }
2082
2083 etm_ctx = arm->etm;
2084 if (!etm_ctx)
2085 {
2086 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2087 return ERROR_FAIL;
2088 }
2089
2090 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2091 {
2092 switch (retval)
2093 {
2094 case ERROR_ETM_ANALYSIS_FAILED:
2095 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2096 break;
2097 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2098 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2099 break;
2100 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2101 command_print(CMD_CTX, "no image available for trace analysis");
2102 break;
2103 default:
2104 command_print(CMD_CTX, "unknown error: %i", retval);
2105 }
2106 }
2107
2108 return retval;
2109 }
2110
2111 static const struct command_registration etm_config_command_handlers[] = {
2112 {
2113 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2114 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2115 *
2116 * Also, these parameters don't match ETM v3+ modules...
2117 */
2118 .name = "config",
2119 .handler = handle_etm_config_command,
2120 .mode = COMMAND_CONFIG,
2121 .help = "Set up ETM output port.",
2122 .usage = "target port_width port_mode clocking capture_driver",
2123 },
2124 COMMAND_REGISTRATION_DONE
2125 };
2126 const struct command_registration etm_command_handlers[] = {
2127 {
2128 .name = "etm",
2129 .mode = COMMAND_ANY,
2130 .help = "Emebdded Trace Macrocell command group",
2131 .chain = etm_config_command_handlers,
2132 },
2133 COMMAND_REGISTRATION_DONE
2134 };
2135
2136 static const struct command_registration etm_exec_command_handlers[] = {
2137 {
2138 .name = "tracemode",
2139 .handler = handle_etm_tracemode_command,
2140 .mode = COMMAND_EXEC,
2141 .help = "configure/display trace mode",
2142 .usage = "('none'|'data'|'address'|'all') "
2143 "context_id_bits "
2144 "['enable'|'disable'] "
2145 "['enable'|'disable']",
2146 },
2147 {
2148 .name = "info",
2149 .handler = handle_etm_info_command,
2150 .mode = COMMAND_EXEC,
2151 .help = "display info about the current target's ETM",
2152 },
2153 {
2154 .name = "status",
2155 .handler = handle_etm_status_command,
2156 .mode = COMMAND_EXEC,
2157 .help = "display current target's ETM status",
2158 },
2159 {
2160 .name = "start",
2161 .handler = handle_etm_start_command,
2162 .mode = COMMAND_EXEC,
2163 .help = "start ETM trace collection",
2164 },
2165 {
2166 .name = "stop",
2167 .handler = handle_etm_stop_command,
2168 .mode = COMMAND_EXEC,
2169 .help = "stop ETM trace collection",
2170 },
2171 {
2172 .name = "trigger_debug",
2173 .handler = handle_etm_trigger_debug_command,
2174 .mode = COMMAND_EXEC,
2175 .help = "enable/disable debug entry on trigger",
2176 .usage = "['enable'|'disable']",
2177 },
2178 {
2179 .name = "analyze",
2180 .handler = handle_etm_analyze_command,
2181 .mode = COMMAND_EXEC,
2182 .help = "analyze collected ETM trace",
2183 },
2184 {
2185 .name = "image",
2186 .handler = handle_etm_image_command,
2187 .mode = COMMAND_EXEC,
2188 .help = "load image from file with optional offset",
2189 .usage = "filename [offset]",
2190 },
2191 {
2192 .name = "dump",
2193 .handler = handle_etm_dump_command,
2194 .mode = COMMAND_EXEC,
2195 .help = "dump captured trace data to file",
2196 .usage = "filename",
2197 },
2198 {
2199 .name = "load",
2200 .handler = handle_etm_load_command,
2201 .mode = COMMAND_EXEC,
2202 .help = "load trace data for analysis <file>",
2203 },
2204 COMMAND_REGISTRATION_DONE
2205 };
2206
2207 static int etm_register_user_commands(struct command_context *cmd_ctx)
2208 {
2209 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2210 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2211 }
add intel's jflashmm functionality to openocd