MIPS: remove unused arg from mips_ejtag_set_instr
[openocd/jflash.git] / src / target / armv4_5.h
blobbacdb72e656a36cb89cdb33a0b34aed68a656add
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV4_5_H
27 #define ARMV4_5_H
29 /* This stuff "knows" that its callers aren't talking
30 * to microcontroller profile (current Cortex-M) parts.
31 * We want to phase it out so core code can be shared.
34 /* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
35 * index into the armv4_5_core_reg_map array. Its remaining users are
36 * remnants which could as easily walk * the register cache directly as
37 * use the expensive ARMV4_5_CORE_REG_MODE() macro.
39 int arm_mode_to_number(enum arm_mode mode);
40 enum arm_mode armv4_5_number_to_mode(int number);
42 extern const int armv4_5_core_reg_map[8][17];
44 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
45 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
47 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
48 enum { ARMV4_5_CPSR = 31, };
50 #endif /* ARMV4_5_H */