ARMv7M: use software breakpoints for algorithms
[openocd/jflash.git] / src / flash / nor / stm32x.c
blob53fc4ea23a56ffcd9ebd81a2013d10fb5d5f53e8
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
34 static int stm32x_mass_erase(struct flash_bank *bank);
36 /* flash bank stm32x <base> <size> 0 0 <target#>
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
40 struct stm32x_flash_bank *stm32x_info;
42 if (CMD_ARGC < 6)
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
54 return ERROR_OK;
57 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
59 struct target *target = bank->target;
60 uint32_t status;
62 target_read_u32(target, STM32_FLASH_SR, &status);
64 return status;
67 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
69 struct target *target = bank->target;
70 uint32_t status;
72 /* wait for busy to clear */
73 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 alive_sleep(1);
78 /* Clear but report errors */
79 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
81 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
83 return status;
86 static int stm32x_read_options(struct flash_bank *bank)
88 uint32_t optiondata;
89 struct stm32x_flash_bank *stm32x_info = NULL;
90 struct target *target = bank->target;
92 stm32x_info = bank->driver_priv;
94 /* read current option bytes */
95 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
97 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
98 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
100 if (optiondata & (1 << OPT_READOUT))
101 LOG_INFO("Device Security Bit Set");
103 /* each bit refers to a 4bank protection */
104 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
106 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
107 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
108 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
109 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
111 return ERROR_OK;
114 static int stm32x_erase_options(struct flash_bank *bank)
116 struct stm32x_flash_bank *stm32x_info = NULL;
117 struct target *target = bank->target;
118 uint32_t status;
120 stm32x_info = bank->driver_priv;
122 /* read current options */
123 stm32x_read_options(bank);
125 /* unlock flash registers */
126 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
127 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
129 /* unlock option flash registers */
130 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
131 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
133 /* erase option bytes */
134 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
135 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
137 status = stm32x_wait_status_busy(bank, 10);
139 if (status & FLASH_WRPRTERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141 if (status & FLASH_PGERR)
142 return ERROR_FLASH_OPERATION_FAILED;
144 /* clear readout protection and complementary option bytes
145 * this will also force a device unlock if set */
146 stm32x_info->option_bytes.RDP = 0x5AA5;
148 return ERROR_OK;
151 static int stm32x_write_options(struct flash_bank *bank)
153 struct stm32x_flash_bank *stm32x_info = NULL;
154 struct target *target = bank->target;
155 uint32_t status;
157 stm32x_info = bank->driver_priv;
159 /* unlock flash registers */
160 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
161 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
163 /* unlock option flash registers */
164 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
165 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
167 /* program option bytes */
168 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
170 /* write user option byte */
171 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
173 status = stm32x_wait_status_busy(bank, 10);
175 if (status & FLASH_WRPRTERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177 if (status & FLASH_PGERR)
178 return ERROR_FLASH_OPERATION_FAILED;
180 /* write protection byte 1 */
181 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
183 status = stm32x_wait_status_busy(bank, 10);
185 if (status & FLASH_WRPRTERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & FLASH_PGERR)
188 return ERROR_FLASH_OPERATION_FAILED;
190 /* write protection byte 2 */
191 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
193 status = stm32x_wait_status_busy(bank, 10);
195 if (status & FLASH_WRPRTERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197 if (status & FLASH_PGERR)
198 return ERROR_FLASH_OPERATION_FAILED;
200 /* write protection byte 3 */
201 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
203 status = stm32x_wait_status_busy(bank, 10);
205 if (status & FLASH_WRPRTERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207 if (status & FLASH_PGERR)
208 return ERROR_FLASH_OPERATION_FAILED;
210 /* write protection byte 4 */
211 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
213 status = stm32x_wait_status_busy(bank, 10);
215 if (status & FLASH_WRPRTERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217 if (status & FLASH_PGERR)
218 return ERROR_FLASH_OPERATION_FAILED;
220 /* write readout protection bit */
221 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
223 status = stm32x_wait_status_busy(bank, 10);
225 if (status & FLASH_WRPRTERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227 if (status & FLASH_PGERR)
228 return ERROR_FLASH_OPERATION_FAILED;
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
232 return ERROR_OK;
235 static int stm32x_protect_check(struct flash_bank *bank)
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
240 uint32_t protection;
241 int i, s;
242 int num_bits;
243 int set;
245 if (target->state != TARGET_HALTED)
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
259 if (stm32x_info->ppage_size == 2)
261 /* high density flash/connectivity line protection */
263 set = 1;
265 if (protection & (1 << 31))
266 set = 0;
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
272 bank->sectors[s].is_protected = set;
275 if (bank->num_sectors > 61)
276 num_bits = 31;
278 for (i = 0; i < num_bits; i++)
280 set = 1;
282 if (protection & (1 << i))
283 set = 0;
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
289 else
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
294 set = 1;
296 if (protection & (1 << i))
297 set = 0;
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
304 return ERROR_OK;
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
309 struct target *target = bank->target;
310 int i;
311 uint32_t status;
313 if (bank->target->state != TARGET_HALTED)
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
319 if ((first == 0) && (last == (bank->num_sectors - 1)))
321 return stm32x_mass_erase(bank);
324 /* unlock flash registers */
325 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
326 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
328 for (i = first; i <= last; i++)
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
331 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
332 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
334 status = stm32x_wait_status_busy(bank, 10);
336 if (status & FLASH_WRPRTERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 if (status & FLASH_PGERR)
339 return ERROR_FLASH_OPERATION_FAILED;
340 bank->sectors[i].is_erased = 1;
343 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
345 return ERROR_OK;
348 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
350 struct stm32x_flash_bank *stm32x_info = NULL;
351 struct target *target = bank->target;
352 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
353 int i, reg, bit;
354 int status;
355 uint32_t protection;
357 stm32x_info = bank->driver_priv;
359 if (target->state != TARGET_HALTED)
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
365 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
367 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
368 return ERROR_FLASH_SECTOR_INVALID;
371 /* medium density - each bit refers to a 4bank protection
372 * high density - each bit refers to a 2bank protection */
373 target_read_u32(target, STM32_FLASH_WRPR, &protection);
375 prot_reg[0] = (uint16_t)protection;
376 prot_reg[1] = (uint16_t)(protection >> 8);
377 prot_reg[2] = (uint16_t)(protection >> 16);
378 prot_reg[3] = (uint16_t)(protection >> 24);
380 if (stm32x_info->ppage_size == 2)
382 /* high density flash */
384 /* bit 7 controls sector 62 - 255 protection */
385 if (last > 61)
387 if (set)
388 prot_reg[3] &= ~(1 << 7);
389 else
390 prot_reg[3] |= (1 << 7);
393 if (first > 61)
394 first = 62;
395 if (last > 61)
396 last = 61;
398 for (i = first; i <= last; i++)
400 reg = (i / stm32x_info->ppage_size) / 8;
401 bit = (i / stm32x_info->ppage_size) - (reg * 8);
403 if (set)
404 prot_reg[reg] &= ~(1 << bit);
405 else
406 prot_reg[reg] |= (1 << bit);
409 else
411 /* medium density flash */
412 for (i = first; i <= last; i++)
414 reg = (i / stm32x_info->ppage_size) / 8;
415 bit = (i / stm32x_info->ppage_size) - (reg * 8);
417 if (set)
418 prot_reg[reg] &= ~(1 << bit);
419 else
420 prot_reg[reg] |= (1 << bit);
424 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
425 return status;
427 stm32x_info->option_bytes.protection[0] = prot_reg[0];
428 stm32x_info->option_bytes.protection[1] = prot_reg[1];
429 stm32x_info->option_bytes.protection[2] = prot_reg[2];
430 stm32x_info->option_bytes.protection[3] = prot_reg[3];
432 return stm32x_write_options(bank);
435 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
437 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
438 struct target *target = bank->target;
439 uint32_t buffer_size = 16384;
440 struct working_area *source;
441 uint32_t address = bank->base + offset;
442 struct reg_param reg_params[4];
443 struct armv7m_algorithm armv7m_info;
444 int retval = ERROR_OK;
446 uint8_t stm32x_flash_write_code[] = {
447 /* write: */
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
451 0x23, 0x60, /* str r3, [r4, #0] */
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
454 /* busy: */
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
457 0xFB, 0xD0, /* beq busy */
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
459 0x01, 0xD1, /* bne exit */
460 0x01, 0x3A, /* subs r2, r2, #1 */
461 0xED, 0xD1, /* bne write */
462 0x00, 0xBE, /* bkpt #0 */
463 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
464 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
467 /* flash write code */
468 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
470 LOG_WARNING("no working area available, can't do block memory writes");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
474 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
475 return retval;
477 /* memory buffer */
478 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
480 buffer_size /= 2;
481 if (buffer_size <= 256)
483 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
484 if (stm32x_info->write_algorithm)
485 target_free_working_area(target, stm32x_info->write_algorithm);
487 LOG_WARNING("no large enough working area available, can't do block memory writes");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
492 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
493 armv7m_info.core_mode = ARMV7M_MODE_ANY;
495 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
496 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
497 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
498 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
500 while (count > 0)
502 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
504 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
505 break;
507 buf_set_u32(reg_params[0].value, 0, 32, source->address);
508 buf_set_u32(reg_params[1].value, 0, 32, address);
509 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
511 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
512 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
514 LOG_ERROR("error executing stm32x flash write algorithm");
515 retval = ERROR_FLASH_OPERATION_FAILED;
516 break;
519 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
521 LOG_ERROR("flash memory not erased before writing");
522 /* Clear but report errors */
523 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
524 retval = ERROR_FLASH_OPERATION_FAILED;
525 break;
528 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
530 LOG_ERROR("flash memory write protected");
531 /* Clear but report errors */
532 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
533 retval = ERROR_FLASH_OPERATION_FAILED;
534 break;
537 buffer += thisrun_count * 2;
538 address += thisrun_count * 2;
539 count -= thisrun_count;
542 target_free_working_area(target, source);
543 target_free_working_area(target, stm32x_info->write_algorithm);
545 destroy_reg_param(&reg_params[0]);
546 destroy_reg_param(&reg_params[1]);
547 destroy_reg_param(&reg_params[2]);
548 destroy_reg_param(&reg_params[3]);
550 return retval;
553 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
555 struct target *target = bank->target;
556 uint32_t words_remaining = (count / 2);
557 uint32_t bytes_remaining = (count & 0x00000001);
558 uint32_t address = bank->base + offset;
559 uint32_t bytes_written = 0;
560 uint8_t status;
561 int retval;
563 if (bank->target->state != TARGET_HALTED)
565 LOG_ERROR("Target not halted");
566 return ERROR_TARGET_NOT_HALTED;
569 if (offset & 0x1)
571 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
572 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
575 /* unlock flash registers */
576 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
577 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
579 /* multiple half words (2-byte) to be programmed? */
580 if (words_remaining > 0)
582 /* try using a block write */
583 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
585 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
587 /* if block write failed (no sufficient working area),
588 * we use normal (slow) single dword accesses */
589 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
591 else if (retval == ERROR_FLASH_OPERATION_FAILED)
593 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
594 return ERROR_FLASH_OPERATION_FAILED;
597 else
599 buffer += words_remaining * 2;
600 address += words_remaining * 2;
601 words_remaining = 0;
605 while (words_remaining > 0)
607 uint16_t value;
608 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
610 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
611 target_write_u16(target, address, value);
613 status = stm32x_wait_status_busy(bank, 5);
615 if (status & FLASH_WRPRTERR)
617 LOG_ERROR("flash memory not erased before writing");
618 return ERROR_FLASH_OPERATION_FAILED;
620 if (status & FLASH_PGERR)
622 LOG_ERROR("flash memory write protected");
623 return ERROR_FLASH_OPERATION_FAILED;
626 bytes_written += 2;
627 words_remaining--;
628 address += 2;
631 if (bytes_remaining)
633 uint16_t value = 0xffff;
634 memcpy(&value, buffer + bytes_written, bytes_remaining);
636 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
637 target_write_u16(target, address, value);
639 status = stm32x_wait_status_busy(bank, 5);
641 if (status & FLASH_WRPRTERR)
643 LOG_ERROR("flash memory not erased before writing");
644 return ERROR_FLASH_OPERATION_FAILED;
646 if (status & FLASH_PGERR)
648 LOG_ERROR("flash memory write protected");
649 return ERROR_FLASH_OPERATION_FAILED;
653 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
655 return ERROR_OK;
658 static int stm32x_probe(struct flash_bank *bank)
660 struct target *target = bank->target;
661 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
662 int i;
663 uint16_t num_pages;
664 uint32_t device_id;
665 int page_size;
667 if (bank->target->state != TARGET_HALTED)
669 LOG_ERROR("Target not halted");
670 return ERROR_TARGET_NOT_HALTED;
673 stm32x_info->probed = 0;
675 /* read stm32 device id register */
676 target_read_u32(target, 0xE0042000, &device_id);
677 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
679 /* get flash size from target */
680 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
682 /* failed reading flash size, default to max target family */
683 num_pages = 0xffff;
686 if ((device_id & 0x7ff) == 0x410)
688 /* medium density - we have 1k pages
689 * 4 pages for a protection area */
690 page_size = 1024;
691 stm32x_info->ppage_size = 4;
693 /* check for early silicon */
694 if (num_pages == 0xffff)
696 /* number of sectors incorrect on revA */
697 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
698 num_pages = 128;
701 else if ((device_id & 0x7ff) == 0x412)
703 /* low density - we have 1k pages
704 * 4 pages for a protection area */
705 page_size = 1024;
706 stm32x_info->ppage_size = 4;
708 /* check for early silicon */
709 if (num_pages == 0xffff)
711 /* number of sectors incorrect on revA */
712 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
713 num_pages = 32;
716 else if ((device_id & 0x7ff) == 0x414)
718 /* high density - we have 2k pages
719 * 2 pages for a protection area */
720 page_size = 2048;
721 stm32x_info->ppage_size = 2;
723 /* check for early silicon */
724 if (num_pages == 0xffff)
726 /* number of sectors incorrect on revZ */
727 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
728 num_pages = 512;
731 else if ((device_id & 0x7ff) == 0x418)
733 /* connectivity line density - we have 2k pages
734 * 2 pages for a protection area */
735 page_size = 2048;
736 stm32x_info->ppage_size = 2;
738 /* check for early silicon */
739 if (num_pages == 0xffff)
741 /* number of sectors incorrect on revZ */
742 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
743 num_pages = 256;
746 else
748 LOG_WARNING("Cannot identify target as a STM32 family.");
749 return ERROR_FLASH_OPERATION_FAILED;
752 LOG_INFO("flash size = %dkbytes", num_pages);
754 /* calculate numbers of pages */
755 num_pages /= (page_size / 1024);
757 bank->base = 0x08000000;
758 bank->size = (num_pages * page_size);
759 bank->num_sectors = num_pages;
760 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
762 for (i = 0; i < num_pages; i++)
764 bank->sectors[i].offset = i * page_size;
765 bank->sectors[i].size = page_size;
766 bank->sectors[i].is_erased = -1;
767 bank->sectors[i].is_protected = 1;
770 stm32x_info->probed = 1;
772 return ERROR_OK;
775 static int stm32x_auto_probe(struct flash_bank *bank)
777 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
778 if (stm32x_info->probed)
779 return ERROR_OK;
780 return stm32x_probe(bank);
783 #if 0
784 COMMAND_HANDLER(stm32x_handle_part_id_command)
786 return ERROR_OK;
788 #endif
790 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
792 struct target *target = bank->target;
793 uint32_t device_id;
794 int printed;
796 /* read stm32 device id register */
797 target_read_u32(target, 0xE0042000, &device_id);
799 if ((device_id & 0x7ff) == 0x410)
801 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
802 buf += printed;
803 buf_size -= printed;
805 switch (device_id >> 16)
807 case 0x0000:
808 snprintf(buf, buf_size, "A");
809 break;
811 case 0x2000:
812 snprintf(buf, buf_size, "B");
813 break;
815 case 0x2001:
816 snprintf(buf, buf_size, "Z");
817 break;
819 case 0x2003:
820 snprintf(buf, buf_size, "Y");
821 break;
823 default:
824 snprintf(buf, buf_size, "unknown");
825 break;
828 else if ((device_id & 0x7ff) == 0x412)
830 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
831 buf += printed;
832 buf_size -= printed;
834 switch (device_id >> 16)
836 case 0x1000:
837 snprintf(buf, buf_size, "A");
838 break;
840 default:
841 snprintf(buf, buf_size, "unknown");
842 break;
845 else if ((device_id & 0x7ff) == 0x414)
847 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
848 buf += printed;
849 buf_size -= printed;
851 switch (device_id >> 16)
853 case 0x1000:
854 snprintf(buf, buf_size, "A");
855 break;
857 case 0x1001:
858 snprintf(buf, buf_size, "Z");
859 break;
861 default:
862 snprintf(buf, buf_size, "unknown");
863 break;
866 else if ((device_id & 0x7ff) == 0x418)
868 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
869 buf += printed;
870 buf_size -= printed;
872 switch (device_id >> 16)
874 case 0x1000:
875 snprintf(buf, buf_size, "A");
876 break;
878 case 0x1001:
879 snprintf(buf, buf_size, "Z");
880 break;
882 default:
883 snprintf(buf, buf_size, "unknown");
884 break;
887 else
889 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
890 return ERROR_FLASH_OPERATION_FAILED;
893 return ERROR_OK;
896 COMMAND_HANDLER(stm32x_handle_lock_command)
898 struct target *target = NULL;
899 struct stm32x_flash_bank *stm32x_info = NULL;
901 if (CMD_ARGC < 1)
903 command_print(CMD_CTX, "stm32x lock <bank>");
904 return ERROR_OK;
907 struct flash_bank *bank;
908 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
909 if (ERROR_OK != retval)
910 return retval;
912 stm32x_info = bank->driver_priv;
914 target = bank->target;
916 if (target->state != TARGET_HALTED)
918 LOG_ERROR("Target not halted");
919 return ERROR_TARGET_NOT_HALTED;
922 if (stm32x_erase_options(bank) != ERROR_OK)
924 command_print(CMD_CTX, "stm32x failed to erase options");
925 return ERROR_OK;
928 /* set readout protection */
929 stm32x_info->option_bytes.RDP = 0;
931 if (stm32x_write_options(bank) != ERROR_OK)
933 command_print(CMD_CTX, "stm32x failed to lock device");
934 return ERROR_OK;
937 command_print(CMD_CTX, "stm32x locked");
939 return ERROR_OK;
942 COMMAND_HANDLER(stm32x_handle_unlock_command)
944 struct target *target = NULL;
945 struct stm32x_flash_bank *stm32x_info = NULL;
947 if (CMD_ARGC < 1)
949 command_print(CMD_CTX, "stm32x unlock <bank>");
950 return ERROR_OK;
953 struct flash_bank *bank;
954 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
955 if (ERROR_OK != retval)
956 return retval;
958 stm32x_info = bank->driver_priv;
960 target = bank->target;
962 if (target->state != TARGET_HALTED)
964 LOG_ERROR("Target not halted");
965 return ERROR_TARGET_NOT_HALTED;
968 if (stm32x_erase_options(bank) != ERROR_OK)
970 command_print(CMD_CTX, "stm32x failed to unlock device");
971 return ERROR_OK;
974 if (stm32x_write_options(bank) != ERROR_OK)
976 command_print(CMD_CTX, "stm32x failed to lock device");
977 return ERROR_OK;
980 command_print(CMD_CTX, "stm32x unlocked.\n"
981 "INFO: a reset or power cycle is required "
982 "for the new settings to take effect.");
984 return ERROR_OK;
987 COMMAND_HANDLER(stm32x_handle_options_read_command)
989 uint32_t optionbyte;
990 struct target *target = NULL;
991 struct stm32x_flash_bank *stm32x_info = NULL;
993 if (CMD_ARGC < 1)
995 command_print(CMD_CTX, "stm32x options_read <bank>");
996 return ERROR_OK;
999 struct flash_bank *bank;
1000 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1001 if (ERROR_OK != retval)
1002 return retval;
1004 stm32x_info = bank->driver_priv;
1006 target = bank->target;
1008 if (target->state != TARGET_HALTED)
1010 LOG_ERROR("Target not halted");
1011 return ERROR_TARGET_NOT_HALTED;
1014 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1015 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1017 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1018 command_print(CMD_CTX, "Option Byte Complement Error");
1020 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1021 command_print(CMD_CTX, "Readout Protection On");
1022 else
1023 command_print(CMD_CTX, "Readout Protection Off");
1025 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1026 command_print(CMD_CTX, "Software Watchdog");
1027 else
1028 command_print(CMD_CTX, "Hardware Watchdog");
1030 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1031 command_print(CMD_CTX, "Stop: No reset generated");
1032 else
1033 command_print(CMD_CTX, "Stop: Reset generated");
1035 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1036 command_print(CMD_CTX, "Standby: No reset generated");
1037 else
1038 command_print(CMD_CTX, "Standby: Reset generated");
1040 return ERROR_OK;
1043 COMMAND_HANDLER(stm32x_handle_options_write_command)
1045 struct target *target = NULL;
1046 struct stm32x_flash_bank *stm32x_info = NULL;
1047 uint16_t optionbyte = 0xF8;
1049 if (CMD_ARGC < 4)
1051 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1052 return ERROR_OK;
1055 struct flash_bank *bank;
1056 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1057 if (ERROR_OK != retval)
1058 return retval;
1060 stm32x_info = bank->driver_priv;
1062 target = bank->target;
1064 if (target->state != TARGET_HALTED)
1066 LOG_ERROR("Target not halted");
1067 return ERROR_TARGET_NOT_HALTED;
1070 /* REVISIT: ignores some options which we will display...
1071 * and doesn't insist on the specified syntax.
1074 /* OPT_RDWDGSW */
1075 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1077 optionbyte |= (1 << 0);
1079 else /* REVISIT must be "HWWDG" then ... */
1081 optionbyte &= ~(1 << 0);
1084 /* OPT_RDRSTSTDBY */
1085 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1087 optionbyte |= (1 << 1);
1089 else /* REVISIT must be "RSTSTNDBY" then ... */
1091 optionbyte &= ~(1 << 1);
1094 /* OPT_RDRSTSTOP */
1095 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1097 optionbyte |= (1 << 2);
1099 else /* REVISIT must be "RSTSTOP" then ... */
1101 optionbyte &= ~(1 << 2);
1104 if (stm32x_erase_options(bank) != ERROR_OK)
1106 command_print(CMD_CTX, "stm32x failed to erase options");
1107 return ERROR_OK;
1110 stm32x_info->option_bytes.user_options = optionbyte;
1112 if (stm32x_write_options(bank) != ERROR_OK)
1114 command_print(CMD_CTX, "stm32x failed to write options");
1115 return ERROR_OK;
1118 command_print(CMD_CTX, "stm32x write options complete.\n"
1119 "INFO: a reset or power cycle is required "
1120 "for the new settings to take effect.");
1122 return ERROR_OK;
1125 static int stm32x_mass_erase(struct flash_bank *bank)
1127 struct target *target = bank->target;
1128 uint32_t status;
1130 if (target->state != TARGET_HALTED)
1132 LOG_ERROR("Target not halted");
1133 return ERROR_TARGET_NOT_HALTED;
1136 /* unlock option flash registers */
1137 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1138 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1140 /* mass erase flash memory */
1141 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1142 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1144 status = stm32x_wait_status_busy(bank, 10);
1146 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1148 if (status & FLASH_WRPRTERR)
1150 LOG_ERROR("stm32x device protected");
1151 return ERROR_OK;
1154 if (status & FLASH_PGERR)
1156 LOG_ERROR("stm32x device programming failed");
1157 return ERROR_OK;
1160 return ERROR_OK;
1163 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1165 int i;
1167 if (CMD_ARGC < 1)
1169 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1170 return ERROR_OK;
1173 struct flash_bank *bank;
1174 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1175 if (ERROR_OK != retval)
1176 return retval;
1178 if (stm32x_mass_erase(bank) == ERROR_OK)
1180 /* set all sectors as erased */
1181 for (i = 0; i < bank->num_sectors; i++)
1183 bank->sectors[i].is_erased = 1;
1186 command_print(CMD_CTX, "stm32x mass erase complete");
1188 else
1190 command_print(CMD_CTX, "stm32x mass erase failed");
1193 return ERROR_OK;
1196 static const struct command_registration stm32x_exec_command_handlers[] = {
1198 .name = "lock",
1199 .handler = stm32x_handle_lock_command,
1200 .mode = COMMAND_EXEC,
1201 .usage = "bank_id",
1202 .help = "Lock entire flash device.",
1205 .name = "unlock",
1206 .handler = stm32x_handle_unlock_command,
1207 .mode = COMMAND_EXEC,
1208 .usage = "bank_id",
1209 .help = "Unlock entire protected flash device.",
1212 .name = "mass_erase",
1213 .handler = stm32x_handle_mass_erase_command,
1214 .mode = COMMAND_EXEC,
1215 .usage = "bank_id",
1216 .help = "Erase entire flash device.",
1219 .name = "options_read",
1220 .handler = stm32x_handle_options_read_command,
1221 .mode = COMMAND_EXEC,
1222 .usage = "bank_id",
1223 .help = "Read and display device option byte.",
1226 .name = "options_write",
1227 .handler = stm32x_handle_options_write_command,
1228 .mode = COMMAND_EXEC,
1229 .usage = "bank_id ('SWWDG'|'HWWDG') "
1230 "('RSTSTNDBY'|'NORSTSTNDBY') "
1231 "('RSTSTOP'|'NORSTSTOP')",
1232 .help = "Replace bits in device option byte.",
1234 COMMAND_REGISTRATION_DONE
1236 static const struct command_registration stm32x_command_handlers[] = {
1238 .name = "stm32x",
1239 .mode = COMMAND_ANY,
1240 .help = "stm32x flash command group",
1241 .chain = stm32x_exec_command_handlers,
1243 COMMAND_REGISTRATION_DONE
1246 struct flash_driver stm32x_flash = {
1247 .name = "stm32x",
1248 .commands = stm32x_command_handlers,
1249 .flash_bank_command = stm32x_flash_bank_command,
1250 .erase = stm32x_erase,
1251 .protect = stm32x_protect,
1252 .write = stm32x_write,
1253 .probe = stm32x_probe,
1254 .auto_probe = stm32x_auto_probe,
1255 .erase_check = default_flash_mem_blank_check,
1256 .protect_check = stm32x_protect_check,
1257 .info = stm32x_info,