src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the
  23  * Free Software Foundation, Inc.,
  24  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25  */
  26 #ifndef ARM_H
  27 #define ARM_H
  28
  29 #include <helper/command.h>
  30 #include "target.h"
  31
  32
  33 /**
  34  * @file
  35  * Holds the interface to ARM cores.
  36  *
  37  * At this writing, only "classic ARM" cores built on the ARMv4 register
  38  * and mode model are supported.  The Thumb2-only microcontroller profile
  39  * support has not yet been integrated, affecting Cortex-M parts.
  40  */
  41
  42 /**
  43  * Represent state of an ARM core.
  44  *
  45  * Most numbers match the five low bits of the *PSR registers on
  46  * "classic ARM" processors, which build on the ARMv4 processor
  47  * modes and register set.
  48  *
  49  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  50  *
  51  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  52  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  53  * they support.
  54  */
  55 enum arm_mode {
  56         ARM_MODE_USR = 16,
  57         ARM_MODE_FIQ = 17,
  58         ARM_MODE_IRQ = 18,
  59         ARM_MODE_SVC = 19,
  60         ARM_MODE_ABT = 23,
  61         ARM_MODE_MON = 26,
  62         ARM_MODE_UND = 27,
  63         ARM_MODE_SYS = 31,
  64
  65         ARM_MODE_THREAD,
  66         ARM_MODE_USER_THREAD,
  67         ARM_MODE_HANDLER,
  68
  69         ARM_MODE_ANY = -1
  70 };
  71
  72 const char *arm_mode_name(unsigned psr_mode);
  73 bool is_arm_mode(unsigned psr_mode);
  74
  75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  76 enum arm_state {
  77         ARM_STATE_ARM,
  78         ARM_STATE_THUMB,
  79         ARM_STATE_JAZELLE,
  80         ARM_STATE_THUMB_EE,
  81 };
  82
  83 extern const char *arm_state_strings[];
  84
  85 #define ARM_COMMON_MAGIC 0x0A450A45
  86
  87 /**
  88  * Represents a generic ARM core, with standard application registers.
  89  *
  90  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  91  * Cortex-M series cores do not support as many core states or shadowed
  92  * registers as traditional ARM cores, and only support Thumb2 instructions.
  93  */
  94 struct arm {
  95         int common_magic;
  96         struct reg_cache *core_cache;
  97
  98         /** Handle to the PC; valid in all core modes. */
  99         struct reg *pc;
 100
 101         /** Handle to the CPSR; valid in all core modes. */
 102         struct reg *cpsr;
 103
 104         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 105         struct reg *spsr;
 106
 107         /** Support for arm_reg_current() */
 108         const int *map;
 109
 110         /**
 111          * Indicates what registers are in the ARM state core register set.
 112          * ARM_MODE_ANY indicates the standard set of 37 registers,
 113          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 114          * more registers are shadowed, for "Secure Monitor" mode.
 115          * ARM_MODE_THREAD indicates a microcontroller profile core,
 116          * which only shadows SP.
 117          */
 118         enum arm_mode core_type;
 119
 120         /** Record the current core mode: SVC, USR, or some other mode. */
 121         enum arm_mode core_mode;
 122
 123         /** Record the current core state: ARM, Thumb, or otherwise. */
 124         enum arm_state core_state;
 125
 126         /** Flag reporting unavailability of the BKPT instruction. */
 127         bool is_armv4;
 128
 129         /** Flag reporting whether semihosting is active. */
 130         bool is_semihosting;
 131
 132         /** Value to be returned by semihosting SYS_ERRNO request. */
 133         int semihosting_errno;
 134
 135         int (*setup_semihosting)(struct target *target, int enable);
 136
 137         /** Backpointer to the target. */
 138         struct target *target;
 139
 140         /** Handle for the debug module, if one is present. */
 141         struct arm_dpm *dpm;
 142
 143         /** Handle for the Embedded Trace Module, if one is present. */
 144         struct etm_context *etm;
 145
 146         /* FIXME all these methods should take "struct arm *" not target */
 147
 148         /** Retrieve all core registers, for display. */
 149         int (*full_context)(struct target *target);
 150
 151         /** Retrieve a single core register. */
 152         int (*read_core_reg)(struct target *target, struct reg *reg,
 153                         int num, enum arm_mode mode);
 154         int (*write_core_reg)(struct target *target, struct reg *reg,
 155                         int num, enum arm_mode mode, uint32_t value);
 156
 157         /** Read coprocessor register.  */
 158         int (*mrc)(struct target *target, int cpnum,
 159                         uint32_t op1, uint32_t op2,
 160                         uint32_t CRn, uint32_t CRm,
 161                         uint32_t *value);
 162
 163         /** Write coprocessor register.  */
 164         int (*mcr)(struct target *target, int cpnum,
 165                         uint32_t op1, uint32_t op2,
 166                         uint32_t CRn, uint32_t CRm,
 167                         uint32_t value);
 168
 169         void *arch_info;
 170 };
 171
 172 /** Convert target handle to generic ARM target state handle. */
 173 static inline struct arm *target_to_arm(struct target *target)
 174 {
 175         return target->arch_info;
 176 }
 177
 178 static inline bool is_arm(struct arm *arm)
 179 {
 180         return arm && arm->common_magic == ARM_COMMON_MAGIC;
 181 }
 182
 183 struct arm_algorithm {
 184         int common_magic;
 185
 186         enum arm_mode core_mode;
 187         enum arm_state core_state;
 188 };
 189
 190 struct arm_reg {
 191         int num;
 192         enum arm_mode mode;
 193         struct target *target;
 194         struct arm *armv4_5_common;
 195         uint32_t value;
 196 };
 197
 198 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 199
 200 extern const struct command_registration arm_command_handlers[];
 201
 202 int arm_arch_state(struct target *target);
 203 int arm_get_gdb_reg_list(struct target *target,
 204                 struct reg **reg_list[], int *reg_list_size);
 205
 206 int arm_init_arch_info(struct target *target, struct arm *arm);
 207
 208 /* REVISIT rename this once it's usable by ARMv7-M */
 209 int armv4_5_run_algorithm(struct target *target,
 210                 int num_mem_params, struct mem_param *mem_params,
 211                 int num_reg_params, struct reg_param *reg_params,
 212                 uint32_t entry_point, uint32_t exit_point,
 213                 int timeout_ms, void *arch_info);
 214 int armv4_5_run_algorithm_inner(struct target *target,
 215                 int num_mem_params, struct mem_param *mem_params,
 216                 int num_reg_params, struct reg_param *reg_params,
 217                 uint32_t entry_point, uint32_t exit_point,
 218                 int timeout_ms, void *arch_info,
 219                 int (*run_it)(struct target *target, uint32_t exit_point,
 220                                 int timeout_ms, void *arch_info));
 221
 222 int arm_checksum_memory(struct target *target,
 223                 uint32_t address, uint32_t count, uint32_t *checksum);
 224 int arm_blank_check_memory(struct target *target,
 225                 uint32_t address, uint32_t count, uint32_t *blank);
 226
 227 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 228 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 229
 230 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
 231
 232 extern struct reg arm_gdb_dummy_fp_reg;
 233 extern struct reg arm_gdb_dummy_fps_reg;
 234
 235 #endif /* ARM_H */