src/target/mips32.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "mips32.h"
  30 #include "register.h"
  31
  32 char* mips32_core_reg_list[] =
  33 {
  34         "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
  35         "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
  36         "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
  37         "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
  38         "status", "lo", "hi", "badvaddr", "cause", "pc"
  39 };
  40
  41 const char *mips_isa_strings[] =
  42 {
  43         "MIPS32", "MIPS16e"
  44 };
  45
  46 struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
  47 {
  48         {0, NULL, NULL},
  49         {1, NULL, NULL},
  50         {2, NULL, NULL},
  51         {3, NULL, NULL},
  52         {4, NULL, NULL},
  53         {5, NULL, NULL},
  54         {6, NULL, NULL},
  55         {7, NULL, NULL},
  56         {8, NULL, NULL},
  57         {9, NULL, NULL},
  58         {10, NULL, NULL},
  59         {11, NULL, NULL},
  60         {12, NULL, NULL},
  61         {13, NULL, NULL},
  62         {14, NULL, NULL},
  63         {15, NULL, NULL},
  64         {16, NULL, NULL},
  65         {17, NULL, NULL},
  66         {18, NULL, NULL},
  67         {19, NULL, NULL},
  68         {20, NULL, NULL},
  69         {21, NULL, NULL},
  70         {22, NULL, NULL},
  71         {23, NULL, NULL},
  72         {24, NULL, NULL},
  73         {25, NULL, NULL},
  74         {26, NULL, NULL},
  75         {27, NULL, NULL},
  76         {28, NULL, NULL},
  77         {29, NULL, NULL},
  78         {30, NULL, NULL},
  79         {31, NULL, NULL},
  80
  81         {32, NULL, NULL},
  82         {33, NULL, NULL},
  83         {34, NULL, NULL},
  84         {35, NULL, NULL},
  85         {36, NULL, NULL},
  86         {37, NULL, NULL},
  87 };
  88
  89 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
  90  * we also add 18 unknown registers to handle gdb requests */
  91
  92 #define MIPS32NUMFPREGS 34 + 18
  93
  94 uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
  95
  96 struct reg mips32_gdb_dummy_fp_reg =
  97 {
  98         .name = "GDB dummy floating-point register",
  99         .value = mips32_gdb_dummy_fp_value,
 100         .dirty = 0,
 101         .valid = 1,
 102         .size = 32,
 103         .arch_info = NULL,
 104 };
 105
 106 int mips32_get_core_reg(struct reg *reg)
 107 {
 108         int retval;
 109         struct mips32_core_reg *mips32_reg = reg->arch_info;
 110         struct target *target = mips32_reg->target;
 111         struct mips32_common *mips32_target = target_to_mips32(target);
 112
 113         if (target->state != TARGET_HALTED)
 114         {
 115                 return ERROR_TARGET_NOT_HALTED;
 116         }
 117
 118         retval = mips32_target->read_core_reg(target, mips32_reg->num);
 119
 120         return retval;
 121 }
 122
 123 int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 124 {
 125         struct mips32_core_reg *mips32_reg = reg->arch_info;
 126         struct target *target = mips32_reg->target;
 127         uint32_t value = buf_get_u32(buf, 0, 32);
 128
 129         if (target->state != TARGET_HALTED)
 130         {
 131                 return ERROR_TARGET_NOT_HALTED;
 132         }
 133
 134         buf_set_u32(reg->value, 0, 32, value);
 135         reg->dirty = 1;
 136         reg->valid = 1;
 137
 138         return ERROR_OK;
 139 }
 140
 141 int mips32_read_core_reg(struct target *target, int num)
 142 {
 143         uint32_t reg_value;
 144         struct mips32_core_reg *mips_core_reg;
 145
 146         /* get pointers to arch-specific information */
 147         struct mips32_common *mips32 = target_to_mips32(target);
 148
 149         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 150                 return ERROR_INVALID_ARGUMENTS;
 151
 152         mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 153         reg_value = mips32->core_regs[num];
 154         buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
 155         mips32->core_cache->reg_list[num].valid = 1;
 156         mips32->core_cache->reg_list[num].dirty = 0;
 157
 158         return ERROR_OK;
 159 }
 160
 161 int mips32_write_core_reg(struct target *target, int num)
 162 {
 163         uint32_t reg_value;
 164         struct mips32_core_reg *mips_core_reg;
 165
 166         /* get pointers to arch-specific information */
 167         struct mips32_common *mips32 = target_to_mips32(target);
 168
 169         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 170                 return ERROR_INVALID_ARGUMENTS;
 171
 172         reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 173         mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 174         mips32->core_regs[num] = reg_value;
 175         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 176         mips32->core_cache->reg_list[num].valid = 1;
 177         mips32->core_cache->reg_list[num].dirty = 0;
 178
 179         return ERROR_OK;
 180 }
 181
 182 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 183 {
 184         /* get pointers to arch-specific information */
 185         struct mips32_common *mips32 = target_to_mips32(target);
 186         int i;
 187
 188         /* include floating point registers */
 189         *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
 190         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 191
 192         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 193         {
 194                 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
 195         }
 196
 197         /* add dummy floating points regs */
 198         for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
 199         {
 200                 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
 201         }
 202
 203         return ERROR_OK;
 204 }
 205
 206 int mips32_save_context(struct target *target)
 207 {
 208         int i;
 209
 210         /* get pointers to arch-specific information */
 211         struct mips32_common *mips32 = target_to_mips32(target);
 212         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 213
 214         /* read core registers */
 215         mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
 216
 217         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 218         {
 219                 if (!mips32->core_cache->reg_list[i].valid)
 220                 {
 221                         mips32->read_core_reg(target, i);
 222                 }
 223         }
 224
 225         return ERROR_OK;
 226 }
 227
 228 int mips32_restore_context(struct target *target)
 229 {
 230         int i;
 231
 232         /* get pointers to arch-specific information */
 233         struct mips32_common *mips32 = target_to_mips32(target);
 234         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 235
 236         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 237         {
 238                 if (mips32->core_cache->reg_list[i].dirty)
 239                 {
 240                         mips32->write_core_reg(target, i);
 241                 }
 242         }
 243
 244         /* write core regs */
 245         mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
 246
 247         return ERROR_OK;
 248 }
 249
 250 int mips32_arch_state(struct target *target)
 251 {
 252         struct mips32_common *mips32 = target_to_mips32(target);
 253
 254         LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
 255                 mips_isa_strings[mips32->isa_mode],
 256                 debug_reason_name(target),
 257                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 258
 259         return ERROR_OK;
 260 }
 261
 262 static const struct reg_arch_type mips32_reg_type = {
 263         .get = mips32_get_core_reg,
 264         .set = mips32_set_core_reg,
 265 };
 266
 267 struct reg_cache *mips32_build_reg_cache(struct target *target)
 268 {
 269         /* get pointers to arch-specific information */
 270         struct mips32_common *mips32 = target_to_mips32(target);
 271
 272         int num_regs = MIPS32NUMCOREREGS;
 273         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 274         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 275         struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
 276         struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
 277         int i;
 278
 279         register_init_dummy(&mips32_gdb_dummy_fp_reg);
 280
 281         /* Build the process context cache */
 282         cache->name = "mips32 registers";
 283         cache->next = NULL;
 284         cache->reg_list = reg_list;
 285         cache->num_regs = num_regs;
 286         (*cache_p) = cache;
 287         mips32->core_cache = cache;
 288
 289         for (i = 0; i < num_regs; i++)
 290         {
 291                 arch_info[i] = mips32_core_reg_list_arch_info[i];
 292                 arch_info[i].target = target;
 293                 arch_info[i].mips32_common = mips32;
 294                 reg_list[i].name = mips32_core_reg_list[i];
 295                 reg_list[i].size = 32;
 296                 reg_list[i].value = calloc(1, 4);
 297                 reg_list[i].dirty = 0;
 298                 reg_list[i].valid = 0;
 299                 reg_list[i].type = &mips32_reg_type;
 300                 reg_list[i].arch_info = &arch_info[i];
 301         }
 302
 303         return cache;
 304 }
 305
 306 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
 307 {
 308         target->arch_info = mips32;
 309         mips32->common_magic = MIPS32_COMMON_MAGIC;
 310
 311         /* has breakpoint/watchpint unit been scanned */
 312         mips32->bp_scanned = 0;
 313         mips32->data_break_list = NULL;
 314
 315         mips32->ejtag_info.tap = tap;
 316         mips32->read_core_reg = mips32_read_core_reg;
 317         mips32->write_core_reg = mips32_write_core_reg;
 318
 319         return ERROR_OK;
 320 }
 321
 322 int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 323 {
 324         /*TODO*/
 325         return ERROR_OK;
 326 }
 327
 328 int mips32_examine(struct target *target)
 329 {
 330         struct mips32_common *mips32 = target_to_mips32(target);
 331
 332         if (!target_was_examined(target))
 333         {
 334                 target_set_examined(target);
 335
 336                 /* we will configure later */
 337                 mips32->bp_scanned = 0;
 338                 mips32->num_inst_bpoints = 0;
 339                 mips32->num_data_bpoints = 0;
 340                 mips32->num_inst_bpoints_avail = 0;
 341                 mips32->num_data_bpoints_avail = 0;
 342         }
 343
 344         return ERROR_OK;
 345 }
 346
 347 int mips32_configure_break_unit(struct target *target)
 348 {
 349         /* get pointers to arch-specific information */
 350         struct mips32_common *mips32 = target_to_mips32(target);
 351         int retval;
 352         uint32_t dcr, bpinfo;
 353         int i;
 354
 355         if (mips32->bp_scanned)
 356                 return ERROR_OK;
 357
 358         /* get info about breakpoint support */
 359         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 360                 return retval;
 361
 362         if (dcr & EJTAG_DCR_IB)
 363         {
 364                 /* get number of inst breakpoints */
 365                 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
 366                         return retval;
 367
 368                 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
 369                 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
 370                 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
 371                 for (i = 0; i < mips32->num_inst_bpoints; i++)
 372                 {
 373                         mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
 374                 }
 375
 376                 /* clear IBIS reg */
 377                 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 378                         return retval;
 379         }
 380
 381         if (dcr & EJTAG_DCR_DB)
 382         {
 383                 /* get number of data breakpoints */
 384                 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
 385                         return retval;
 386
 387                 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
 388                 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
 389                 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
 390                 for (i = 0; i < mips32->num_data_bpoints; i++)
 391                 {
 392                         mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
 393                 }
 394
 395                 /* clear DBIS reg */
 396                 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
 397                         return retval;
 398         }
 399
 400         LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
 401
 402         mips32->bp_scanned = 1;
 403
 404         return ERROR_OK;
 405 }
 406
 407 int mips32_enable_interrupts(struct target *target, int enable)
 408 {
 409         int retval;
 410         int update = 0;
 411         uint32_t dcr;
 412
 413         /* read debug control register */
 414         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 415                 return retval;
 416
 417         if (enable)
 418         {
 419                 if (!(dcr & EJTAG_DCR_INTE))
 420                 {
 421                         /* enable interrupts */
 422                         dcr |= EJTAG_DCR_INTE;
 423                         update = 1;
 424                 }
 425         }
 426         else
 427         {
 428                 if (dcr & EJTAG_DCR_INTE)
 429                 {
 430                         /* disable interrupts */
 431                         dcr &= ~EJTAG_DCR_INTE;
 432                         update = 1;
 433                 }
 434         }
 435
 436         if (update)
 437         {
 438                 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
 439                         return retval;
 440         }
 441
 442         return ERROR_OK;
 443 }