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This will add the Value Line HD of stm32 devices.
[openocd/jflash.git] / src / flash / nor / stm32f1x.c
blob4927fb8987fe726b2b523e42294cb69d3d1ed2f8
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
31
32 /* stm32x register locations */
33
34 #define STM32_FLASH_ACR 0x40022000
35 #define STM32_FLASH_KEYR 0x40022004
36 #define STM32_FLASH_OPTKEYR 0x40022008
37 #define STM32_FLASH_SR 0x4002200C
38 #define STM32_FLASH_CR 0x40022010
39 #define STM32_FLASH_AR 0x40022014
40 #define STM32_FLASH_OBR 0x4002201C
41 #define STM32_FLASH_WRPR 0x40022020
42
43 /* option byte location */
44
45 #define STM32_OB_RDP 0x1FFFF800
46 #define STM32_OB_USER 0x1FFFF802
47 #define STM32_OB_DATA0 0x1FFFF804
48 #define STM32_OB_DATA1 0x1FFFF806
49 #define STM32_OB_WRP0 0x1FFFF808
50 #define STM32_OB_WRP1 0x1FFFF80A
51 #define STM32_OB_WRP2 0x1FFFF80C
52 #define STM32_OB_WRP3 0x1FFFF80E
53
54 /* FLASH_CR register bits */
55
56 #define FLASH_PG (1 << 0)
57 #define FLASH_PER (1 << 1)
58 #define FLASH_MER (1 << 2)
59 #define FLASH_OPTPG (1 << 4)
60 #define FLASH_OPTER (1 << 5)
61 #define FLASH_STRT (1 << 6)
62 #define FLASH_LOCK (1 << 7)
63 #define FLASH_OPTWRE (1 << 9)
64
65 /* FLASH_SR register bits */
66
67 #define FLASH_BSY (1 << 0)
68 #define FLASH_PGERR (1 << 2)
69 #define FLASH_WRPRTERR (1 << 4)
70 #define FLASH_EOP (1 << 5)
71
72 /* STM32_FLASH_OBR bit definitions (reading) */
73
74 #define OPT_ERROR 0
75 #define OPT_READOUT 1
76 #define OPT_RDWDGSW 2
77 #define OPT_RDRSTSTOP 3
78 #define OPT_RDRSTSTDBY 4
79 #define OPT_BFB2 5 /* dual flash bank only */
80
81 /* register unlock keys */
82
83 #define KEY1 0x45670123
84 #define KEY2 0xCDEF89AB
85
86 /* we use an offset to access the second bank on dual flash devices
87 * strangely the protection of the second bank is done on the bank0 reg's */
88
89 #define FLASH_OFFSET_B0 0x00
90 #define FLASH_OFFSET_B1 0x40
91
92 struct stm32x_options
93 {
94 uint16_t RDP;
95 uint16_t user_options;
96 uint16_t protection[4];
97 };
98
99 struct stm32x_flash_bank
100 {
101 struct stm32x_options option_bytes;
102 struct working_area *write_algorithm;
103 int ppage_size;
104 int probed;
105
106 bool has_dual_banks;
107 /* used to access dual flash bank stm32xl
108 * 0x00 will address bank 0 flash
109 * 0x40 will address bank 1 flash */
110 int register_offset;
111 };
112
113 static int stm32x_mass_erase(struct flash_bank *bank);
114
115 /* flash bank stm32x <base> <size> 0 0 <target#>
116 */
117 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
118 {
119 struct stm32x_flash_bank *stm32x_info;
120
121 if (CMD_ARGC < 6)
122 {
123 LOG_WARNING("incomplete flash_bank stm32x configuration");
124 return ERROR_FLASH_BANK_INVALID;
125 }
126
127 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
128 bank->driver_priv = stm32x_info;
129
130 stm32x_info->write_algorithm = NULL;
131 stm32x_info->probed = 0;
132 stm32x_info->has_dual_banks = false;
133 stm32x_info->register_offset = FLASH_OFFSET_B0;
134
135 return ERROR_OK;
136 }
137
138 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
139 {
140 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
141 return reg + stm32x_info->register_offset;
142 }
143
144 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
145 {
146 struct target *target = bank->target;
147 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
148 }
149
150 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
151 {
152 struct target *target = bank->target;
153 uint32_t status;
154 int retval = ERROR_OK;
155
156 /* wait for busy to clear */
157 for (;;)
158 {
159 retval = stm32x_get_flash_status(bank, &status);
160 if (retval != ERROR_OK)
161 return retval;
162 LOG_DEBUG("status: 0x%" PRIx32 "", status);
163 if ((status & FLASH_BSY) == 0)
164 break;
165 if (timeout-- <= 0)
166 {
167 LOG_ERROR("timed out waiting for flash");
168 return ERROR_FAIL;
169 }
170 alive_sleep(1);
171 }
172
173 if (status & FLASH_WRPRTERR)
174 {
175 LOG_ERROR("stm32x device protected");
176 retval = ERROR_FAIL;
177 }
178
179 if (status & FLASH_PGERR)
180 {
181 LOG_ERROR("stm32x device programming failed");
182 retval = ERROR_FAIL;
183 }
184
185 /* Clear but report errors */
186 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
187 {
188 /* If this operation fails, we ignore it and report the original
189 * retval
190 */
191 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
192 FLASH_WRPRTERR | FLASH_PGERR);
193 }
194 return retval;
195 }
196
197 int stm32x_check_operation_supported(struct flash_bank *bank)
198 {
199 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
200
201 /* if we have a dual flash bank device then
202 * we need to perform option byte stuff on bank0 only */
203 if (stm32x_info->register_offset != FLASH_OFFSET_B0)
204 {
205 LOG_ERROR("Option Byte Operation's must use bank0");
206 return ERROR_FLASH_OPERATION_FAILED;
207 }
208
209 return ERROR_OK;
210 }
211
212 static int stm32x_read_options(struct flash_bank *bank)
213 {
214 uint32_t optiondata;
215 struct stm32x_flash_bank *stm32x_info = NULL;
216 struct target *target = bank->target;
217
218 stm32x_info = bank->driver_priv;
219
220 /* read current option bytes */
221 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
222 if (retval != ERROR_OK)
223 return retval;
224
225 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
226 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
227
228 if (optiondata & (1 << OPT_READOUT))
229 LOG_INFO("Device Security Bit Set");
230
231 /* each bit refers to a 4bank protection */
232 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
233 if (retval != ERROR_OK)
234 return retval;
235
236 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
237 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
238 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
239 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
240
241 return ERROR_OK;
242 }
243
244 static int stm32x_erase_options(struct flash_bank *bank)
245 {
246 struct stm32x_flash_bank *stm32x_info = NULL;
247 struct target *target = bank->target;
248
249 stm32x_info = bank->driver_priv;
250
251 /* read current options */
252 stm32x_read_options(bank);
253
254 /* unlock flash registers */
255 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
256 if (retval != ERROR_OK)
257 return retval;
258
259 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
260 if (retval != ERROR_OK)
261 return retval;
262
263 /* unlock option flash registers */
264 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
265 if (retval != ERROR_OK)
266 return retval;
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
268 if (retval != ERROR_OK)
269 return retval;
270
271 /* erase option bytes */
272 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
273 if (retval != ERROR_OK)
274 return retval;
275 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278
279 retval = stm32x_wait_status_busy(bank, 10);
280 if (retval != ERROR_OK)
281 return retval;
282
283 /* clear readout protection and complementary option bytes
284 * this will also force a device unlock if set */
285 stm32x_info->option_bytes.RDP = 0x5AA5;
286
287 return ERROR_OK;
288 }
289
290 static int stm32x_write_options(struct flash_bank *bank)
291 {
292 struct stm32x_flash_bank *stm32x_info = NULL;
293 struct target *target = bank->target;
294
295 stm32x_info = bank->driver_priv;
296
297 /* unlock flash registers */
298 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
299 if (retval != ERROR_OK)
300 return retval;
301 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
302 if (retval != ERROR_OK)
303 return retval;
304
305 /* unlock option flash registers */
306 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
307 if (retval != ERROR_OK)
308 return retval;
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
310 if (retval != ERROR_OK)
311 return retval;
312
313 /* program option bytes */
314 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
315 if (retval != ERROR_OK)
316 return retval;
317
318 /* write user option byte */
319 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
320 if (retval != ERROR_OK)
321 return retval;
322
323 retval = stm32x_wait_status_busy(bank, 10);
324 if (retval != ERROR_OK)
325 return retval;
326
327 /* write protection byte 1 */
328 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
329 if (retval != ERROR_OK)
330 return retval;
331
332 retval = stm32x_wait_status_busy(bank, 10);
333 if (retval != ERROR_OK)
334 return retval;
335
336 /* write protection byte 2 */
337 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
338 if (retval != ERROR_OK)
339 return retval;
340
341 retval = stm32x_wait_status_busy(bank, 10);
342 if (retval != ERROR_OK)
343 return retval;
344
345 /* write protection byte 3 */
346 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
347 if (retval != ERROR_OK)
348 return retval;
349
350 retval = stm32x_wait_status_busy(bank, 10);
351 if (retval != ERROR_OK)
352 return retval;
353
354 /* write protection byte 4 */
355 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
356 if (retval != ERROR_OK)
357 return retval;
358
359 retval = stm32x_wait_status_busy(bank, 10);
360 if (retval != ERROR_OK)
361 return retval;
362
363 /* write readout protection bit */
364 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
365 if (retval != ERROR_OK)
366 return retval;
367
368 retval = stm32x_wait_status_busy(bank, 10);
369 if (retval != ERROR_OK)
370 return retval;
371
372 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
373 if (retval != ERROR_OK)
374 return retval;
375
376 return ERROR_OK;
377 }
378
379 static int stm32x_protect_check(struct flash_bank *bank)
380 {
381 struct target *target = bank->target;
382 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
383
384 uint32_t protection;
385 int i, s;
386 int num_bits;
387 int set;
388
389 if (target->state != TARGET_HALTED)
390 {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED;
393 }
394
395 int retval = stm32x_check_operation_supported(bank);
396 if (ERROR_OK != retval)
397 return retval;
398
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
402 if (retval != ERROR_OK)
403 return retval;
404
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
408
409 if (stm32x_info->ppage_size == 2)
410 {
411 /* high density flash/connectivity line protection */
412
413 set = 1;
414
415 if (protection & (1 << 31))
416 set = 0;
417
418 /* bit 31 controls sector 62 - 255 protection for high density
419 * bit 31 controls sector 62 - 127 protection for connectivity line */
420 for (s = 62; s < bank->num_sectors; s++)
421 {
422 bank->sectors[s].is_protected = set;
423 }
424
425 if (bank->num_sectors > 61)
426 num_bits = 31;
427
428 for (i = 0; i < num_bits; i++)
429 {
430 set = 1;
431
432 if (protection & (1 << i))
433 set = 0;
434
435 for (s = 0; s < stm32x_info->ppage_size; s++)
436 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
437 }
438 }
439 else
440 {
441 /* low/medium density flash protection */
442 for (i = 0; i < num_bits; i++)
443 {
444 set = 1;
445
446 if (protection & (1 << i))
447 set = 0;
448
449 for (s = 0; s < stm32x_info->ppage_size; s++)
450 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
451 }
452 }
453
454 return ERROR_OK;
455 }
456
457 static int stm32x_erase(struct flash_bank *bank, int first, int last)
458 {
459 struct target *target = bank->target;
460 int i;
461
462 if (bank->target->state != TARGET_HALTED)
463 {
464 LOG_ERROR("Target not halted");
465 return ERROR_TARGET_NOT_HALTED;
466 }
467
468 if ((first == 0) && (last == (bank->num_sectors - 1)))
469 {
470 return stm32x_mass_erase(bank);
471 }
472
473 /* unlock flash registers */
474 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
475 if (retval != ERROR_OK)
476 return retval;
477 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
478 if (retval != ERROR_OK)
479 return retval;
480
481 for (i = first; i <= last; i++)
482 {
483 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
484 if (retval != ERROR_OK)
485 return retval;
486 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
487 bank->base + bank->sectors[i].offset);
488 if (retval != ERROR_OK)
489 return retval;
490 retval = target_write_u32(target,
491 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
492 if (retval != ERROR_OK)
493 return retval;
494
495 retval = stm32x_wait_status_busy(bank, 100);
496 if (retval != ERROR_OK)
497 return retval;
498
499 bank->sectors[i].is_erased = 1;
500 }
501
502 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
503 if (retval != ERROR_OK)
504 return retval;
505
506 return ERROR_OK;
507 }
508
509 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
510 {
511 struct stm32x_flash_bank *stm32x_info = NULL;
512 struct target *target = bank->target;
513 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
514 int i, reg, bit;
515 int status;
516 uint32_t protection;
517
518 stm32x_info = bank->driver_priv;
519
520 if (target->state != TARGET_HALTED)
521 {
522 LOG_ERROR("Target not halted");
523 return ERROR_TARGET_NOT_HALTED;
524 }
525
526 int retval = stm32x_check_operation_supported(bank);
527 if (ERROR_OK != retval)
528 return retval;
529
530 if ((first % stm32x_info->ppage_size) != 0)
531 {
532 LOG_WARNING("aligned start protect sector to a %d sector boundary",
533 stm32x_info->ppage_size);
534 first = first - (first % stm32x_info->ppage_size);
535 }
536 if (((last + 1) % stm32x_info->ppage_size) != 0)
537 {
538 LOG_WARNING("aligned end protect sector to a %d sector boundary",
539 stm32x_info->ppage_size);
540 last++;
541 last = last - (last % stm32x_info->ppage_size);
542 last--;
543 }
544
545 /* medium density - each bit refers to a 4bank protection
546 * high density - each bit refers to a 2bank protection */
547 retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
548 if (retval != ERROR_OK)
549 return retval;
550
551 prot_reg[0] = (uint16_t)protection;
552 prot_reg[1] = (uint16_t)(protection >> 8);
553 prot_reg[2] = (uint16_t)(protection >> 16);
554 prot_reg[3] = (uint16_t)(protection >> 24);
555
556 if (stm32x_info->ppage_size == 2)
557 {
558 /* high density flash */
559
560 /* bit 7 controls sector 62 - 255 protection */
561 if (last > 61)
562 {
563 if (set)
564 prot_reg[3] &= ~(1 << 7);
565 else
566 prot_reg[3] |= (1 << 7);
567 }
568
569 if (first > 61)
570 first = 62;
571 if (last > 61)
572 last = 61;
573
574 for (i = first; i <= last; i++)
575 {
576 reg = (i / stm32x_info->ppage_size) / 8;
577 bit = (i / stm32x_info->ppage_size) - (reg * 8);
578
579 if (set)
580 prot_reg[reg] &= ~(1 << bit);
581 else
582 prot_reg[reg] |= (1 << bit);
583 }
584 }
585 else
586 {
587 /* medium density flash */
588 for (i = first; i <= last; i++)
589 {
590 reg = (i / stm32x_info->ppage_size) / 8;
591 bit = (i / stm32x_info->ppage_size) - (reg * 8);
592
593 if (set)
594 prot_reg[reg] &= ~(1 << bit);
595 else
596 prot_reg[reg] |= (1 << bit);
597 }
598 }
599
600 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
601 return status;
602
603 stm32x_info->option_bytes.protection[0] = prot_reg[0];
604 stm32x_info->option_bytes.protection[1] = prot_reg[1];
605 stm32x_info->option_bytes.protection[2] = prot_reg[2];
606 stm32x_info->option_bytes.protection[3] = prot_reg[3];
607
608 return stm32x_write_options(bank);
609 }
610
611 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
612 uint32_t offset, uint32_t count)
613 {
614 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
615 struct target *target = bank->target;
616 uint32_t buffer_size = 16384;
617 struct working_area *source;
618 uint32_t address = bank->base + offset;
619 struct reg_param reg_params[4];
620 struct armv7m_algorithm armv7m_info;
621 int retval = ERROR_OK;
622
623 /* see contib/loaders/flash/stm32x.s for src */
624
625 static const uint8_t stm32x_flash_write_code[] = {
626 /* #define STM32_FLASH_CR_OFFSET 0x10 */
627 /* #define STM32_FLASH_SR_OFFSET 0x0C */
628 /* write: */
629 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
630 0x1c, 0x44, /* add r4, r3 */
631 /* write_half_word: */
632 0x01, 0x23, /* movs r3, #0x01 */
633 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
634 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
635 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
636 /* busy: */
637 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
638 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
639 0xfb, 0xd0, /* beq busy */
640 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
641 0x01, 0xd1, /* bne exit */
642 0x01, 0x3a, /* subs r2, r2, #0x01 */
643 0xf0, 0xd1, /* bne write_half_word */
644 /* exit: */
645 0x00, 0xbe, /* bkpt #0x00 */
646 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
647 };
648
649 /* flash write code */
650 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
651 &stm32x_info->write_algorithm) != ERROR_OK)
652 {
653 LOG_WARNING("no working area available, can't do block memory writes");
654 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
655 };
656
657 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
658 sizeof(stm32x_flash_write_code),
659 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
660 return retval;
661
662 /* memory buffer */
663 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
664 {
665 buffer_size /= 2;
666 if (buffer_size <= 256)
667 {
668 /* if we already allocated the writing code, but failed to get a
669 * buffer, free the algorithm */
670 if (stm32x_info->write_algorithm)
671 target_free_working_area(target, stm32x_info->write_algorithm);
672
673 LOG_WARNING("no large enough working area available, can't do block memory writes");
674 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
675 }
676 };
677
678 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
679 armv7m_info.core_mode = ARMV7M_MODE_ANY;
680
681 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
682 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
683 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
684 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
685
686 while (count > 0)
687 {
688 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
689 (buffer_size / 2) : count;
690
691 if ((retval = target_write_buffer(target, source->address,
692 thisrun_count * 2, buffer)) != ERROR_OK)
693 break;
694
695 buf_set_u32(reg_params[0].value, 0, 32, source->address);
696 buf_set_u32(reg_params[1].value, 0, 32, address);
697 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
698 buf_set_u32(reg_params[3].value, 0, 32, stm32x_info->register_offset);
699
700 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
701 stm32x_info->write_algorithm->address,
702 0,
703 10000, &armv7m_info)) != ERROR_OK)
704 {
705 LOG_ERROR("error executing stm32x flash write algorithm");
706 break;
707 }
708
709 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
710 {
711 LOG_ERROR("flash memory not erased before writing");
712 /* Clear but report errors */
713 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
714 retval = ERROR_FAIL;
715 break;
716 }
717
718 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
719 {
720 LOG_ERROR("flash memory write protected");
721 /* Clear but report errors */
722 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
723 retval = ERROR_FAIL;
724 break;
725 }
726
727 buffer += thisrun_count * 2;
728 address += thisrun_count * 2;
729 count -= thisrun_count;
730 }
731
732 target_free_working_area(target, source);
733 target_free_working_area(target, stm32x_info->write_algorithm);
734
735 destroy_reg_param(&reg_params[0]);
736 destroy_reg_param(&reg_params[1]);
737 destroy_reg_param(&reg_params[2]);
738 destroy_reg_param(&reg_params[3]);
739
740 return retval;
741 }
742
743 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
744 uint32_t offset, uint32_t count)
745 {
746 struct target *target = bank->target;
747 uint32_t words_remaining = (count / 2);
748 uint32_t bytes_remaining = (count & 0x00000001);
749 uint32_t address = bank->base + offset;
750 uint32_t bytes_written = 0;
751 int retval;
752
753 if (bank->target->state != TARGET_HALTED)
754 {
755 LOG_ERROR("Target not halted");
756 return ERROR_TARGET_NOT_HALTED;
757 }
758
759 if (offset & 0x1)
760 {
761 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
762 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
763 }
764
765 /* unlock flash registers */
766 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
767 if (retval != ERROR_OK)
768 return retval;
769 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
770 if (retval != ERROR_OK)
771 return retval;
772
773 /* multiple half words (2-byte) to be programmed? */
774 if (words_remaining > 0)
775 {
776 /* try using a block write */
777 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
778 {
779 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
780 {
781 /* if block write failed (no sufficient working area),
782 * we use normal (slow) single dword accesses */
783 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
784 }
785 }
786 else
787 {
788 buffer += words_remaining * 2;
789 address += words_remaining * 2;
790 words_remaining = 0;
791 }
792 }
793
794 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
795 return retval;
796
797 while (words_remaining > 0)
798 {
799 uint16_t value;
800 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
801
802 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
803 if (retval != ERROR_OK)
804 return retval;
805 retval = target_write_u16(target, address, value);
806 if (retval != ERROR_OK)
807 return retval;
808
809 retval = stm32x_wait_status_busy(bank, 5);
810 if (retval != ERROR_OK)
811 return retval;
812
813 bytes_written += 2;
814 words_remaining--;
815 address += 2;
816 }
817
818 if (bytes_remaining)
819 {
820 uint16_t value = 0xffff;
821 memcpy(&value, buffer + bytes_written, bytes_remaining);
822
823 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
824 if (retval != ERROR_OK)
825 return retval;
826 retval = target_write_u16(target, address, value);
827 if (retval != ERROR_OK)
828 return retval;
829
830 retval = stm32x_wait_status_busy(bank, 5);
831 if (retval != ERROR_OK)
832 return retval;
833 }
834
835 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
836 }
837
838 static int stm32x_probe(struct flash_bank *bank)
839 {
840 struct target *target = bank->target;
841 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
842 int i;
843 uint16_t num_pages;
844 uint32_t device_id;
845 int page_size;
846 uint32_t base_address = 0x08000000;
847
848 stm32x_info->probed = 0;
849 stm32x_info->register_offset = FLASH_OFFSET_B0;
850
851 /* read stm32 device id register */
852 int retval = target_read_u32(target, 0xE0042000, &device_id);
853 if (retval != ERROR_OK)
854 return retval;
855 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
856
857 /* get flash size from target. */
858 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
859 if (retval != ERROR_OK)
860 {
861 LOG_WARNING("failed reading flash size, default to max target family");
862 /* failed reading flash size, default to max target family */
863 num_pages = 0xffff;
864 }
865
866 if ((device_id & 0x7ff) == 0x410)
867 {
868 /* medium density - we have 1k pages
869 * 4 pages for a protection area */
870 page_size = 1024;
871 stm32x_info->ppage_size = 4;
872
873 /* check for early silicon */
874 if (num_pages == 0xffff)
875 {
876 /* number of sectors incorrect on revA */
877 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
878 num_pages = 128;
879 }
880 }
881 else if ((device_id & 0x7ff) == 0x412)
882 {
883 /* low density - we have 1k pages
884 * 4 pages for a protection area */
885 page_size = 1024;
886 stm32x_info->ppage_size = 4;
887
888 /* check for early silicon */
889 if (num_pages == 0xffff)
890 {
891 /* number of sectors incorrect on revA */
892 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
893 num_pages = 32;
894 }
895 }
896 else if ((device_id & 0x7ff) == 0x414)
897 {
898 /* high density - we have 2k pages
899 * 2 pages for a protection area */
900 page_size = 2048;
901 stm32x_info->ppage_size = 2;
902
903 /* check for early silicon */
904 if (num_pages == 0xffff)
905 {
906 /* number of sectors incorrect on revZ */
907 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
908 num_pages = 512;
909 }
910 }
911 else if ((device_id & 0x7ff) == 0x418)
912 {
913 /* connectivity line density - we have 2k pages
914 * 2 pages for a protection area */
915 page_size = 2048;
916 stm32x_info->ppage_size = 2;
917
918 /* check for early silicon */
919 if (num_pages == 0xffff)
920 {
921 /* number of sectors incorrect on revZ */
922 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
923 num_pages = 256;
924 }
925 }
926 else if ((device_id & 0x7ff) == 0x420)
927 {
928 /* value line density - we have 1k pages
929 * 4 pages for a protection area */
930 page_size = 1024;
931 stm32x_info->ppage_size = 4;
932
933 /* check for early silicon */
934 if (num_pages == 0xffff)
935 {
936 /* number of sectors may be incorrrect on early silicon */
937 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
938 num_pages = 128;
939 }
940 }
941 else if ((device_id & 0x7ff) == 0x428)
942 {
943 /* value line density - we have 1k pages
944 * 4 pages for a protection area */
945 page_size = 2048;
946 stm32x_info->ppage_size = 4;
947
948 /* check for early silicon */
949 if (num_pages == 0xffff)
950 {
951 /* number of sectors may be incorrrect on early silicon */
952 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
953 num_pages = 128;
954 }
955 }
956
957 else if ((device_id & 0x7ff) == 0x430)
958 {
959 /* xl line density - we have 2k pages
960 * 2 pages for a protection area */
961 page_size = 2048;
962 stm32x_info->ppage_size = 2;
963 stm32x_info->has_dual_banks = true;
964
965 /* check for early silicon */
966 if (num_pages == 0xffff)
967 {
968 /* number of sectors may be incorrrect on early silicon */
969 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
970 num_pages = 1024;
971 }
972
973 /* split reported size into matching bank */
974 if (bank->base != 0x08080000)
975 {
976 /* bank 0 will be fixed 512k */
977 num_pages = 512;
978 }
979 else
980 {
981 num_pages -= 512;
982 /* bank1 also uses a register offset */
983 stm32x_info->register_offset = FLASH_OFFSET_B1;
984 base_address = 0x08080000;
985 }
986 }
987 else
988 {
989 LOG_WARNING("Cannot identify target as a STM32 family.");
990 return ERROR_FAIL;
991 }
992
993 LOG_INFO("flash size = %dkbytes", num_pages);
994
995 /* calculate numbers of pages */
996 num_pages /= (page_size / 1024);
997
998 if (bank->sectors)
999 {
1000 free(bank->sectors);
1001 bank->sectors = NULL;
1002 }
1003
1004 bank->base = base_address;
1005 bank->size = (num_pages * page_size);
1006 bank->num_sectors = num_pages;
1007 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1008
1009 for (i = 0; i < num_pages; i++)
1010 {
1011 bank->sectors[i].offset = i * page_size;
1012 bank->sectors[i].size = page_size;
1013 bank->sectors[i].is_erased = -1;
1014 bank->sectors[i].is_protected = 1;
1015 }
1016
1017 stm32x_info->probed = 1;
1018
1019 return ERROR_OK;
1020 }
1021
1022 static int stm32x_auto_probe(struct flash_bank *bank)
1023 {
1024 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1025 if (stm32x_info->probed)
1026 return ERROR_OK;
1027 return stm32x_probe(bank);
1028 }
1029
1030 #if 0
1031 COMMAND_HANDLER(stm32x_handle_part_id_command)
1032 {
1033 return ERROR_OK;
1034 }
1035 #endif
1036
1037 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1038 {
1039 struct target *target = bank->target;
1040 uint32_t device_id;
1041 int printed;
1042
1043 /* read stm32 device id register */
1044 int retval = target_read_u32(target, 0xE0042000, &device_id);
1045 if (retval != ERROR_OK)
1046 return retval;
1047
1048 if ((device_id & 0x7ff) == 0x410)
1049 {
1050 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1051 buf += printed;
1052 buf_size -= printed;
1053
1054 switch (device_id >> 16)
1055 {
1056 case 0x0000:
1057 snprintf(buf, buf_size, "A");
1058 break;
1059
1060 case 0x2000:
1061 snprintf(buf, buf_size, "B");
1062 break;
1063
1064 case 0x2001:
1065 snprintf(buf, buf_size, "Z");
1066 break;
1067
1068 case 0x2003:
1069 snprintf(buf, buf_size, "Y");
1070 break;
1071
1072 default:
1073 snprintf(buf, buf_size, "unknown");
1074 break;
1075 }
1076 }
1077 else if ((device_id & 0x7ff) == 0x412)
1078 {
1079 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1080 buf += printed;
1081 buf_size -= printed;
1082
1083 switch (device_id >> 16)
1084 {
1085 case 0x1000:
1086 snprintf(buf, buf_size, "A");
1087 break;
1088
1089 default:
1090 snprintf(buf, buf_size, "unknown");
1091 break;
1092 }
1093 }
1094 else if ((device_id & 0x7ff) == 0x414)
1095 {
1096 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1097 buf += printed;
1098 buf_size -= printed;
1099
1100 switch (device_id >> 16)
1101 {
1102 case 0x1000:
1103 snprintf(buf, buf_size, "A");
1104 break;
1105
1106 case 0x1001:
1107 snprintf(buf, buf_size, "Z");
1108 break;
1109
1110 default:
1111 snprintf(buf, buf_size, "unknown");
1112 break;
1113 }
1114 }
1115 else if ((device_id & 0x7ff) == 0x418)
1116 {
1117 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1118 buf += printed;
1119 buf_size -= printed;
1120
1121 switch (device_id >> 16)
1122 {
1123 case 0x1000:
1124 snprintf(buf, buf_size, "A");
1125 break;
1126
1127 case 0x1001:
1128 snprintf(buf, buf_size, "Z");
1129 break;
1130
1131 default:
1132 snprintf(buf, buf_size, "unknown");
1133 break;
1134 }
1135 }
1136 else if ((device_id & 0x7ff) == 0x420)
1137 {
1138 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1139 buf += printed;
1140 buf_size -= printed;
1141
1142 switch (device_id >> 16)
1143 {
1144 case 0x1000:
1145 snprintf(buf, buf_size, "A");
1146 break;
1147
1148 case 0x1001:
1149 snprintf(buf, buf_size, "Z");
1150 break;
1151
1152 default:
1153 snprintf(buf, buf_size, "unknown");
1154 break;
1155 }
1156 }
1157 else if ((device_id & 0x7ff) == 0x428)
1158 {
1159 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1160 buf += printed;
1161 buf_size -= printed;
1162
1163 switch (device_id >> 16)
1164 {
1165 case 0x1000:
1166 snprintf(buf, buf_size, "A");
1167 break;
1168
1169 case 0x1001:
1170 snprintf(buf, buf_size, "Z");
1171 break;
1172
1173 default:
1174 snprintf(buf, buf_size, "unknown");
1175 break;
1176 }
1177 }
1178 else if ((device_id & 0x7ff) == 0x430)
1179 {
1180 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1181 buf += printed;
1182 buf_size -= printed;
1183
1184 switch (device_id >> 16)
1185 {
1186 case 0x1000:
1187 snprintf(buf, buf_size, "A");
1188 break;
1189
1190 default:
1191 snprintf(buf, buf_size, "unknown");
1192 break;
1193 }
1194 }
1195 else
1196 {
1197 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1198 return ERROR_FAIL;
1199 }
1200
1201 return ERROR_OK;
1202 }
1203
1204 COMMAND_HANDLER(stm32x_handle_lock_command)
1205 {
1206 struct target *target = NULL;
1207 struct stm32x_flash_bank *stm32x_info = NULL;
1208
1209 if (CMD_ARGC < 1)
1210 {
1211 command_print(CMD_CTX, "stm32x lock <bank>");
1212 return ERROR_OK;
1213 }
1214
1215 struct flash_bank *bank;
1216 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1217 if (ERROR_OK != retval)
1218 return retval;
1219
1220 stm32x_info = bank->driver_priv;
1221
1222 target = bank->target;
1223
1224 if (target->state != TARGET_HALTED)
1225 {
1226 LOG_ERROR("Target not halted");
1227 return ERROR_TARGET_NOT_HALTED;
1228 }
1229
1230 retval = stm32x_check_operation_supported(bank);
1231 if (ERROR_OK != retval)
1232 return retval;
1233
1234 if (stm32x_erase_options(bank) != ERROR_OK)
1235 {
1236 command_print(CMD_CTX, "stm32x failed to erase options");
1237 return ERROR_OK;
1238 }
1239
1240 /* set readout protection */
1241 stm32x_info->option_bytes.RDP = 0;
1242
1243 if (stm32x_write_options(bank) != ERROR_OK)
1244 {
1245 command_print(CMD_CTX, "stm32x failed to lock device");
1246 return ERROR_OK;
1247 }
1248
1249 command_print(CMD_CTX, "stm32x locked");
1250
1251 return ERROR_OK;
1252 }
1253
1254 COMMAND_HANDLER(stm32x_handle_unlock_command)
1255 {
1256 struct target *target = NULL;
1257
1258 if (CMD_ARGC < 1)
1259 {
1260 command_print(CMD_CTX, "stm32x unlock <bank>");
1261 return ERROR_OK;
1262 }
1263
1264 struct flash_bank *bank;
1265 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1266 if (ERROR_OK != retval)
1267 return retval;
1268
1269 target = bank->target;
1270
1271 if (target->state != TARGET_HALTED)
1272 {
1273 LOG_ERROR("Target not halted");
1274 return ERROR_TARGET_NOT_HALTED;
1275 }
1276
1277 retval = stm32x_check_operation_supported(bank);
1278 if (ERROR_OK != retval)
1279 return retval;
1280
1281 if (stm32x_erase_options(bank) != ERROR_OK)
1282 {
1283 command_print(CMD_CTX, "stm32x failed to unlock device");
1284 return ERROR_OK;
1285 }
1286
1287 if (stm32x_write_options(bank) != ERROR_OK)
1288 {
1289 command_print(CMD_CTX, "stm32x failed to lock device");
1290 return ERROR_OK;
1291 }
1292
1293 command_print(CMD_CTX, "stm32x unlocked.\n"
1294 "INFO: a reset or power cycle is required "
1295 "for the new settings to take effect.");
1296
1297 return ERROR_OK;
1298 }
1299
1300 COMMAND_HANDLER(stm32x_handle_options_read_command)
1301 {
1302 uint32_t optionbyte;
1303 struct target *target = NULL;
1304 struct stm32x_flash_bank *stm32x_info = NULL;
1305
1306 if (CMD_ARGC < 1)
1307 {
1308 command_print(CMD_CTX, "stm32x options_read <bank>");
1309 return ERROR_OK;
1310 }
1311
1312 struct flash_bank *bank;
1313 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1314 if (ERROR_OK != retval)
1315 return retval;
1316
1317 stm32x_info = bank->driver_priv;
1318
1319 target = bank->target;
1320
1321 if (target->state != TARGET_HALTED)
1322 {
1323 LOG_ERROR("Target not halted");
1324 return ERROR_TARGET_NOT_HALTED;
1325 }
1326
1327 retval = stm32x_check_operation_supported(bank);
1328 if (ERROR_OK != retval)
1329 return retval;
1330
1331 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1332 if (retval != ERROR_OK)
1333 return retval;
1334 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1335
1336 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1337 command_print(CMD_CTX, "Option Byte Complement Error");
1338
1339 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1340 command_print(CMD_CTX, "Readout Protection On");
1341 else
1342 command_print(CMD_CTX, "Readout Protection Off");
1343
1344 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1345 command_print(CMD_CTX, "Software Watchdog");
1346 else
1347 command_print(CMD_CTX, "Hardware Watchdog");
1348
1349 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1350 command_print(CMD_CTX, "Stop: No reset generated");
1351 else
1352 command_print(CMD_CTX, "Stop: Reset generated");
1353
1354 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1355 command_print(CMD_CTX, "Standby: No reset generated");
1356 else
1357 command_print(CMD_CTX, "Standby: Reset generated");
1358
1359 if (stm32x_info->has_dual_banks)
1360 {
1361 if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
1362 command_print(CMD_CTX, "Boot: Bank 0");
1363 else
1364 command_print(CMD_CTX, "Boot: Bank 1");
1365 }
1366
1367 return ERROR_OK;
1368 }
1369
1370 COMMAND_HANDLER(stm32x_handle_options_write_command)
1371 {
1372 struct target *target = NULL;
1373 struct stm32x_flash_bank *stm32x_info = NULL;
1374 uint16_t optionbyte = 0xF8;
1375
1376 if (CMD_ARGC < 4)
1377 {
1378 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> "
1379 "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
1380 return ERROR_OK;
1381 }
1382
1383 struct flash_bank *bank;
1384 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1385 if (ERROR_OK != retval)
1386 return retval;
1387
1388 stm32x_info = bank->driver_priv;
1389
1390 target = bank->target;
1391
1392 if (target->state != TARGET_HALTED)
1393 {
1394 LOG_ERROR("Target not halted");
1395 return ERROR_TARGET_NOT_HALTED;
1396 }
1397
1398 retval = stm32x_check_operation_supported(bank);
1399 if (ERROR_OK != retval)
1400 return retval;
1401
1402 /* REVISIT: ignores some options which we will display...
1403 * and doesn't insist on the specified syntax.
1404 */
1405
1406 /* OPT_RDWDGSW */
1407 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1408 {
1409 optionbyte |= (1 << 0);
1410 }
1411 else /* REVISIT must be "HWWDG" then ... */
1412 {
1413 optionbyte &= ~(1 << 0);
1414 }
1415
1416 /* OPT_RDRSTSTOP */
1417 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1418 {
1419 optionbyte |= (1 << 1);
1420 }
1421 else /* REVISIT must be "RSTSTNDBY" then ... */
1422 {
1423 optionbyte &= ~(1 << 1);
1424 }
1425
1426 /* OPT_RDRSTSTDBY */
1427 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1428 {
1429 optionbyte |= (1 << 2);
1430 }
1431 else /* REVISIT must be "RSTSTOP" then ... */
1432 {
1433 optionbyte &= ~(1 << 2);
1434 }
1435
1436 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
1437 {
1438 /* OPT_BFB2 */
1439 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1440 {
1441 optionbyte |= (1 << 3);
1442 }
1443 else
1444 {
1445 optionbyte &= ~(1 << 3);
1446 }
1447 }
1448
1449 if (stm32x_erase_options(bank) != ERROR_OK)
1450 {
1451 command_print(CMD_CTX, "stm32x failed to erase options");
1452 return ERROR_OK;
1453 }
1454
1455 stm32x_info->option_bytes.user_options = optionbyte;
1456
1457 if (stm32x_write_options(bank) != ERROR_OK)
1458 {
1459 command_print(CMD_CTX, "stm32x failed to write options");
1460 return ERROR_OK;
1461 }
1462
1463 command_print(CMD_CTX, "stm32x write options complete.\n"
1464 "INFO: a reset or power cycle is required "
1465 "for the new settings to take effect.");
1466
1467 return ERROR_OK;
1468 }
1469
1470 static int stm32x_mass_erase(struct flash_bank *bank)
1471 {
1472 struct target *target = bank->target;
1473
1474 if (target->state != TARGET_HALTED)
1475 {
1476 LOG_ERROR("Target not halted");
1477 return ERROR_TARGET_NOT_HALTED;
1478 }
1479
1480 /* unlock option flash registers */
1481 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1482 if (retval != ERROR_OK)
1483 return retval;
1484 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1485 if (retval != ERROR_OK)
1486 return retval;
1487
1488 /* mass erase flash memory */
1489 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1490 if (retval != ERROR_OK)
1491 return retval;
1492 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1493 if (retval != ERROR_OK)
1494 return retval;
1495
1496 retval = stm32x_wait_status_busy(bank, 100);
1497 if (retval != ERROR_OK)
1498 return retval;
1499
1500 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1501 if (retval != ERROR_OK)
1502 return retval;
1503
1504 return ERROR_OK;
1505 }
1506
1507 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1508 {
1509 int i;
1510
1511 if (CMD_ARGC < 1)
1512 {
1513 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1514 return ERROR_OK;
1515 }
1516
1517 struct flash_bank *bank;
1518 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1519 if (ERROR_OK != retval)
1520 return retval;
1521
1522 retval = stm32x_mass_erase(bank);
1523 if (retval == ERROR_OK)
1524 {
1525 /* set all sectors as erased */
1526 for (i = 0; i < bank->num_sectors; i++)
1527 {
1528 bank->sectors[i].is_erased = 1;
1529 }
1530
1531 command_print(CMD_CTX, "stm32x mass erase complete");
1532 }
1533 else
1534 {
1535 command_print(CMD_CTX, "stm32x mass erase failed");
1536 }
1537
1538 return retval;
1539 }
1540
1541 static const struct command_registration stm32x_exec_command_handlers[] = {
1542 {
1543 .name = "lock",
1544 .handler = stm32x_handle_lock_command,
1545 .mode = COMMAND_EXEC,
1546 .usage = "bank_id",
1547 .help = "Lock entire flash device.",
1548 },
1549 {
1550 .name = "unlock",
1551 .handler = stm32x_handle_unlock_command,
1552 .mode = COMMAND_EXEC,
1553 .usage = "bank_id",
1554 .help = "Unlock entire protected flash device.",
1555 },
1556 {
1557 .name = "mass_erase",
1558 .handler = stm32x_handle_mass_erase_command,
1559 .mode = COMMAND_EXEC,
1560 .usage = "bank_id",
1561 .help = "Erase entire flash device.",
1562 },
1563 {
1564 .name = "options_read",
1565 .handler = stm32x_handle_options_read_command,
1566 .mode = COMMAND_EXEC,
1567 .usage = "bank_id",
1568 .help = "Read and display device option byte.",
1569 },
1570 {
1571 .name = "options_write",
1572 .handler = stm32x_handle_options_write_command,
1573 .mode = COMMAND_EXEC,
1574 .usage = "bank_id ('SWWDG'|'HWWDG') "
1575 "('RSTSTNDBY'|'NORSTSTNDBY') "
1576 "('RSTSTOP'|'NORSTSTOP')",
1577 .help = "Replace bits in device option byte.",
1578 },
1579 COMMAND_REGISTRATION_DONE
1580 };
1581
1582 static const struct command_registration stm32x_command_handlers[] = {
1583 {
1584 .name = "stm32f1x",
1585 .mode = COMMAND_ANY,
1586 .help = "stm32f1x flash command group",
1587 .chain = stm32x_exec_command_handlers,
1588 },
1589 COMMAND_REGISTRATION_DONE
1590 };
1591
1592 struct flash_driver stm32f1x_flash = {
1593 .name = "stm32f1x",
1594 .commands = stm32x_command_handlers,
1595 .flash_bank_command = stm32x_flash_bank_command,
1596 .erase = stm32x_erase,
1597 .protect = stm32x_protect,
1598 .write = stm32x_write,
1599 .read = default_flash_read,
1600 .probe = stm32x_probe,
1601 .auto_probe = stm32x_auto_probe,
1602 .erase_check = default_flash_mem_blank_check,
1603 .protect_check = stm32x_protect_check,
1604 .info = get_stm32x_info,
1605 };
add intel's jflashmm functionality to openocd