1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include <jtag/interface.h>
37 static uint8_t output_value
= 0x0;
38 static int dev_mem_fd
;
39 static void *gpio_controller
;
40 static volatile uint8_t *gpio_data_register
;
41 static volatile uint8_t *gpio_data_direction_register
;
43 /* low level command set
45 static int ep93xx_read(void);
46 static void ep93xx_write(int tck
, int tms
, int tdi
);
47 static void ep93xx_reset(int trst
, int srst
);
49 static int ep93xx_speed(int speed
);
50 static int ep93xx_init(void);
51 static int ep93xx_quit(void);
53 struct timespec ep93xx_zzzz
;
55 struct jtag_interface ep93xx_interface
=
59 .supported
= DEBUG_CAP_TMS_SEQ
,
60 .execute_queue
= bitbang_execute_queue
,
62 .speed
= ep93xx_speed
,
67 static struct bitbang_interface ep93xx_bitbang
=
70 .write
= ep93xx_write
,
71 .reset
= ep93xx_reset
,
75 static int ep93xx_read(void)
77 return !!(*gpio_data_register
& TDO_BIT
);
80 static void ep93xx_write(int tck
, int tms
, int tdi
)
83 output_value
|= TCK_BIT
;
85 output_value
&= ~TCK_BIT
;
88 output_value
|= TMS_BIT
;
90 output_value
&= ~TMS_BIT
;
93 output_value
|= TDI_BIT
;
95 output_value
&= ~TDI_BIT
;
97 *gpio_data_register
= output_value
;
98 nanosleep(&ep93xx_zzzz
, NULL
);
101 /* (1) assert or (0) deassert reset lines */
102 static void ep93xx_reset(int trst
, int srst
)
105 output_value
|= TRST_BIT
;
107 output_value
&= ~TRST_BIT
;
110 output_value
|= SRST_BIT
;
112 output_value
&= ~SRST_BIT
;
114 *gpio_data_register
= output_value
;
115 nanosleep(&ep93xx_zzzz
, NULL
);
118 static int ep93xx_speed(int speed
)
124 static int set_gonk_mode(void)
129 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
130 MAP_SHARED
, dev_mem_fd
, 0x80930000);
131 if (syscon
== MAP_FAILED
) {
133 return ERROR_JTAG_INIT_FAILED
;
136 devicecfg
= *((volatile int *)(syscon
+ 0x80));
137 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
138 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
140 munmap(syscon
, 4096);
145 static int ep93xx_init(void)
149 bitbang_interface
= &ep93xx_bitbang
;
151 ep93xx_zzzz
.tv_sec
= 0;
152 ep93xx_zzzz
.tv_nsec
= 10000000;
154 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
155 if (dev_mem_fd
< 0) {
157 return ERROR_JTAG_INIT_FAILED
;
160 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
161 MAP_SHARED
, dev_mem_fd
, 0x80840000);
162 if (gpio_controller
== MAP_FAILED
) {
165 return ERROR_JTAG_INIT_FAILED
;
168 ret
= set_gonk_mode();
169 if (ret
!= ERROR_OK
) {
170 munmap(gpio_controller
, 4096);
176 /* Use GPIO port A. */
177 gpio_data_register
= gpio_controller
+ 0x00;
178 gpio_data_direction_register
= gpio_controller
+ 0x10;
181 /* Use GPIO port B. */
182 gpio_data_register
= gpio_controller
+ 0x04;
183 gpio_data_direction_register
= gpio_controller
+ 0x14;
185 /* Use GPIO port C. */
186 gpio_data_register
= gpio_controller
+ 0x08;
187 gpio_data_direction_register
= gpio_controller
+ 0x18;
189 /* Use GPIO port D. */
190 gpio_data_register
= gpio_controller
+ 0x0c;
191 gpio_data_direction_register
= gpio_controller
+ 0x1c;
194 /* Use GPIO port C. */
195 gpio_data_register
= gpio_controller
+ 0x08;
196 gpio_data_direction_register
= gpio_controller
+ 0x18;
198 LOG_INFO("gpio_data_register = %p\n", gpio_data_register
);
199 LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register
);
201 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
202 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
203 * TMS/TRST/SRST high.
205 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
206 *gpio_data_register
= output_value
;
207 nanosleep(&ep93xx_zzzz
, NULL
);
210 * Configure the direction register. 1 = output, 0 = input.
212 *gpio_data_direction_register
=
213 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
215 nanosleep(&ep93xx_zzzz
, NULL
);
219 static int ep93xx_quit(void)