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stlink: export write_debug_reg
[openocd/jflash.git] / src / target / arm_adi_v5.c
blob9a98f61d5652bde9925fb5e726128f85123e11b5
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "jtag/interface.h"
73 #include "arm.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
104 {
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
106
107 if (new_ap != dap->ap_current) {
108 dap->ap_current = new_ap;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
111 */
112 dap->ap_bank_value = -1;
113 dap->ap_csw_value = -1;
114 dap->ap_tar_value = -1;
115 }
116 }
117
118 /**
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
121 *
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
126 *
127 * @todo Rename to reflect it being specifically a MEM-AP function.
128 *
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
134 *
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
136 */
137 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
138 {
139 int retval;
140
141 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
142 if (csw != dap->ap_csw_value) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
145 if (retval != ERROR_OK)
146 return retval;
147 dap->ap_csw_value = csw;
148 }
149 if (tar != dap->ap_tar_value) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
152 if (retval != ERROR_OK)
153 return retval;
154 dap->ap_tar_value = tar;
155 }
156 /* Disable TAR cache when autoincrementing */
157 if (csw & CSW_ADDRINC_MASK)
158 dap->ap_tar_value = -1;
159 return ERROR_OK;
160 }
161
162 /**
163 * Asynchronous (queued) read of a word from memory or a system register.
164 *
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
170 *
171 * @return ERROR_OK for success. Otherwise a fault code.
172 */
173 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
174 uint32_t *value)
175 {
176 int retval;
177
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
180 */
181 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
182 address & 0xFFFFFFF0);
183 if (retval != ERROR_OK)
184 return retval;
185
186 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
187 }
188
189 /**
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
192 *
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
197 *
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
200 */
201 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
202 uint32_t *value)
203 {
204 int retval;
205
206 retval = mem_ap_read_u32(dap, address, value);
207 if (retval != ERROR_OK)
208 return retval;
209
210 return dap_run(dap);
211 }
212
213 /**
214 * Asynchronous (queued) write of a word to memory or a system register.
215 *
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
221 *
222 * @return ERROR_OK for success. Otherwise a fault code.
223 */
224 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
225 uint32_t value)
226 {
227 int retval;
228
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
231 */
232 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
233 address & 0xFFFFFFF0);
234 if (retval != ERROR_OK)
235 return retval;
236
237 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
238 value);
239 }
240
241 /**
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
244 *
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
249 *
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
251 */
252 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
253 uint32_t value)
254 {
255 int retval = mem_ap_write_u32(dap, address, value);
256
257 if (retval != ERROR_OK)
258 return retval;
259
260 return dap_run(dap);
261 }
262
263 /*****************************************************************************
264 * *
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
266 * *
267 * Write a buffer in target order (little endian) *
268 * *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
271 {
272 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
273 uint32_t adr = address;
274 const uint8_t *pBuffer = buffer;
275
276 count >>= 2;
277 wcount = count;
278
279 /* if we have an unaligned access - reorder data */
280 if (adr & 0x3u) {
281 for (writecount = 0; writecount < count; writecount++) {
282 int i;
283 uint32_t outvalue;
284 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
285
286 for (i = 0; i < 4; i++) {
287 *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue;
288 outvalue >>= 8;
289 adr++;
290 }
291 pBuffer += sizeof(uint32_t);
292 }
293 }
294
295 while (wcount > 0) {
296 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
297 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
298 if (wcount < blocksize)
299 blocksize = wcount;
300
301 /* handle unaligned data at 4k boundary */
302 if (blocksize == 0)
303 blocksize = 1;
304
305 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
306 if (retval != ERROR_OK)
307 return retval;
308
309 for (writecount = 0; writecount < blocksize; writecount++) {
310 retval = dap_queue_ap_write(dap, AP_REG_DRW,
311 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
312 if (retval != ERROR_OK)
313 break;
314 }
315
316 retval = dap_run(dap);
317 if (retval == ERROR_OK) {
318 wcount = wcount - blocksize;
319 address = address + 4 * blocksize;
320 buffer = buffer + 4 * blocksize;
321 } else
322 errorcount++;
323
324 if (errorcount > 1) {
325 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
326 return retval;
327 }
328 }
329
330 return retval;
331 }
332
333 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
334 const uint8_t *buffer, int count, uint32_t address)
335 {
336 int retval = ERROR_OK;
337 int wcount, blocksize, writecount, i;
338
339 wcount = count >> 1;
340
341 while (wcount > 0) {
342 int nbytes;
343
344 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
345 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
346
347 if (wcount < blocksize)
348 blocksize = wcount;
349
350 /* handle unaligned data at 4k boundary */
351 if (blocksize == 0)
352 blocksize = 1;
353
354 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
355 if (retval != ERROR_OK)
356 return retval;
357 writecount = blocksize;
358
359 do {
360 nbytes = MIN((writecount << 1), 4);
361
362 if (nbytes < 4) {
363 retval = mem_ap_write_buf_u16(dap, buffer,
364 nbytes, address);
365 if (retval != ERROR_OK) {
366 LOG_WARNING("Block write error address "
367 "0x%" PRIx32 ", count 0x%x",
368 address, count);
369 return retval;
370 }
371
372 address += nbytes >> 1;
373 } else {
374 uint32_t outvalue;
375 memcpy(&outvalue, buffer, sizeof(uint32_t));
376
377 for (i = 0; i < nbytes; i++) {
378 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
379 outvalue >>= 8;
380 address++;
381 }
382
383 memcpy(&outvalue, buffer, sizeof(uint32_t));
384 retval = dap_queue_ap_write(dap,
385 AP_REG_DRW, outvalue);
386 if (retval != ERROR_OK)
387 break;
388
389 retval = dap_run(dap);
390 if (retval != ERROR_OK) {
391 LOG_WARNING("Block write error address "
392 "0x%" PRIx32 ", count 0x%x",
393 address, count);
394 return retval;
395 }
396 }
397
398 buffer += nbytes >> 1;
399 writecount -= nbytes >> 1;
400
401 } while (writecount);
402 wcount -= blocksize;
403 }
404
405 return retval;
406 }
407
408 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
409 {
410 int retval = ERROR_OK;
411
412 if (count >= 4)
413 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
414
415 while (count > 0) {
416 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
417 if (retval != ERROR_OK)
418 return retval;
419 uint16_t svalue;
420 memcpy(&svalue, buffer, sizeof(uint16_t));
421 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
422 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
423 if (retval != ERROR_OK)
424 break;
425
426 retval = dap_run(dap);
427 if (retval != ERROR_OK)
428 break;
429
430 count -= 2;
431 address += 2;
432 buffer += 2;
433 }
434
435 return retval;
436 }
437
438 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
439 const uint8_t *buffer, int count, uint32_t address)
440 {
441 int retval = ERROR_OK;
442 int wcount, blocksize, writecount, i;
443
444 wcount = count;
445
446 while (wcount > 0) {
447 int nbytes;
448
449 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
450 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
451
452 if (wcount < blocksize)
453 blocksize = wcount;
454
455 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
456 if (retval != ERROR_OK)
457 return retval;
458 writecount = blocksize;
459
460 do {
461 nbytes = MIN(writecount, 4);
462
463 if (nbytes < 4) {
464 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
465 if (retval != ERROR_OK) {
466 LOG_WARNING("Block write error address "
467 "0x%" PRIx32 ", count 0x%x",
468 address, count);
469 return retval;
470 }
471
472 address += nbytes;
473 } else {
474 uint32_t outvalue;
475 memcpy(&outvalue, buffer, sizeof(uint32_t));
476
477 for (i = 0; i < nbytes; i++) {
478 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
479 outvalue >>= 8;
480 address++;
481 }
482
483 memcpy(&outvalue, buffer, sizeof(uint32_t));
484 retval = dap_queue_ap_write(dap,
485 AP_REG_DRW, outvalue);
486 if (retval != ERROR_OK)
487 break;
488
489 retval = dap_run(dap);
490 if (retval != ERROR_OK) {
491 LOG_WARNING("Block write error address "
492 "0x%" PRIx32 ", count 0x%x",
493 address, count);
494 return retval;
495 }
496 }
497
498 buffer += nbytes;
499 writecount -= nbytes;
500
501 } while (writecount);
502 wcount -= blocksize;
503 }
504
505 return retval;
506 }
507
508 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
509 {
510 int retval = ERROR_OK;
511
512 if (count >= 4)
513 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
514
515 while (count > 0) {
516 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
517 if (retval != ERROR_OK)
518 return retval;
519 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
520 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
521 if (retval != ERROR_OK)
522 break;
523
524 retval = dap_run(dap);
525 if (retval != ERROR_OK)
526 break;
527
528 count--;
529 address++;
530 buffer++;
531 }
532
533 return retval;
534 }
535
536 /* FIXME don't import ... this is a temporary workaround for the
537 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
538 */
539 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
540 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
541 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
542
543 /**
544 * Synchronously read a block of 32-bit words into a buffer
545 * @param dap The DAP connected to the MEM-AP.
546 * @param buffer where the words will be stored (in host byte order).
547 * @param count How many words to read.
548 * @param address Memory address from which to read words; all the
549 * words must be readable by the currently selected MEM-AP.
550 */
551 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
552 int count, uint32_t address)
553 {
554 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
555 uint32_t adr = address;
556 uint8_t *pBuffer = buffer;
557
558 count >>= 2;
559 wcount = count;
560
561 while (wcount > 0) {
562 /* Adjust to read blocks within boundaries aligned to the
563 * TAR autoincrement size (at least 2^10). Autoincrement
564 * mode avoids an extra per-word roundtrip to update TAR.
565 */
566 blocksize = max_tar_block_size(dap->tar_autoincr_block,
567 address);
568 if (wcount < blocksize)
569 blocksize = wcount;
570
571 /* handle unaligned data at 4k boundary */
572 if (blocksize == 0)
573 blocksize = 1;
574
575 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
576 address);
577 if (retval != ERROR_OK)
578 return retval;
579
580 /* FIXME remove these three calls to adi_jtag_dp_scan(),
581 * so this routine becomes transport-neutral. Be careful
582 * not to cause performance problems with JTAG; would it
583 * suffice to loop over dap_queue_ap_read(), or would that
584 * be slower when JTAG is the chosen transport?
585 */
586
587 /* Scan out first read */
588 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
589 DPAP_READ, 0, NULL, NULL);
590 if (retval != ERROR_OK)
591 return retval;
592 for (readcount = 0; readcount < blocksize - 1; readcount++) {
593 /* Scan out next read; scan in posted value for the
594 * previous one. Assumes read is acked "OK/FAULT",
595 * and CTRL_STAT says that meant "OK".
596 */
597 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
598 DPAP_READ, 0, buffer + 4 * readcount,
599 &dap->ack);
600 if (retval != ERROR_OK)
601 return retval;
602 }
603
604 /* Scan in last posted value; RDBUFF has no other effect,
605 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
606 */
607 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
608 DPAP_READ, 0, buffer + 4 * readcount,
609 &dap->ack);
610 if (retval != ERROR_OK)
611 return retval;
612
613 retval = dap_run(dap);
614 if (retval != ERROR_OK) {
615 errorcount++;
616 if (errorcount <= 1) {
617 /* try again */
618 continue;
619 }
620 LOG_WARNING("Block read error address 0x%" PRIx32, address);
621 return retval;
622 }
623 wcount = wcount - blocksize;
624 address += 4 * blocksize;
625 buffer += 4 * blocksize;
626 }
627
628 /* if we have an unaligned access - reorder data */
629 if (adr & 0x3u) {
630 for (readcount = 0; readcount < count; readcount++) {
631 int i;
632 uint32_t data;
633 memcpy(&data, pBuffer, sizeof(uint32_t));
634
635 for (i = 0; i < 4; i++) {
636 *((uint8_t *)pBuffer) =
637 (data >> 8 * (adr & 0x3));
638 pBuffer++;
639 adr++;
640 }
641 }
642 }
643
644 return retval;
645 }
646
647 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
648 uint8_t *buffer, int count, uint32_t address)
649 {
650 uint32_t invalue;
651 int retval = ERROR_OK;
652 int wcount, blocksize, readcount, i;
653
654 wcount = count >> 1;
655
656 while (wcount > 0) {
657 int nbytes;
658
659 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
660 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
661 if (wcount < blocksize)
662 blocksize = wcount;
663
664 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
665 if (retval != ERROR_OK)
666 return retval;
667
668 /* handle unaligned data at 4k boundary */
669 if (blocksize == 0)
670 blocksize = 1;
671 readcount = blocksize;
672
673 do {
674 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
675 if (retval != ERROR_OK)
676 return retval;
677 retval = dap_run(dap);
678 if (retval != ERROR_OK) {
679 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
680 return retval;
681 }
682
683 nbytes = MIN((readcount << 1), 4);
684
685 for (i = 0; i < nbytes; i++) {
686 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
687 buffer++;
688 address++;
689 }
690
691 readcount -= (nbytes >> 1);
692 } while (readcount);
693 wcount -= blocksize;
694 }
695
696 return retval;
697 }
698
699 /**
700 * Synchronously read a block of 16-bit halfwords into a buffer
701 * @param dap The DAP connected to the MEM-AP.
702 * @param buffer where the halfwords will be stored (in host byte order).
703 * @param count How many halfwords to read.
704 * @param address Memory address from which to read words; all the
705 * words must be readable by the currently selected MEM-AP.
706 */
707 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
708 int count, uint32_t address)
709 {
710 uint32_t invalue, i;
711 int retval = ERROR_OK;
712
713 if (count >= 4)
714 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
715
716 while (count > 0) {
717 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
718 if (retval != ERROR_OK)
719 return retval;
720 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
721 if (retval != ERROR_OK)
722 break;
723
724 retval = dap_run(dap);
725 if (retval != ERROR_OK)
726 break;
727
728 if (address & 0x1) {
729 for (i = 0; i < 2; i++) {
730 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
731 buffer++;
732 address++;
733 }
734 } else {
735 uint16_t svalue = (invalue >> 8 * (address & 0x3));
736 memcpy(buffer, &svalue, sizeof(uint16_t));
737 address += 2;
738 buffer += 2;
739 }
740 count -= 2;
741 }
742
743 return retval;
744 }
745
746 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
747 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
748 *
749 * The solution is to arrange for a large out/in scan in this loop and
750 * and convert data afterwards.
751 */
752 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
753 uint8_t *buffer, int count, uint32_t address)
754 {
755 uint32_t invalue;
756 int retval = ERROR_OK;
757 int wcount, blocksize, readcount, i;
758
759 wcount = count;
760
761 while (wcount > 0) {
762 int nbytes;
763
764 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
765 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
766
767 if (wcount < blocksize)
768 blocksize = wcount;
769
770 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
771 if (retval != ERROR_OK)
772 return retval;
773 readcount = blocksize;
774
775 do {
776 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
777 if (retval != ERROR_OK)
778 return retval;
779 retval = dap_run(dap);
780 if (retval != ERROR_OK) {
781 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
782 return retval;
783 }
784
785 nbytes = MIN(readcount, 4);
786
787 for (i = 0; i < nbytes; i++) {
788 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
789 buffer++;
790 address++;
791 }
792
793 readcount -= nbytes;
794 } while (readcount);
795 wcount -= blocksize;
796 }
797
798 return retval;
799 }
800
801 /**
802 * Synchronously read a block of bytes into a buffer
803 * @param dap The DAP connected to the MEM-AP.
804 * @param buffer where the bytes will be stored.
805 * @param count How many bytes to read.
806 * @param address Memory address from which to read data; all the
807 * data must be readable by the currently selected MEM-AP.
808 */
809 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
810 int count, uint32_t address)
811 {
812 uint32_t invalue;
813 int retval = ERROR_OK;
814
815 if (count >= 4)
816 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
817
818 while (count > 0) {
819 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
820 if (retval != ERROR_OK)
821 return retval;
822 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
823 if (retval != ERROR_OK)
824 return retval;
825 retval = dap_run(dap);
826 if (retval != ERROR_OK)
827 break;
828
829 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
830 count--;
831 address++;
832 buffer++;
833 }
834
835 return retval;
836 }
837
838 /*--------------------------------------------------------------------*/
839 /* Wrapping function with selection of AP */
840 /*--------------------------------------------------------------------*/
841 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
842 uint32_t address, uint32_t *value)
843 {
844 dap_ap_select(swjdp, ap);
845 return mem_ap_read_u32(swjdp, address, value);
846 }
847
848 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
849 uint32_t address, uint32_t value)
850 {
851 dap_ap_select(swjdp, ap);
852 return mem_ap_write_u32(swjdp, address, value);
853 }
854
855 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
856 uint32_t address, uint32_t *value)
857 {
858 dap_ap_select(swjdp, ap);
859 return mem_ap_read_atomic_u32(swjdp, address, value);
860 }
861
862 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
863 uint32_t address, uint32_t value)
864 {
865 dap_ap_select(swjdp, ap);
866 return mem_ap_write_atomic_u32(swjdp, address, value);
867 }
868
869 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
870 uint8_t *buffer, int count, uint32_t address)
871 {
872 dap_ap_select(swjdp, ap);
873 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
874 }
875
876 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
877 uint8_t *buffer, int count, uint32_t address)
878 {
879 dap_ap_select(swjdp, ap);
880 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
881 }
882
883 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
884 uint8_t *buffer, int count, uint32_t address)
885 {
886 dap_ap_select(swjdp, ap);
887 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
888 }
889
890 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
891 const uint8_t *buffer, int count, uint32_t address)
892 {
893 dap_ap_select(swjdp, ap);
894 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
895 }
896
897 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
898 const uint8_t *buffer, int count, uint32_t address)
899 {
900 dap_ap_select(swjdp, ap);
901 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
902 }
903
904 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
905 const uint8_t *buffer, int count, uint32_t address)
906 {
907 dap_ap_select(swjdp, ap);
908 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
909 }
910
911 #define MDM_REG_STAT 0x00
912 #define MDM_REG_CTRL 0x04
913 #define MDM_REG_ID 0xfc
914
915 #define MDM_STAT_FMEACK (1<<0)
916 #define MDM_STAT_FREADY (1<<1)
917 #define MDM_STAT_SYSSEC (1<<2)
918 #define MDM_STAT_SYSRES (1<<3)
919 #define MDM_STAT_FMEEN (1<<5)
920 #define MDM_STAT_BACKDOOREN (1<<6)
921 #define MDM_STAT_LPEN (1<<7)
922 #define MDM_STAT_VLPEN (1<<8)
923 #define MDM_STAT_LLSMODEXIT (1<<9)
924 #define MDM_STAT_VLLSXMODEXIT (1<<10)
925 #define MDM_STAT_CORE_HALTED (1<<16)
926 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
927 #define MDM_STAT_CORESLEEPING (1<<18)
928
929 #define MEM_CTRL_FMEIP (1<<0)
930 #define MEM_CTRL_DBG_DIS (1<<1)
931 #define MEM_CTRL_DBG_REQ (1<<2)
932 #define MEM_CTRL_SYS_RES_REQ (1<<3)
933 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
934 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
935 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
936 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
937
938 /**
939 *
940 */
941 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
942 {
943 uint32_t val;
944 int retval;
945 enum reset_types jtag_reset_config = jtag_get_reset_config();
946
947 dap_ap_select(dap, 1);
948
949 /* first check mdm-ap id register */
950 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
951 if (retval != ERROR_OK)
952 return retval;
953 dap_run(dap);
954
955 if (val != 0x001C0000) {
956 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
957 dap_ap_select(dap, 0);
958 return ERROR_FAIL;
959 }
960
961 /* read and parse status register
962 * it's important that the device is out of
963 * reset here
964 */
965 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
966 if (retval != ERROR_OK)
967 return retval;
968 dap_run(dap);
969
970 LOG_DEBUG("MDM_REG_STAT %08X", val);
971
972 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
973 LOG_DEBUG("MDMAP: system is secured, masserase needed");
974
975 if (!(val & MDM_STAT_FMEEN))
976 LOG_DEBUG("MDMAP: masserase is disabled");
977 else {
978 /* we need to assert reset */
979 if (jtag_reset_config & RESET_HAS_SRST) {
980 /* default to asserting srst */
981 adapter_assert_reset();
982 } else {
983 LOG_DEBUG("SRST not configured");
984 dap_ap_select(dap, 0);
985 return ERROR_FAIL;
986 }
987
988 while (1) {
989 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
990 if (retval != ERROR_OK)
991 return retval;
992 dap_run(dap);
993 /* read status register and wait for ready */
994 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
995 if (retval != ERROR_OK)
996 return retval;
997 dap_run(dap);
998 LOG_DEBUG("MDM_REG_STAT %08X", val);
999
1000 if ((val & 1))
1001 break;
1002 }
1003
1004 while (1) {
1005 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1006 if (retval != ERROR_OK)
1007 return retval;
1008 dap_run(dap);
1009 /* read status register */
1010 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1011 if (retval != ERROR_OK)
1012 return retval;
1013 dap_run(dap);
1014 LOG_DEBUG("MDM_REG_STAT %08X", val);
1015 /* read control register and wait for ready */
1016 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1017 if (retval != ERROR_OK)
1018 return retval;
1019 dap_run(dap);
1020 LOG_DEBUG("MDM_REG_CTRL %08X", val);
1021
1022 if (val == 0x00)
1023 break;
1024 }
1025 }
1026 }
1027
1028 dap_ap_select(dap, 0);
1029
1030 return ERROR_OK;
1031 }
1032
1033 /** */
1034 struct dap_syssec_filter {
1035 /** */
1036 uint32_t idcode;
1037 /** */
1038 int (*dap_init)(struct adiv5_dap *dap);
1039 };
1040
1041 /** */
1042 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1043 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1044 };
1045
1046 /**
1047 *
1048 */
1049 int dap_syssec(struct adiv5_dap *dap)
1050 {
1051 unsigned int i;
1052 struct jtag_tap *tap;
1053
1054 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1055 tap = dap->jtag_info->tap;
1056
1057 while (tap != NULL) {
1058 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1059 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1060 dap_syssec_filter_data[i].dap_init(dap);
1061 }
1062 tap = tap->next_tap;
1063 }
1064 }
1065
1066 return ERROR_OK;
1067 }
1068
1069 /*--------------------------------------------------------------------------*/
1070
1071
1072 /* FIXME don't import ... just initialize as
1073 * part of DAP transport setup
1074 */
1075 extern const struct dap_ops jtag_dp_ops;
1076
1077 /*--------------------------------------------------------------------------*/
1078
1079 /**
1080 * Initialize a DAP. This sets up the power domains, prepares the DP
1081 * for further use, and arranges to use AP #0 for all AP operations
1082 * until dap_ap-select() changes that policy.
1083 *
1084 * @param dap The DAP being initialized.
1085 *
1086 * @todo Rename this. We also need an initialization scheme which account
1087 * for SWD transports not just JTAG; that will need to address differences
1088 * in layering. (JTAG is useful without any debug target; but not SWD.)
1089 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1090 */
1091 int ahbap_debugport_init(struct adiv5_dap *dap)
1092 {
1093 uint32_t ctrlstat;
1094 int cnt = 0;
1095 int retval;
1096
1097 LOG_DEBUG(" ");
1098
1099 /* test for initialized low level jtag hardware
1100 * this always fails for stlink hardware
1101 */
1102 if (!dap->jtag_info) {
1103 LOG_DEBUG("No low level jtag hardware found");
1104 return ERROR_OK;
1105 }
1106
1107 /* JTAG-DP or SWJ-DP, in JTAG mode
1108 * ... for SWD mode this is patched as part
1109 * of link switchover
1110 */
1111 if (!dap->ops)
1112 dap->ops = &jtag_dp_ops;
1113
1114 /* Default MEM-AP setup.
1115 *
1116 * REVISIT AP #0 may be an inappropriate default for this.
1117 * Should we probe, or take a hint from the caller?
1118 * Presumably we can ignore the possibility of multiple APs.
1119 */
1120 dap->ap_current = !0;
1121 dap_ap_select(dap, 0);
1122
1123 /* DP initialization */
1124
1125 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1126 if (retval != ERROR_OK)
1127 return retval;
1128
1129 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1130 if (retval != ERROR_OK)
1131 return retval;
1132
1133 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1134 if (retval != ERROR_OK)
1135 return retval;
1136
1137 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1138 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1139 if (retval != ERROR_OK)
1140 return retval;
1141
1142 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1143 if (retval != ERROR_OK)
1144 return retval;
1145 retval = dap_run(dap);
1146 if (retval != ERROR_OK)
1147 return retval;
1148
1149 /* Check that we have debug power domains activated */
1150 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1151 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1152 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1153 if (retval != ERROR_OK)
1154 return retval;
1155 retval = dap_run(dap);
1156 if (retval != ERROR_OK)
1157 return retval;
1158 alive_sleep(10);
1159 }
1160
1161 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1162 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1163 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1164 if (retval != ERROR_OK)
1165 return retval;
1166 retval = dap_run(dap);
1167 if (retval != ERROR_OK)
1168 return retval;
1169 alive_sleep(10);
1170 }
1171
1172 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1173 if (retval != ERROR_OK)
1174 return retval;
1175 /* With debug power on we can activate OVERRUN checking */
1176 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1177 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1178 if (retval != ERROR_OK)
1179 return retval;
1180 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1181 if (retval != ERROR_OK)
1182 return retval;
1183
1184 dap_syssec(dap);
1185
1186 return ERROR_OK;
1187 }
1188
1189 /* CID interpretation -- see ARM IHI 0029B section 3
1190 * and ARM IHI 0031A table 13-3.
1191 */
1192 static const char *class_description[16] = {
1193 "Reserved", "ROM table", "Reserved", "Reserved",
1194 "Reserved", "Reserved", "Reserved", "Reserved",
1195 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1196 "Reserved", "OptimoDE DESS",
1197 "Generic IP component", "PrimeCell or System component"
1198 };
1199
1200 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1201 {
1202 return cid3 == 0xb1 && cid2 == 0x05
1203 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1204 }
1205
1206 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1207 uint32_t *out_dbgbase, uint32_t *out_apid)
1208 {
1209 uint32_t ap_old;
1210 int retval;
1211 uint32_t dbgbase, apid;
1212
1213 /* AP address is in bits 31:24 of DP_SELECT */
1214 if (ap >= 256)
1215 return ERROR_COMMAND_SYNTAX_ERROR;
1216
1217 ap_old = dap->ap_current;
1218 dap_ap_select(dap, ap);
1219
1220 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1221 if (retval != ERROR_OK)
1222 return retval;
1223 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1224 if (retval != ERROR_OK)
1225 return retval;
1226 retval = dap_run(dap);
1227 if (retval != ERROR_OK)
1228 return retval;
1229
1230 /* Excavate the device ID code */
1231 struct jtag_tap *tap = dap->jtag_info->tap;
1232 while (tap != NULL) {
1233 if (tap->hasidcode)
1234 break;
1235 tap = tap->next_tap;
1236 }
1237 if (tap == NULL || !tap->hasidcode)
1238 return ERROR_OK;
1239
1240 dap_ap_select(dap, ap_old);
1241
1242 /* The asignment happens only here to prevent modification of these
1243 * values before they are certain. */
1244 *out_dbgbase = dbgbase;
1245 *out_apid = apid;
1246
1247 return ERROR_OK;
1248 }
1249
1250 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1251 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1252 {
1253 uint32_t ap_old;
1254 uint32_t romentry, entry_offset = 0, component_base, devtype;
1255 int retval = ERROR_FAIL;
1256
1257 if (ap >= 256)
1258 return ERROR_COMMAND_SYNTAX_ERROR;
1259
1260 ap_old = dap->ap_current;
1261 dap_ap_select(dap, ap);
1262
1263 do {
1264 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1265 entry_offset, &romentry);
1266 if (retval != ERROR_OK)
1267 return retval;
1268
1269 component_base = (dbgbase & 0xFFFFF000)
1270 + (romentry & 0xFFFFF000);
1271
1272 if (romentry & 0x1) {
1273 retval = mem_ap_read_atomic_u32(dap,
1274 (component_base & 0xfffff000) | 0xfcc,
1275 &devtype);
1276 if ((devtype & 0xff) == type) {
1277 *addr = component_base;
1278 retval = ERROR_OK;
1279 break;
1280 }
1281 }
1282 entry_offset += 4;
1283 } while (romentry > 0);
1284
1285 dap_ap_select(dap, ap_old);
1286
1287 return retval;
1288 }
1289
1290 static int dap_info_command(struct command_context *cmd_ctx,
1291 struct adiv5_dap *dap, int ap)
1292 {
1293 int retval;
1294 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1295 int romtable_present = 0;
1296 uint8_t mem_ap;
1297 uint32_t ap_old;
1298
1299 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1300 if (retval != ERROR_OK)
1301 return retval;
1302
1303 ap_old = dap->ap_current;
1304 dap_ap_select(dap, ap);
1305
1306 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1307 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1308 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1309 if (apid) {
1310 switch (apid&0x0F) {
1311 case 0:
1312 command_print(cmd_ctx, "\tType is JTAG-AP");
1313 break;
1314 case 1:
1315 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1316 break;
1317 case 2:
1318 command_print(cmd_ctx, "\tType is MEM-AP APB");
1319 break;
1320 default:
1321 command_print(cmd_ctx, "\tUnknown AP type");
1322 break;
1323 }
1324
1325 /* NOTE: a MEM-AP may have a single CoreSight component that's
1326 * not a ROM table ... or have no such components at all.
1327 */
1328 if (mem_ap)
1329 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1330 } else
1331 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1332
1333 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1334 if (romtable_present) {
1335 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1336 uint16_t entry_offset;
1337
1338 /* bit 16 of apid indicates a memory access port */
1339 if (dbgbase & 0x02)
1340 command_print(cmd_ctx, "\tValid ROM table present");
1341 else
1342 command_print(cmd_ctx, "\tROM table in legacy format");
1343
1344 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1345 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1346 if (retval != ERROR_OK)
1347 return retval;
1348 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1349 if (retval != ERROR_OK)
1350 return retval;
1351 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1352 if (retval != ERROR_OK)
1353 return retval;
1354 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1355 if (retval != ERROR_OK)
1356 return retval;
1357 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1358 if (retval != ERROR_OK)
1359 return retval;
1360 retval = dap_run(dap);
1361 if (retval != ERROR_OK)
1362 return retval;
1363
1364 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1365 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1366 ", CID2 0x%2.2x"
1367 ", CID1 0x%2.2x"
1368 ", CID0 0x%2.2x",
1369 (unsigned) cid3, (unsigned)cid2,
1370 (unsigned) cid1, (unsigned) cid0);
1371 if (memtype & 0x01)
1372 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1373 else
1374 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1375 "Dedicated debug bus.");
1376
1377 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1378 entry_offset = 0;
1379 do {
1380 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1381 if (retval != ERROR_OK)
1382 return retval;
1383 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1384 if (romentry & 0x01) {
1385 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1386 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1387 uint32_t component_base;
1388 unsigned part_num;
1389 char *type, *full;
1390
1391 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1392
1393 /* IDs are in last 4K section */
1394 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1395 if (retval != ERROR_OK)
1396 return retval;
1397 c_pid0 &= 0xff;
1398 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1399 if (retval != ERROR_OK)
1400 return retval;
1401 c_pid1 &= 0xff;
1402 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1403 if (retval != ERROR_OK)
1404 return retval;
1405 c_pid2 &= 0xff;
1406 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1407 if (retval != ERROR_OK)
1408 return retval;
1409 c_pid3 &= 0xff;
1410 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1411 if (retval != ERROR_OK)
1412 return retval;
1413 c_pid4 &= 0xff;
1414
1415 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1416 if (retval != ERROR_OK)
1417 return retval;
1418 c_cid0 &= 0xff;
1419 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1420 if (retval != ERROR_OK)
1421 return retval;
1422 c_cid1 &= 0xff;
1423 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1424 if (retval != ERROR_OK)
1425 return retval;
1426 c_cid2 &= 0xff;
1427 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1428 if (retval != ERROR_OK)
1429 return retval;
1430 c_cid3 &= 0xff;
1431
1432 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1433 "start address 0x%" PRIx32, component_base,
1434 /* component may take multiple 4K pages */
1435 component_base - 0x1000*(c_pid4 >> 4));
1436 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1437 (int) (c_cid1 >> 4) & 0xf,
1438 /* See ARM IHI 0029B Table 3-3 */
1439 class_description[(c_cid1 >> 4) & 0xf]);
1440
1441 /* CoreSight component? */
1442 if (((c_cid1 >> 4) & 0x0f) == 9) {
1443 uint32_t devtype;
1444 unsigned minor;
1445 char *major = "Reserved", *subtype = "Reserved";
1446
1447 retval = mem_ap_read_atomic_u32(dap,
1448 (component_base & 0xfffff000) | 0xfcc,
1449 &devtype);
1450 if (retval != ERROR_OK)
1451 return retval;
1452 minor = (devtype >> 4) & 0x0f;
1453 switch (devtype & 0x0f) {
1454 case 0:
1455 major = "Miscellaneous";
1456 switch (minor) {
1457 case 0:
1458 subtype = "other";
1459 break;
1460 case 4:
1461 subtype = "Validation component";
1462 break;
1463 }
1464 break;
1465 case 1:
1466 major = "Trace Sink";
1467 switch (minor) {
1468 case 0:
1469 subtype = "other";
1470 break;
1471 case 1:
1472 subtype = "Port";
1473 break;
1474 case 2:
1475 subtype = "Buffer";
1476 break;
1477 }
1478 break;
1479 case 2:
1480 major = "Trace Link";
1481 switch (minor) {
1482 case 0:
1483 subtype = "other";
1484 break;
1485 case 1:
1486 subtype = "Funnel, router";
1487 break;
1488 case 2:
1489 subtype = "Filter";
1490 break;
1491 case 3:
1492 subtype = "FIFO, buffer";
1493 break;
1494 }
1495 break;
1496 case 3:
1497 major = "Trace Source";
1498 switch (minor) {
1499 case 0:
1500 subtype = "other";
1501 break;
1502 case 1:
1503 subtype = "Processor";
1504 break;
1505 case 2:
1506 subtype = "DSP";
1507 break;
1508 case 3:
1509 subtype = "Engine/Coprocessor";
1510 break;
1511 case 4:
1512 subtype = "Bus";
1513 break;
1514 }
1515 break;
1516 case 4:
1517 major = "Debug Control";
1518 switch (minor) {
1519 case 0:
1520 subtype = "other";
1521 break;
1522 case 1:
1523 subtype = "Trigger Matrix";
1524 break;
1525 case 2:
1526 subtype = "Debug Auth";
1527 break;
1528 }
1529 break;
1530 case 5:
1531 major = "Debug Logic";
1532 switch (minor) {
1533 case 0:
1534 subtype = "other";
1535 break;
1536 case 1:
1537 subtype = "Processor";
1538 break;
1539 case 2:
1540 subtype = "DSP";
1541 break;
1542 case 3:
1543 subtype = "Engine/Coprocessor";
1544 break;
1545 }
1546 break;
1547 }
1548 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1549 (unsigned) (devtype & 0xff),
1550 major, subtype);
1551 /* REVISIT also show 0xfc8 DevId */
1552 }
1553
1554 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1555 command_print(cmd_ctx,
1556 "\t\tCID3 0%2.2x"
1557 ", CID2 0%2.2x"
1558 ", CID1 0%2.2x"
1559 ", CID0 0%2.2x",
1560 (int) c_cid3,
1561 (int) c_cid2,
1562 (int)c_cid1,
1563 (int)c_cid0);
1564 command_print(cmd_ctx,
1565 "\t\tPeripheral ID[4..0] = hex "
1566 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1567 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1568 (int) c_pid1, (int) c_pid0);
1569
1570 /* Part number interpretations are from Cortex
1571 * core specs, the CoreSight components TRM
1572 * (ARM DDI 0314H), CoreSight System Design
1573 * Guide (ARM DGI 0012D) and ETM specs; also
1574 * from chip observation (e.g. TI SDTI).
1575 */
1576 part_num = (c_pid0 & 0xff);
1577 part_num |= (c_pid1 & 0x0f) << 8;
1578 switch (part_num) {
1579 case 0x000:
1580 type = "Cortex-M3 NVIC";
1581 full = "(Interrupt Controller)";
1582 break;
1583 case 0x001:
1584 type = "Cortex-M3 ITM";
1585 full = "(Instrumentation Trace Module)";
1586 break;
1587 case 0x002:
1588 type = "Cortex-M3 DWT";
1589 full = "(Data Watchpoint and Trace)";
1590 break;
1591 case 0x003:
1592 type = "Cortex-M3 FBP";
1593 full = "(Flash Patch and Breakpoint)";
1594 break;
1595 case 0x00d:
1596 type = "CoreSight ETM11";
1597 full = "(Embedded Trace)";
1598 break;
1599 /* case 0x113: what? */
1600 case 0x120: /* from OMAP3 memmap */
1601 type = "TI SDTI";
1602 full = "(System Debug Trace Interface)";
1603 break;
1604 case 0x343: /* from OMAP3 memmap */
1605 type = "TI DAPCTL";
1606 full = "";
1607 break;
1608 case 0x906:
1609 type = "Coresight CTI";
1610 full = "(Cross Trigger)";
1611 break;
1612 case 0x907:
1613 type = "Coresight ETB";
1614 full = "(Trace Buffer)";
1615 break;
1616 case 0x908:
1617 type = "Coresight CSTF";
1618 full = "(Trace Funnel)";
1619 break;
1620 case 0x910:
1621 type = "CoreSight ETM9";
1622 full = "(Embedded Trace)";
1623 break;
1624 case 0x912:
1625 type = "Coresight TPIU";
1626 full = "(Trace Port Interface Unit)";
1627 break;
1628 case 0x921:
1629 type = "Cortex-A8 ETM";
1630 full = "(Embedded Trace)";
1631 break;
1632 case 0x922:
1633 type = "Cortex-A8 CTI";
1634 full = "(Cross Trigger)";
1635 break;
1636 case 0x923:
1637 type = "Cortex-M3 TPIU";
1638 full = "(Trace Port Interface Unit)";
1639 break;
1640 case 0x924:
1641 type = "Cortex-M3 ETM";
1642 full = "(Embedded Trace)";
1643 break;
1644 case 0x930:
1645 type = "Cortex-R4 ETM";
1646 full = "(Embedded Trace)";
1647 break;
1648 case 0xc08:
1649 type = "Cortex-A8 Debug";
1650 full = "(Debug Unit)";
1651 break;
1652 default:
1653 type = "-*- unrecognized -*-";
1654 full = "";
1655 break;
1656 }
1657 command_print(cmd_ctx, "\t\tPart is %s %s",
1658 type, full);
1659 } else {
1660 if (romentry)
1661 command_print(cmd_ctx, "\t\tComponent not present");
1662 else
1663 command_print(cmd_ctx, "\t\tEnd of ROM table");
1664 }
1665 entry_offset += 4;
1666 } while (romentry > 0);
1667 } else
1668 command_print(cmd_ctx, "\tNo ROM table present");
1669 dap_ap_select(dap, ap_old);
1670
1671 return ERROR_OK;
1672 }
1673
1674 COMMAND_HANDLER(handle_dap_info_command)
1675 {
1676 struct target *target = get_current_target(CMD_CTX);
1677 struct arm *arm = target_to_arm(target);
1678 struct adiv5_dap *dap = arm->dap;
1679 uint32_t apsel;
1680
1681 switch (CMD_ARGC) {
1682 case 0:
1683 apsel = dap->apsel;
1684 break;
1685 case 1:
1686 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1687 break;
1688 default:
1689 return ERROR_COMMAND_SYNTAX_ERROR;
1690 }
1691
1692 return dap_info_command(CMD_CTX, dap, apsel);
1693 }
1694
1695 COMMAND_HANDLER(dap_baseaddr_command)
1696 {
1697 struct target *target = get_current_target(CMD_CTX);
1698 struct arm *arm = target_to_arm(target);
1699 struct adiv5_dap *dap = arm->dap;
1700
1701 uint32_t apsel, baseaddr;
1702 int retval;
1703
1704 switch (CMD_ARGC) {
1705 case 0:
1706 apsel = dap->apsel;
1707 break;
1708 case 1:
1709 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1710 /* AP address is in bits 31:24 of DP_SELECT */
1711 if (apsel >= 256)
1712 return ERROR_COMMAND_SYNTAX_ERROR;
1713 break;
1714 default:
1715 return ERROR_COMMAND_SYNTAX_ERROR;
1716 }
1717
1718 dap_ap_select(dap, apsel);
1719
1720 /* NOTE: assumes we're talking to a MEM-AP, which
1721 * has a base address. There are other kinds of AP,
1722 * though they're not common for now. This should
1723 * use the ID register to verify it's a MEM-AP.
1724 */
1725 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1726 if (retval != ERROR_OK)
1727 return retval;
1728 retval = dap_run(dap);
1729 if (retval != ERROR_OK)
1730 return retval;
1731
1732 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1733
1734 return retval;
1735 }
1736
1737 COMMAND_HANDLER(dap_memaccess_command)
1738 {
1739 struct target *target = get_current_target(CMD_CTX);
1740 struct arm *arm = target_to_arm(target);
1741 struct adiv5_dap *dap = arm->dap;
1742
1743 uint32_t memaccess_tck;
1744
1745 switch (CMD_ARGC) {
1746 case 0:
1747 memaccess_tck = dap->memaccess_tck;
1748 break;
1749 case 1:
1750 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1751 break;
1752 default:
1753 return ERROR_COMMAND_SYNTAX_ERROR;
1754 }
1755 dap->memaccess_tck = memaccess_tck;
1756
1757 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1758 dap->memaccess_tck);
1759
1760 return ERROR_OK;
1761 }
1762
1763 COMMAND_HANDLER(dap_apsel_command)
1764 {
1765 struct target *target = get_current_target(CMD_CTX);
1766 struct arm *arm = target_to_arm(target);
1767 struct adiv5_dap *dap = arm->dap;
1768
1769 uint32_t apsel, apid;
1770 int retval;
1771
1772 switch (CMD_ARGC) {
1773 case 0:
1774 apsel = 0;
1775 break;
1776 case 1:
1777 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1778 /* AP address is in bits 31:24 of DP_SELECT */
1779 if (apsel >= 256)
1780 return ERROR_COMMAND_SYNTAX_ERROR;
1781 break;
1782 default:
1783 return ERROR_COMMAND_SYNTAX_ERROR;
1784 }
1785
1786 dap->apsel = apsel;
1787 dap_ap_select(dap, apsel);
1788
1789 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1790 if (retval != ERROR_OK)
1791 return retval;
1792 retval = dap_run(dap);
1793 if (retval != ERROR_OK)
1794 return retval;
1795
1796 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1797 apsel, apid);
1798
1799 return retval;
1800 }
1801
1802 COMMAND_HANDLER(dap_apid_command)
1803 {
1804 struct target *target = get_current_target(CMD_CTX);
1805 struct arm *arm = target_to_arm(target);
1806 struct adiv5_dap *dap = arm->dap;
1807
1808 uint32_t apsel, apid;
1809 int retval;
1810
1811 switch (CMD_ARGC) {
1812 case 0:
1813 apsel = dap->apsel;
1814 break;
1815 case 1:
1816 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1817 /* AP address is in bits 31:24 of DP_SELECT */
1818 if (apsel >= 256)
1819 return ERROR_COMMAND_SYNTAX_ERROR;
1820 break;
1821 default:
1822 return ERROR_COMMAND_SYNTAX_ERROR;
1823 }
1824
1825 dap_ap_select(dap, apsel);
1826
1827 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1828 if (retval != ERROR_OK)
1829 return retval;
1830 retval = dap_run(dap);
1831 if (retval != ERROR_OK)
1832 return retval;
1833
1834 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1835
1836 return retval;
1837 }
1838
1839 static const struct command_registration dap_commands[] = {
1840 {
1841 .name = "info",
1842 .handler = handle_dap_info_command,
1843 .mode = COMMAND_EXEC,
1844 .help = "display ROM table for MEM-AP "
1845 "(default currently selected AP)",
1846 .usage = "[ap_num]",
1847 },
1848 {
1849 .name = "apsel",
1850 .handler = dap_apsel_command,
1851 .mode = COMMAND_EXEC,
1852 .help = "Set the currently selected AP (default 0) "
1853 "and display the result",
1854 .usage = "[ap_num]",
1855 },
1856 {
1857 .name = "apid",
1858 .handler = dap_apid_command,
1859 .mode = COMMAND_EXEC,
1860 .help = "return ID register from AP "
1861 "(default currently selected AP)",
1862 .usage = "[ap_num]",
1863 },
1864 {
1865 .name = "baseaddr",
1866 .handler = dap_baseaddr_command,
1867 .mode = COMMAND_EXEC,
1868 .help = "return debug base address from MEM-AP "
1869 "(default currently selected AP)",
1870 .usage = "[ap_num]",
1871 },
1872 {
1873 .name = "memaccess",
1874 .handler = dap_memaccess_command,
1875 .mode = COMMAND_EXEC,
1876 .help = "set/get number of extra tck for MEM-AP memory "
1877 "bus access [0-255]",
1878 .usage = "[cycles]",
1879 },
1880 COMMAND_REGISTRATION_DONE
1881 };
1882
1883 const struct command_registration dap_command_handlers[] = {
1884 {
1885 .name = "dap",
1886 .mode = COMMAND_EXEC,
1887 .help = "DAP command group",
1888 .usage = "",
1889 .chain = dap_commands,
1890 },
1891 COMMAND_REGISTRATION_DONE
1892 };
add intel's jflashmm functionality to openocd