1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
48 /* FLASH_CR0 register bits */
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
62 /* FLASH_CR1 register bits */
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
77 /* FLASH_ER register bits */
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
88 struct str7x_flash_bank
90 uint32_t *sector_bits
;
93 uint32_t register_base
;
94 struct working_area
*write_algorithm
;
97 struct str7x_mem_layout
{
98 uint32_t sector_start
;
103 enum str7x_status_codes
105 STR7X_CMD_SUCCESS
= 0,
106 STR7X_INVALID_COMMAND
= 1,
107 STR7X_SRC_ADDR_ERROR
= 2,
108 STR7X_DST_ADDR_ERROR
= 3,
109 STR7X_SRC_ADDR_NOT_MAPPED
= 4,
110 STR7X_DST_ADDR_NOT_MAPPED
= 5,
111 STR7X_COUNT_ERROR
= 6,
112 STR7X_INVALID_SECTOR
= 7,
113 STR7X_SECTOR_NOT_BLANK
= 8,
114 STR7X_SECTOR_NOT_PREPARED
= 9,
115 STR7X_COMPARE_ERROR
= 10,
119 static struct str7x_mem_layout mem_layout_str7bank0
[] = {
120 {0x00000000, 0x02000, 0x01},
121 {0x00002000, 0x02000, 0x02},
122 {0x00004000, 0x02000, 0x04},
123 {0x00006000, 0x02000, 0x08},
124 {0x00008000, 0x08000, 0x10},
125 {0x00010000, 0x10000, 0x20},
126 {0x00020000, 0x10000, 0x40},
127 {0x00030000, 0x10000, 0x80}
130 static struct str7x_mem_layout mem_layout_str7bank1
[] = {
131 {0x00000000, 0x02000, 0x10000},
132 {0x00002000, 0x02000, 0x20000}
135 static int str7x_get_flash_adr(struct flash_bank
*bank
, uint32_t reg
)
137 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
138 return (str7x_info
->register_base
| reg
);
141 static int str7x_build_block_list(struct flash_bank
*bank
)
143 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
147 int b0_sectors
= 0, b1_sectors
= 0;
164 LOG_ERROR("BUG: unknown bank->size encountered");
168 num_sectors
= b0_sectors
+ b1_sectors
;
170 bank
->num_sectors
= num_sectors
;
171 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
172 str7x_info
->sector_bits
= malloc(sizeof(uint32_t) * num_sectors
);
176 for (i
= 0; i
< b0_sectors
; i
++)
178 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank0
[i
].sector_start
;
179 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank0
[i
].sector_size
;
180 bank
->sectors
[num_sectors
].is_erased
= -1;
181 /* the reset_init handler marks all the sectors unprotected,
182 * matching hardware after reset; keep the driver in sync
184 bank
->sectors
[num_sectors
].is_protected
= 0;
185 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank0
[i
].sector_bit
;
188 for (i
= 0; i
< b1_sectors
; i
++)
190 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank1
[i
].sector_start
;
191 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank1
[i
].sector_size
;
192 bank
->sectors
[num_sectors
].is_erased
= -1;
193 /* the reset_init handler marks all the sectors unprotected,
194 * matching hardware after reset; keep the driver in sync
196 bank
->sectors
[num_sectors
].is_protected
= 0;
197 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank1
[i
].sector_bit
;
203 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
205 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command
)
207 struct str7x_flash_bank
*str7x_info
;
211 return ERROR_COMMAND_SYNTAX_ERROR
;
214 str7x_info
= malloc(sizeof(struct str7x_flash_bank
));
215 bank
->driver_priv
= str7x_info
;
217 /* set default bits for str71x flash */
218 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA1
| FLASH_BSYA0
);
219 str7x_info
->disable_bit
= (1 << 1);
221 if (strcmp(CMD_ARGV
[6], "STR71x") == 0)
223 str7x_info
->register_base
= 0x40100000;
225 else if (strcmp(CMD_ARGV
[6], "STR73x") == 0)
227 str7x_info
->register_base
= 0x80100000;
228 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA0
);
230 else if (strcmp(CMD_ARGV
[6], "STR75x") == 0)
232 str7x_info
->register_base
= 0x20100000;
233 str7x_info
->disable_bit
= (1 << 0);
237 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV
[6]);
239 return ERROR_FLASH_BANK_INVALID
;
242 str7x_build_block_list(bank
);
244 str7x_info
->write_algorithm
= NULL
;
249 /* wait for flash to become idle or report errors.
251 FIX!!! what's the maximum timeout??? The documentation doesn't
252 state any maximum time.... by inspection it seems > 1000ms is to be
255 10000ms is long enough that it should cover anything, yet not
256 quite be equivalent to an infinite loop.
259 static int str7x_waitbusy(struct flash_bank
*bank
)
263 struct target
*target
= bank
->target
;
264 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
266 for (i
= 0 ; i
< 10000; i
++)
269 err
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), &retval
);
273 if ((retval
& str7x_info
->busy_bits
) == 0)
278 LOG_ERROR("Timed out waiting for str7x flash");
283 static int str7x_result(struct flash_bank
*bank
)
285 struct target
*target
= bank
->target
;
286 uint32_t flash_flags
;
289 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), &flash_flags
);
290 if (retval
!= ERROR_OK
)
293 if (flash_flags
& FLASH_WPF
)
295 LOG_ERROR("str7x hw write protection set");
298 if (flash_flags
& FLASH_RESER
)
300 LOG_ERROR("str7x suspended program erase not resumed");
303 if (flash_flags
& FLASH_10ER
)
305 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
308 if (flash_flags
& FLASH_PGER
)
310 LOG_ERROR("str7x program error");
313 if (flash_flags
& FLASH_ERER
)
315 LOG_ERROR("str7x erase error");
318 if (retval
== ERROR_OK
)
320 if (flash_flags
& FLASH_ERR
)
322 /* this should always be set if one of the others are set... */
323 LOG_ERROR("str7x write operation failed / bad setup");
331 static int str7x_protect_check(struct flash_bank
*bank
)
333 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
334 struct target
*target
= bank
->target
;
337 uint32_t flash_flags
;
339 if (bank
->target
->state
!= TARGET_HALTED
)
341 LOG_ERROR("Target not halted");
342 return ERROR_TARGET_NOT_HALTED
;
346 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVWPAR
), &flash_flags
);
347 if (retval
!= ERROR_OK
)
350 for (i
= 0; i
< bank
->num_sectors
; i
++)
352 if (flash_flags
& str7x_info
->sector_bits
[i
])
353 bank
->sectors
[i
].is_protected
= 0;
355 bank
->sectors
[i
].is_protected
= 1;
361 static int str7x_erase(struct flash_bank
*bank
, int first
, int last
)
363 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
364 struct target
*target
= bank
->target
;
368 uint32_t sectors
= 0;
371 if (bank
->target
->state
!= TARGET_HALTED
)
373 LOG_ERROR("Target not halted");
374 return ERROR_TARGET_NOT_HALTED
;
377 for (i
= first
; i
<= last
; i
++)
379 sectors
|= str7x_info
->sector_bits
[i
];
382 LOG_DEBUG("sectors: 0x%" PRIx32
"", sectors
);
384 /* clear FLASH_ER register */
385 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
390 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
395 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR1
), cmd
);
399 cmd
= FLASH_SER
| FLASH_WMS
;
400 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
404 err
= str7x_waitbusy(bank
);
408 err
= str7x_result(bank
);
412 for (i
= first
; i
<= last
; i
++)
413 bank
->sectors
[i
].is_erased
= 1;
418 static int str7x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
420 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
421 struct target
*target
= bank
->target
;
424 uint32_t protect_blocks
;
426 if (bank
->target
->state
!= TARGET_HALTED
)
428 LOG_ERROR("Target not halted");
429 return ERROR_TARGET_NOT_HALTED
;
432 protect_blocks
= 0xFFFFFFFF;
436 for (i
= first
; i
<= last
; i
++)
437 protect_blocks
&= ~(str7x_info
->sector_bits
[i
]);
440 /* clear FLASH_ER register */
442 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
447 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
451 cmd
= str7x_get_flash_adr(bank
, FLASH_NVWPAR
);
452 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), cmd
);
456 cmd
= protect_blocks
;
457 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), cmd
);
461 cmd
= FLASH_SPR
| FLASH_WMS
;
462 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
466 err
= str7x_waitbusy(bank
);
470 err
= str7x_result(bank
);
477 static int str7x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
478 uint32_t offset
, uint32_t count
)
480 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
481 struct target
*target
= bank
->target
;
482 uint32_t buffer_size
= 32768;
483 struct working_area
*source
;
484 uint32_t address
= bank
->base
+ offset
;
485 struct reg_param reg_params
[6];
486 struct arm_algorithm armv4_5_info
;
487 int retval
= ERROR_OK
;
489 /* see contib/loaders/flash/str7x.s for src */
491 static const uint32_t str7x_flash_write_code
[] = {
493 0xe3a04201, /* mov r4, #0x10000000 */
494 0xe5824000, /* str r4, [r2, #0x0] */
495 0xe5821010, /* str r1, [r2, #0x10] */
496 0xe4904004, /* ldr r4, [r0], #4 */
497 0xe5824008, /* str r4, [r2, #0x8] */
498 0xe4904004, /* ldr r4, [r0], #4 */
499 0xe582400c, /* str r4, [r2, #0xc] */
500 0xe3a04209, /* mov r4, #0x90000000 */
501 0xe5824000, /* str r4, [r2, #0x0] */
503 0xe5924000, /* ldr r4, [r2, #0x0] */
504 0xe1140005, /* tst r4, r5 */
505 0x1afffffc, /* bne busy */
506 0xe5924014, /* ldr r4, [r2, #0x14] */
507 0xe31400ff, /* tst r4, #0xff */
508 0x03140c01, /* tsteq r4, #0x100 */
509 0x1a000002, /* bne exit */
510 0xe2811008, /* add r1, r1, #0x8 */
511 0xe2533001, /* subs r3, r3, #1 */
512 0x1affffec, /* bne write */
514 0xeafffffe, /* b exit */
517 /* flash write code */
518 if (target_alloc_working_area_try(target
, sizeof(str7x_flash_write_code
),
519 &str7x_info
->write_algorithm
) != ERROR_OK
)
521 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
524 target_write_buffer(target
, str7x_info
->write_algorithm
->address
,
525 sizeof(str7x_flash_write_code
),
526 (uint8_t*)str7x_flash_write_code
);
529 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
532 if (buffer_size
<= 256)
534 /* if we already allocated the writing code, but failed to get a
535 * buffer, free the algorithm */
536 if (str7x_info
->write_algorithm
)
537 target_free_working_area(target
, str7x_info
->write_algorithm
);
539 LOG_WARNING("no large enough working area available, can't do block memory writes");
540 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
544 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
545 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
546 armv4_5_info
.core_state
= ARM_STATE_ARM
;
548 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
549 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
550 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
551 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
552 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
553 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
557 uint32_t thisrun_count
= (count
> (buffer_size
/ 8)) ? (buffer_size
/ 8) : count
;
559 target_write_buffer(target
, source
->address
, thisrun_count
* 8, buffer
);
561 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
562 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
563 buf_set_u32(reg_params
[2].value
, 0, 32, str7x_get_flash_adr(bank
, FLASH_CR0
));
564 buf_set_u32(reg_params
[3].value
, 0, 32, thisrun_count
);
565 buf_set_u32(reg_params
[5].value
, 0, 32, str7x_info
->busy_bits
);
567 if ((retval
= target_run_algorithm(target
, 0, NULL
, 6, reg_params
,
568 str7x_info
->write_algorithm
->address
,
569 str7x_info
->write_algorithm
->address
+ (sizeof(str7x_flash_write_code
) - 4),
570 10000, &armv4_5_info
)) != ERROR_OK
)
575 if (buf_get_u32(reg_params
[4].value
, 0, 32) != 0x00)
577 retval
= str7x_result(bank
);
581 buffer
+= thisrun_count
* 8;
582 address
+= thisrun_count
* 8;
583 count
-= thisrun_count
;
586 target_free_working_area(target
, source
);
587 target_free_working_area(target
, str7x_info
->write_algorithm
);
589 destroy_reg_param(®_params
[0]);
590 destroy_reg_param(®_params
[1]);
591 destroy_reg_param(®_params
[2]);
592 destroy_reg_param(®_params
[3]);
593 destroy_reg_param(®_params
[4]);
594 destroy_reg_param(®_params
[5]);
599 static int str7x_write(struct flash_bank
*bank
, uint8_t *buffer
,
600 uint32_t offset
, uint32_t count
)
602 struct target
*target
= bank
->target
;
603 uint32_t dwords_remaining
= (count
/ 8);
604 uint32_t bytes_remaining
= (count
& 0x00000007);
605 uint32_t address
= bank
->base
+ offset
;
606 uint32_t bytes_written
= 0;
609 uint32_t check_address
= offset
;
612 if (bank
->target
->state
!= TARGET_HALTED
)
614 LOG_ERROR("Target not halted");
615 return ERROR_TARGET_NOT_HALTED
;
620 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment", offset
);
621 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
624 for (i
= 0; i
< bank
->num_sectors
; i
++)
626 uint32_t sec_start
= bank
->sectors
[i
].offset
;
627 uint32_t sec_end
= sec_start
+ bank
->sectors
[i
].size
;
629 /* check if destination falls within the current sector */
630 if ((check_address
>= sec_start
) && (check_address
< sec_end
))
632 /* check if destination ends in the current sector */
633 if (offset
+ count
< sec_end
)
634 check_address
= offset
+ count
;
636 check_address
= sec_end
;
640 if (check_address
!= offset
+ count
)
641 return ERROR_FLASH_DST_OUT_OF_BANK
;
643 /* clear FLASH_ER register */
644 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
646 /* multiple dwords (8-byte) to be programmed? */
647 if (dwords_remaining
> 0)
649 /* try using a block write */
650 if ((retval
= str7x_write_block(bank
, buffer
, offset
,
651 dwords_remaining
)) != ERROR_OK
)
653 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
655 /* if block write failed (no sufficient working area),
656 * we use normal (slow) single dword accesses */
657 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
665 buffer
+= dwords_remaining
* 8;
666 address
+= dwords_remaining
* 8;
667 dwords_remaining
= 0;
671 while (dwords_remaining
> 0)
675 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
678 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
681 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
682 4, 1, buffer
+ bytes_written
);
686 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
687 4, 1, buffer
+ bytes_written
);
690 /* start programming cycle */
691 cmd
= FLASH_DWPG
| FLASH_WMS
;
692 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
695 err
= str7x_waitbusy(bank
);
699 err
= str7x_result(bank
);
709 uint8_t last_dword
[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
711 /* copy the last remaining bytes into the write buffer */
712 memcpy(last_dword
, buffer
+bytes_written
, bytes_remaining
);
716 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
719 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
722 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
726 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
727 4, 1, last_dword
+ 4);
729 /* start programming cycle */
730 cmd
= FLASH_DWPG
| FLASH_WMS
;
731 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
734 err
= str7x_waitbusy(bank
);
738 err
= str7x_result(bank
);
746 static int str7x_probe(struct flash_bank
*bank
)
752 COMMAND_HANDLER(str7x_handle_part_id_command
)
758 static int get_str7x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
760 snprintf(buf
, buf_size
, "str7x flash driver info");
761 /* STR7x flash doesn't support sector protection interrogation.
762 * FLASH_NVWPAR acts as a write only register; its read value
763 * doesn't reflect the actual protection state of the sectors.
765 LOG_WARNING("STR7x flash lock information might not be correct "
766 "due to hardware limitations.");
770 COMMAND_HANDLER(str7x_handle_disable_jtag_command
)
772 struct target
*target
= NULL
;
773 struct str7x_flash_bank
*str7x_info
= NULL
;
776 uint16_t ProtectionLevel
= 0;
777 uint16_t ProtectionRegs
;
781 return ERROR_COMMAND_SYNTAX_ERROR
;
784 struct flash_bank
*bank
;
785 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
786 if (ERROR_OK
!= retval
)
789 str7x_info
= bank
->driver_priv
;
791 target
= bank
->target
;
793 if (target
->state
!= TARGET_HALTED
)
795 LOG_ERROR("Target not halted");
796 return ERROR_TARGET_NOT_HALTED
;
799 /* first we get protection status */
801 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR0
), ®
);
803 if (!(reg
& str7x_info
->disable_bit
))
808 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR1
), ®
);
809 ProtectionRegs
= ~(reg
>> 16);
811 while (((ProtectionRegs
) != 0) && (ProtectionLevel
< 16))
813 ProtectionRegs
>>= 1;
817 if (ProtectionLevel
== 0)
819 flash_cmd
= FLASH_SPR
;
820 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
821 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFB8);
822 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), 0xFFFFFFFD);
823 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
824 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
828 flash_cmd
= FLASH_SPR
;
829 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
830 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFBC);
831 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
832 ~(1 << (15 + ProtectionLevel
)));
833 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
834 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
840 static const struct command_registration str7x_exec_command_handlers
[] = {
842 .name
= "disable_jtag",
844 .handler
= str7x_handle_disable_jtag_command
,
845 .mode
= COMMAND_EXEC
,
846 .help
= "disable jtag access",
848 COMMAND_REGISTRATION_DONE
851 static const struct command_registration str7x_command_handlers
[] = {
855 .help
= "str7x flash command group",
857 .chain
= str7x_exec_command_handlers
,
859 COMMAND_REGISTRATION_DONE
862 struct flash_driver str7x_flash
= {
864 .commands
= str7x_command_handlers
,
865 .flash_bank_command
= str7x_flash_bank_command
,
866 .erase
= str7x_erase
,
867 .protect
= str7x_protect
,
868 .write
= str7x_write
,
869 .read
= default_flash_read
,
870 .probe
= str7x_probe
,
871 .auto_probe
= str7x_probe
,
872 .erase_check
= default_flash_blank_check
,
873 .protect_check
= str7x_protect_check
,
874 .info
= get_str7x_info
,