1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
32 #define MB (1024*1024)
33 #define ERASE_REGION(num, size) (((size/256) << 16) | (num-1))
35 /* non-CFI compatible flashes */
36 static struct non_cfi non_cfi_flashes
[] = {
42 .interface_desc
= 0x0, /* x8 only device */
43 .max_buf_write_size
= 0x0,
44 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
45 .num_erase_regions
= 1,
48 ERASE_REGION(16, 4*KB
)
56 .interface_desc
= 0x0, /* x8 only device */
57 .max_buf_write_size
= 0x0,
58 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
59 .num_erase_regions
= 1,
62 ERASE_REGION(32, 4*KB
)
70 .interface_desc
= 0x0, /* x8 only device */
71 .max_buf_write_size
= 0x0,
72 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
73 .num_erase_regions
= 1,
76 ERASE_REGION(64, 4*KB
)
84 .interface_desc
= 0x0, /* x8 only device */
85 .max_buf_write_size
= 0x0,
86 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
87 .num_erase_regions
= 1,
90 ERASE_REGION(128, 4*KB
)
94 .mfr
= CFI_MFR_AMD
, /* Spansion AM29LV040B */
98 .interface_desc
= 0x0, /* x8 only device */
99 .max_buf_write_size
= 0x0,
100 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
101 .num_erase_regions
= 1,
104 ERASE_REGION(8, 64*KB
)
112 .interface_desc
= 0x2, /* x8 or x16 device */
113 .max_buf_write_size
= 0x0,
114 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
115 .num_erase_regions
= 1,
118 ERASE_REGION(128, 4*KB
)
123 .id
= 0xd6, /* ST29F400BB */
126 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
127 .max_buf_write_size
= 0x0,
128 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
129 .num_erase_regions
= 4,
132 ERASE_REGION(1, 16*KB
),
133 ERASE_REGION(2, 8*KB
),
134 ERASE_REGION(1, 32*KB
),
135 ERASE_REGION(7, 64*KB
)
140 .id
= 0xd5, /* ST29F400BT */
143 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
144 .max_buf_write_size
= 0x0,
145 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
146 .num_erase_regions
= 4,
149 ERASE_REGION(7, 64*KB
),
150 ERASE_REGION(1, 32*KB
),
151 ERASE_REGION(2, 8*KB
),
152 ERASE_REGION(1, 16*KB
)
156 /* SST 39VF* do not support DQ5 status polling - this currently is
157 only supported by the host algorithm, not by the target code using
159 Only true for 8-bit and 32-bit wide memories. 16-bit wide memories
160 without DQ5 status polling are supported by the target code.
164 .id
= 0x2782, /* SST39xF160 */
167 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
168 .max_buf_write_size
= 0x0,
169 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
170 .num_erase_regions
= 1,
173 ERASE_REGION(512, 4*KB
)
178 .id
= 0x2783, /* SST39VF320 */
181 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
182 .max_buf_write_size
= 0x0,
183 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
184 .num_erase_regions
= 1,
187 ERASE_REGION(1024, 4*KB
)
192 .id
= 0x234b, /* SST39VF1601 */
195 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
196 .max_buf_write_size
= 0x0,
197 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
198 .num_erase_regions
= 1,
201 ERASE_REGION(512, 4*KB
)
206 .id
= 0x234a, /* SST39VF1602 */
209 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
210 .max_buf_write_size
= 0x0,
211 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
212 .num_erase_regions
= 1,
215 ERASE_REGION(512, 4*KB
)
220 .id
= 0x235b, /* SST39VF3201 */
223 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
224 .max_buf_write_size
= 0x0,
225 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
226 .num_erase_regions
= 1,
229 ERASE_REGION(1024, 4*KB
)
234 .id
= 0x235a, /* SST39VF3202 */
237 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
238 .max_buf_write_size
= 0x0,
239 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
240 .num_erase_regions
= 1,
243 ERASE_REGION(1024, 4*KB
)
248 .id
= 0x236d, /* SST39VF6401B */
251 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
252 .max_buf_write_size
= 0x0,
253 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ6_DQ7
,
254 .num_erase_regions
= 1,
257 ERASE_REGION(2048, 4*KB
)
262 .id
= 0x22ab, /* AM29F400BB */
265 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
266 .max_buf_write_size
= 0x0,
267 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
268 .num_erase_regions
= 4,
271 ERASE_REGION(1, 16*KB
),
272 ERASE_REGION(2, 8*KB
),
273 ERASE_REGION(1, 32*KB
),
274 ERASE_REGION(7, 64*KB
)
279 .id
= 0x2223, /* AM29F400BT */
282 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
283 .max_buf_write_size
= 0x0,
284 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
285 .num_erase_regions
= 4,
288 ERASE_REGION(7, 64*KB
),
289 ERASE_REGION(1, 32*KB
),
290 ERASE_REGION(2, 8*KB
),
291 ERASE_REGION(1, 16*KB
)
295 .mfr
= CFI_MFR_FUJITSU
,
296 .id
= 0x226b, /* AM29SL800DB */
299 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
300 .max_buf_write_size
= 0x0,
301 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
302 .num_erase_regions
= 4,
305 ERASE_REGION(1, 16*KB
),
306 ERASE_REGION(2, 8*KB
),
307 ERASE_REGION(1, 32*KB
),
308 ERASE_REGION(15, 64*KB
)
312 .mfr
= CFI_MFR_FUJITSU
,
313 .id
= 0x22ea, /* MBM29SL800TE */
316 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
317 .max_buf_write_size
= 0x0,
318 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
319 .num_erase_regions
= 4,
322 ERASE_REGION(15, 64*KB
),
323 ERASE_REGION(1, 32*KB
),
324 ERASE_REGION(2, 8*KB
),
325 ERASE_REGION(1, 16*KB
)
329 .mfr
= CFI_MFR_FUJITSU
,
330 .id
= 0xba, /* 29LV400BC */
333 .interface_desc
= 0x1, /* x8 or x16 device w/ nBYTE */
334 .max_buf_write_size
= 0x00,
335 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
336 .num_erase_regions
= 4,
339 ERASE_REGION(1, 16*KB
),
340 ERASE_REGION(2, 8*KB
),
341 ERASE_REGION(1, 32*KB
),
342 ERASE_REGION(7, 64*KB
)
347 .id
= 0xb31a, /* A29L800A */
350 .interface_desc
= 0x2,
351 .max_buf_write_size
= 0x0,
352 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
353 .num_erase_regions
= 4,
356 ERASE_REGION(1, 16*KB
),
357 ERASE_REGION(2, 8*KB
),
358 ERASE_REGION(1, 32*KB
),
359 ERASE_REGION(15, 64*KB
)
364 .id
= 0x225b, /* MX29LV800B */
367 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
368 .max_buf_write_size
= 0x0,
369 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
370 .num_erase_regions
= 4,
373 ERASE_REGION(1, 16*KB
),
374 ERASE_REGION(2, 8*KB
),
375 ERASE_REGION(1, 32*KB
),
376 ERASE_REGION(15, 64*KB
)
382 .id
= 0x2249, /* MX29LV160AB: 2MB */
385 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
386 .max_buf_write_size
= 0x0,
387 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
388 .num_erase_regions
= 4,
391 ERASE_REGION(1, 16*KB
),
392 ERASE_REGION(2, 8*KB
),
393 ERASE_REGION(1, 32*KB
),
394 ERASE_REGION(31, 64*KB
)
399 .id
= 0x22C4, /* MX29LV160AT: 2MB */
402 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
403 .max_buf_write_size
= 0x0,
404 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
405 .num_erase_regions
= 4,
408 ERASE_REGION(31, 64*KB
),
409 ERASE_REGION(1, 32*KB
),
410 ERASE_REGION(2, 8*KB
),
411 ERASE_REGION(1, 16*KB
)
416 .id
= 0x225b, /* EN29LV800BB */
419 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
420 .max_buf_write_size
= 0x0,
421 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
422 .num_erase_regions
= 4,
425 ERASE_REGION(1, 16*KB
),
426 ERASE_REGION(2, 8*KB
),
427 ERASE_REGION(1, 32*KB
),
428 ERASE_REGION(15, 64*KB
)
432 .mfr
= CFI_MFR_ATMEL
,
433 .id
= 0x00c0, /* Atmel 49BV1614 */
436 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
437 .max_buf_write_size
= 0x0,
438 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
439 .num_erase_regions
= 3,
442 ERASE_REGION(8, 8*KB
),
443 ERASE_REGION(2, 32*KB
),
444 ERASE_REGION(30, 64*KB
)
448 .mfr
= CFI_MFR_ATMEL
,
449 .id
= 0xC2, /* Atmel 49BV1614T */
452 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
453 .max_buf_write_size
= 0x0,
454 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
455 .num_erase_regions
= 3,
458 ERASE_REGION(30, 64*KB
),
459 ERASE_REGION(2, 32*KB
),
460 ERASE_REGION(8, 8*KB
)
465 .id
= 0x225b, /* S29AL008D */
468 .interface_desc
= 0x2, /* x8 or x16 device with nBYTE */
469 .max_buf_write_size
= 0x0,
470 .status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
,
471 .num_erase_regions
= 4,
474 ERASE_REGION(1, 16*KB
),
475 ERASE_REGION(2, 8*KB
),
476 ERASE_REGION(1, 32*KB
),
477 ERASE_REGION(15, 64*KB
)
486 void cfi_fixup_non_cfi(struct flash_bank
*bank
)
489 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
490 struct non_cfi
*non_cfi
= non_cfi_flashes
;
492 if(cfi_info
->x16_as_x8
)
497 for (non_cfi
= non_cfi_flashes
; non_cfi
->mfr
; non_cfi
++)
499 if ((cfi_info
->manufacturer
== non_cfi
->mfr
)
500 && (cfi_info
->device_id
== (non_cfi
->id
& mask
)))
506 /* only fixup jedec flashs found in table */
510 cfi_info
->not_cfi
= 1;
512 /* fill in defaults for non-critical data */
513 cfi_info
->vcc_min
= 0x0;
514 cfi_info
->vcc_max
= 0x0;
515 cfi_info
->vpp_min
= 0x0;
516 cfi_info
->vpp_max
= 0x0;
517 /* these are used for timeouts - use vales that should be long enough
518 for normal operation. */
519 cfi_info
->word_write_timeout_typ
= 0x0a;
520 cfi_info
->buf_write_timeout_typ
= 0x0d;
521 cfi_info
->block_erase_timeout_typ
= 0x0d;
522 cfi_info
->chip_erase_timeout_typ
= 0x10;
523 cfi_info
->word_write_timeout_max
= 0x0;
524 cfi_info
->buf_write_timeout_max
= 0x0;
525 cfi_info
->block_erase_timeout_max
= 0x0;
526 cfi_info
->chip_erase_timeout_max
= 0x0;
528 cfi_info
->qry
[0] = 'Q';
529 cfi_info
->qry
[1] = 'R';
530 cfi_info
->qry
[2] = 'Y';
532 cfi_info
->pri_id
= non_cfi
->pri_id
;
533 cfi_info
->pri_addr
= 0x0;
534 cfi_info
->alt_id
= 0x0;
535 cfi_info
->alt_addr
= 0x0;
536 cfi_info
->alt_ext
= NULL
;
538 cfi_info
->interface_desc
= non_cfi
->interface_desc
;
539 cfi_info
->max_buf_write_size
= non_cfi
->max_buf_write_size
;
540 cfi_info
->status_poll_mask
= non_cfi
->status_poll_mask
;
541 cfi_info
->num_erase_regions
= non_cfi
->num_erase_regions
;
542 size_t erase_region_info_size
= sizeof(*cfi_info
->erase_region_info
) *
543 cfi_info
->num_erase_regions
;
544 cfi_info
->erase_region_info
= malloc(erase_region_info_size
);
545 memcpy(cfi_info
->erase_region_info
,
546 non_cfi
->erase_region_info
, erase_region_info_size
);
547 cfi_info
->dev_size
= non_cfi
->dev_size
;
549 if (cfi_info
->pri_id
== 0x2)
551 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
553 pri_ext
->pri
[0] = 'P';
554 pri_ext
->pri
[1] = 'R';
555 pri_ext
->pri
[2] = 'I';
557 pri_ext
->major_version
= '1';
558 pri_ext
->minor_version
= '0';
560 pri_ext
->SiliconRevision
= 0x0;
561 pri_ext
->EraseSuspend
= 0x0;
562 pri_ext
->EraseSuspend
= 0x0;
563 pri_ext
->BlkProt
= 0x0;
564 pri_ext
->TmpBlkUnprotect
= 0x0;
565 pri_ext
->BlkProtUnprot
= 0x0;
566 pri_ext
->SimultaneousOps
= 0x0;
567 pri_ext
->BurstMode
= 0x0;
568 pri_ext
->PageMode
= 0x0;
569 pri_ext
->VppMin
= 0x0;
570 pri_ext
->VppMax
= 0x0;
571 pri_ext
->TopBottom
= 0x0;
573 pri_ext
->_unlock1
= 0x5555;
574 pri_ext
->_unlock2
= 0x2AAA;
575 pri_ext
->_reversed_geometry
= 0;
577 cfi_info
->pri_ext
= pri_ext
;
578 } else if ((cfi_info
->pri_id
== 0x1) || (cfi_info
->pri_id
== 0x3))
580 LOG_ERROR("BUG: non-CFI flashes using the Intel commandset are not yet supported");