?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
NAND/davinci: Fix segfault for hwecc4_infix reads
[openocd/genbsdl.git] / src / flash / nand / davinci.c
blob90219c691cb9afd54b9eef35913bbd975adee3ba
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /*
21 * DaVinci family NAND controller support for OpenOCD.
22 *
23 * This driver uses hardware ECC (1-bit or 4-bit) unless
24 * the chip is accessed in "raw" mode.
25 */
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include "arm_io.h"
33 #include <target/target.h>
34
35 enum ecc {
36 HWECC1, /* all controllers support 1-bit ECC */
37 HWECC4, /* newer chips also have 4-bit ECC hardware */
38 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
39 };
40
41 struct davinci_nand {
42 struct target *target;
43
44 uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
45 uint8_t eccmode;
46
47 /* Async EMIF controller base */
48 uint32_t aemif;
49
50 /* NAND chip addresses */
51 uint32_t data; /* without CLE or ALE */
52 uint32_t cmd; /* with CLE */
53 uint32_t addr; /* with ALE */
54
55 /* write acceleration */
56 struct arm_nand_data io;
57
58 /* page i/o for the relevant flavor of hardware ECC */
59 int (*read_page)(struct nand_device *nand, uint32_t page,
60 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
61 int (*write_page)(struct nand_device *nand, uint32_t page,
62 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
63 };
64
65 #define NANDFCR 0x60 /* flash control register */
66 #define NANDFSR 0x64 /* flash status register */
67 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
68 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
69 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
70 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
71 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
72
73 static int halted(struct target *target, const char *label)
74 {
75 if (target->state == TARGET_HALTED)
76 return true;
77
78 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
79 return false;
80 }
81
82 static int davinci_init(struct nand_device *nand)
83 {
84 struct davinci_nand *info = nand->controller_priv;
85 struct target *target = info->target;
86 uint32_t nandfcr;
87
88 if (!halted(target, "init"))
89 return ERROR_NAND_OPERATION_FAILED;
90
91 /* We require something else to have configured AEMIF to talk
92 * to NAND chip in this range (including timings and width).
93 */
94 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
95 if (!(nandfcr & (1 << info->chipsel))) {
96 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
97 return ERROR_NAND_OPERATION_FAILED;
98 }
99
100 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
101 * tested. 16 bit support should work too; but not with 4-bit ECC.
102 */
103
104 return ERROR_OK;
105 }
106
107 static int davinci_reset(struct nand_device *nand)
108 {
109 return ERROR_OK;
110 }
111
112 static int davinci_nand_ready(struct nand_device *nand, int timeout)
113 {
114 struct davinci_nand *info = nand->controller_priv;
115 struct target *target = info->target;
116 uint32_t nandfsr;
117
118 /* NOTE: return code is zero/error, else success; not ERROR_* */
119
120 if (!halted(target, "ready"))
121 return 0;
122
123 do {
124 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
125
126 if (nandfsr & 0x01)
127 return 1;
128
129 alive_sleep(1);
130 } while (timeout-- > 0);
131
132 return 0;
133 }
134
135 static int davinci_command(struct nand_device *nand, uint8_t command)
136 {
137 struct davinci_nand *info = nand->controller_priv;
138 struct target *target = info->target;
139
140 if (!halted(target, "command"))
141 return ERROR_NAND_OPERATION_FAILED;
142
143 target_write_u8(target, info->cmd, command);
144 return ERROR_OK;
145 }
146
147 static int davinci_address(struct nand_device *nand, uint8_t address)
148 {
149 struct davinci_nand *info = nand->controller_priv;
150 struct target *target = info->target;
151
152 if (!halted(target, "address"))
153 return ERROR_NAND_OPERATION_FAILED;
154
155 target_write_u8(target, info->addr, address);
156 return ERROR_OK;
157 }
158
159 static int davinci_write_data(struct nand_device *nand, uint16_t data)
160 {
161 struct davinci_nand *info = nand->controller_priv;
162 struct target *target = info->target;
163
164 if (!halted(target, "write_data"))
165 return ERROR_NAND_OPERATION_FAILED;
166
167 target_write_u8(target, info->data, data);
168 return ERROR_OK;
169 }
170
171 static int davinci_read_data(struct nand_device *nand, void *data)
172 {
173 struct davinci_nand *info = nand->controller_priv;
174 struct target *target = info->target;
175
176 if (!halted(target, "read_data"))
177 return ERROR_NAND_OPERATION_FAILED;
178
179 target_read_u8(target, info->data, data);
180 return ERROR_OK;
181 }
182
183 /* REVISIT a bit of native code should let block reads be MUCH faster */
184
185 static int davinci_read_block_data(struct nand_device *nand,
186 uint8_t *data, int data_size)
187 {
188 struct davinci_nand *info = nand->controller_priv;
189 struct target *target = info->target;
190 uint32_t nfdata = info->data;
191 uint32_t tmp;
192
193 if (!halted(target, "read_block"))
194 return ERROR_NAND_OPERATION_FAILED;
195
196 while (data_size >= 4) {
197 target_read_u32(target, nfdata, &tmp);
198
199 data[0] = tmp;
200 data[1] = tmp >> 8;
201 data[2] = tmp >> 16;
202 data[3] = tmp >> 24;
203
204 data_size -= 4;
205 data += 4;
206 }
207
208 while (data_size > 0) {
209 target_read_u8(target, nfdata, data);
210
211 data_size -= 1;
212 data += 1;
213 }
214
215 return ERROR_OK;
216 }
217
218 static int davinci_write_block_data(struct nand_device *nand,
219 uint8_t *data, int data_size)
220 {
221 struct davinci_nand *info = nand->controller_priv;
222 struct target *target = info->target;
223 uint32_t nfdata = info->data;
224 uint32_t tmp;
225 int status;
226
227 if (!halted(target, "write_block"))
228 return ERROR_NAND_OPERATION_FAILED;
229
230 /* try the fast way first */
231 status = arm_nandwrite(&info->io, data, data_size);
232 if (status != ERROR_NAND_NO_BUFFER)
233 return status;
234
235 /* else do it slowly */
236 while (data_size >= 4) {
237 tmp = le_to_h_u32(data);
238 target_write_u32(target, nfdata, tmp);
239
240 data_size -= 4;
241 data += 4;
242 }
243
244 while (data_size > 0) {
245 target_write_u8(target, nfdata, *data);
246
247 data_size -= 1;
248 data += 1;
249 }
250
251 return ERROR_OK;
252 }
253
254 static int davinci_write_page(struct nand_device *nand, uint32_t page,
255 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
256 {
257 struct davinci_nand *info = nand->controller_priv;
258 uint8_t *ooballoc = NULL;
259 int status;
260
261 if (!nand->device)
262 return ERROR_NAND_DEVICE_NOT_PROBED;
263 if (!halted(info->target, "write_page"))
264 return ERROR_NAND_OPERATION_FAILED;
265
266 /* Always write both data and OOB ... we are not "raw" I/O! */
267 if (!data) {
268 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
269 return ERROR_NAND_OPERATION_FAILED;
270 }
271
272 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
273 switch (nand->page_size) {
274 case 512:
275 oob_size = 16;
276 break;
277 case 2048:
278 oob_size = 64;
279 break;
280 case 4096:
281 oob_size = 128;
282 break;
283 default:
284 return ERROR_NAND_OPERATION_FAILED;
285 }
286 if (!oob) {
287 ooballoc = malloc(oob_size);
288 if (!ooballoc)
289 return ERROR_NAND_OPERATION_FAILED;
290 oob = ooballoc;
291 memset(oob, 0x0ff, oob_size);
292 }
293
294 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
295 * use 512 byte chunks. Read side support will often want
296 * to include oob_size ...
297 */
298 info->io.chunk_size = nand->page_size;
299
300 status = info->write_page(nand, page, data, data_size, oob, oob_size);
301 free(ooballoc);
302 return status;
303 }
304
305 static int davinci_read_page(struct nand_device *nand, uint32_t page,
306 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
307 {
308 struct davinci_nand *info = nand->controller_priv;
309
310 if (!nand->device)
311 return ERROR_NAND_DEVICE_NOT_PROBED;
312 if (!halted(info->target, "read_page"))
313 return ERROR_NAND_OPERATION_FAILED;
314
315 return info->read_page(nand, page, data, data_size, oob, oob_size);
316 }
317
318 static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
319 {
320 struct davinci_nand *info = nand->controller_priv;
321 struct target *target = info->target;
322 int page3 = nand->address_cycles - (nand->page_size == 512);
323
324 /* write command ({page,otp}x{read,program} */
325 target_write_u8(target, info->cmd, cmd);
326
327 /* column address (beginning-of-page) */
328 target_write_u8(target, info->addr, 0);
329 if (nand->page_size > 512)
330 target_write_u8(target, info->addr, 0);
331
332 /* page address */
333 target_write_u8(target, info->addr, page);
334 target_write_u8(target, info->addr, page >> 8);
335 if (page3)
336 target_write_u8(target, info->addr, page >> 16);
337 if (page3 == 2)
338 target_write_u8(target, info->addr, page >> 24);
339 }
340
341 static int davinci_seek_column(struct nand_device *nand, uint16_t column)
342 {
343 struct davinci_nand *info = nand->controller_priv;
344 struct target *target = info->target;
345
346 /* Random read, we must have issued a page read already */
347 target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
348
349 target_write_u8(target, info->addr, column);
350
351 if (nand->page_size > 512) {
352 target_write_u8(target, info->addr, column >> 8);
353 target_write_u8(target, info->cmd, NAND_CMD_RNDOUTSTART);
354 }
355
356 if (!davinci_nand_ready(nand, 100))
357 return ERROR_NAND_OPERATION_TIMEOUT;
358
359 return ERROR_OK;
360 }
361
362 static int davinci_writepage_tail(struct nand_device *nand,
363 uint8_t *oob, uint32_t oob_size)
364 {
365 struct davinci_nand *info = nand->controller_priv;
366 struct target *target = info->target;
367 uint8_t status;
368
369 if (oob_size)
370 davinci_write_block_data(nand, oob, oob_size);
371
372 /* non-cachemode page program */
373 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
374
375 if (!davinci_nand_ready(nand, 100))
376 return ERROR_NAND_OPERATION_TIMEOUT;
377
378 if (nand_read_status(nand, &status) != ERROR_OK) {
379 LOG_ERROR("couldn't read status");
380 return ERROR_NAND_OPERATION_FAILED;
381 }
382
383 if (status & NAND_STATUS_FAIL) {
384 LOG_ERROR("write operation failed, status: 0x%02x", status);
385 return ERROR_NAND_OPERATION_FAILED;
386 }
387
388 return ERROR_OK;
389 }
390
391 /*
392 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
393 */
394 static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
395 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
396 {
397 unsigned oob_offset;
398 struct davinci_nand *info = nand->controller_priv;
399 struct target *target = info->target;
400 const uint32_t fcr_addr = info->aemif + NANDFCR;
401 const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
402 uint32_t fcr, ecc1;
403
404 /* Write contiguous ECC bytes starting at specified offset.
405 * NOTE: Linux reserves twice as many bytes as we need; and
406 * for 16-bit OOB, those extra bytes are discontiguous.
407 */
408 switch (nand->page_size) {
409 case 512:
410 oob_offset = 0;
411 break;
412 case 2048:
413 oob_offset = 40;
414 break;
415 default:
416 oob_offset = 80;
417 break;
418 }
419
420 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
421
422 /* scrub any old ECC state */
423 target_read_u32(target, ecc1_addr, &ecc1);
424
425 target_read_u32(target, fcr_addr, &fcr);
426 fcr |= 1 << (8 + info->chipsel);
427
428 do {
429 /* set "start csX 1bit ecc" bit */
430 target_write_u32(target, fcr_addr, fcr);
431
432 /* write 512 bytes */
433 davinci_write_block_data(nand, data, 512);
434 data += 512;
435 data_size -= 512;
436
437 /* read the ecc, pack to 3 bytes, and invert so the ecc
438 * in an erased block is correct
439 */
440 target_read_u32(target, ecc1_addr, &ecc1);
441 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
442 ecc1 = ~ecc1;
443
444 /* save correct ECC code into oob data */
445 oob[oob_offset++] = (uint8_t)(ecc1);
446 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
447 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
448
449 } while (data_size);
450
451 /* write OOB into spare area */
452 return davinci_writepage_tail(nand, oob, oob_size);
453 }
454
455 /*
456 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
457 * slows down large page reads done with error correction (since the OOB
458 * is read first, so its ECC data can be used incrementally), but the
459 * manufacturer bad block markers are safe. Contrast: old "infix" style.
460 */
461 static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
462 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
463 {
464 static const uint8_t ecc512[] = {
465 0, 1, 2, 3, 4, /* 5== mfr badblock */
466 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
467 };
468 static const uint8_t ecc2048[] = {
469 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
470 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
471 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
472 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
473 };
474 static const uint8_t ecc4096[] = {
475 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
476 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
477 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
478 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
479 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
480 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
481 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
482 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
483 };
484
485 struct davinci_nand *info = nand->controller_priv;
486 const uint8_t *l;
487 struct target *target = info->target;
488 const uint32_t fcr_addr = info->aemif + NANDFCR;
489 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
490 uint32_t fcr, ecc4;
491
492 /* Use the same ECC layout Linux uses. For small page chips
493 * it's a bit cramped.
494 *
495 * NOTE: at this writing, 4KB pages have issues in Linux
496 * because they need more than 64 bytes of ECC data, which
497 * the standard ECC logic can't handle.
498 */
499 switch (nand->page_size) {
500 case 512:
501 l = ecc512;
502 break;
503 case 2048:
504 l = ecc2048;
505 break;
506 default:
507 l = ecc4096;
508 break;
509 }
510
511 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
512
513 /* scrub any old ECC state */
514 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
515
516 target_read_u32(target, fcr_addr, &fcr);
517 fcr &= ~(0x03 << 4);
518 fcr |= (1 << 12) | (info->chipsel << 4);
519
520 do {
521 uint32_t raw_ecc[4], *p;
522 int i;
523
524 /* start 4bit ecc on csX */
525 target_write_u32(target, fcr_addr, fcr);
526
527 /* write 512 bytes */
528 davinci_write_block_data(nand, data, 512);
529 data += 512;
530 data_size -= 512;
531
532 /* read the ecc, then save it into 10 bytes in the oob */
533 for (i = 0; i < 4; i++) {
534 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
535 raw_ecc[i] &= 0x03ff03ff;
536 }
537 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
538 oob[*l++] = p[0] & 0xff;
539 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
540 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
541 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
542 oob[*l++] = (p[1] >> 18) & 0xff;
543 }
544
545 } while (data_size);
546
547 /* write OOB into spare area */
548 return davinci_writepage_tail(nand, oob, oob_size);
549 }
550
551 /*
552 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
553 * manufacturer bad block markers, except on small page chips. Once you
554 * write to a page using this scheme, you need specialized code to update
555 * it (code which ignores now-invalid bad block markers).
556 *
557 * This is needed *only* to support older firmware. Older ROM Boot Loaders
558 * need it to read their second stage loader (UBL) into SRAM, but from then
559 * on the whole system can use the cleaner non-infix layouts. Systems with
560 * older second stage loaders (ABL/U-Boot, etc) or other system software
561 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
562 */
563 static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
564 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
565 {
566 struct davinci_nand *info = nand->controller_priv;
567 struct target *target = info->target;
568 const uint32_t fcr_addr = info->aemif + NANDFCR;
569 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
570 uint32_t fcr, ecc4;
571
572 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
573
574 /* scrub any old ECC state */
575 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
576
577 target_read_u32(target, fcr_addr, &fcr);
578 fcr &= ~(0x03 << 4);
579 fcr |= (1 << 12) | (info->chipsel << 4);
580
581 do {
582 uint32_t raw_ecc[4], *p;
583 uint8_t *l;
584 int i;
585
586 /* start 4bit ecc on csX */
587 target_write_u32(target, fcr_addr, fcr);
588
589 /* write 512 bytes */
590 davinci_write_block_data(nand, data, 512);
591 data += 512;
592 data_size -= 512;
593
594 /* read the ecc */
595 for (i = 0; i < 4; i++) {
596 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
597 raw_ecc[i] &= 0x03ff03ff;
598 }
599
600 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
601 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
602 *l++ = p[0] & 0xff;
603 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
604 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
605 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
606 *l++ = (p[1] >> 18) & 0xff;
607 }
608
609 /* write this "out-of-band" data -- infix */
610 davinci_write_block_data(nand, oob, 16);
611 oob += 16;
612 oob_size -= 16;
613
614 } while (data_size);
615
616 /* the last data and OOB writes included the spare area */
617 return davinci_writepage_tail(nand, NULL, 0);
618 }
619
620 static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
621 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
622 {
623 int read_size;
624 int want_col, at_col;
625 int ret;
626
627 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
628
629 /* large page devices need a start command */
630 if (nand->page_size > 512)
631 davinci_command(nand, NAND_CMD_READSTART);
632
633 if (!davinci_nand_ready(nand, 100))
634 return ERROR_NAND_OPERATION_TIMEOUT;
635
636 /* NOTE: not bothering to compute and use ECC data for now */
637
638 want_col = 0;
639 at_col = 0;
640 while ((data && data_size) || (oob && oob_size)) {
641
642 if (data && data_size) {
643 if (want_col != at_col) {
644 /* Reads are slow, so seek past them when we can */
645 ret = davinci_seek_column(nand, want_col);
646 if (ret != ERROR_OK)
647 return ret;
648 at_col = want_col;
649 }
650 /* read 512 bytes or data_size, whichever is smaller*/
651 read_size = data_size > 512 ? 512 : data_size;
652 davinci_read_block_data(nand, data, read_size);
653 data += read_size;
654 data_size -= read_size;
655 at_col += read_size;
656 }
657 want_col += 512;
658
659 if (oob && oob_size) {
660 if (want_col != at_col) {
661 ret = davinci_seek_column(nand, want_col);
662 if (ret != ERROR_OK)
663 return ret;
664 at_col = want_col;
665 }
666 /* read this "out-of-band" data -- infix */
667 read_size = oob_size > 16 ? 16 : oob_size;
668 davinci_read_block_data(nand, oob, read_size);
669 oob += read_size;
670 oob_size -= read_size;
671 at_col += read_size;
672 }
673 want_col += 16;
674 }
675 return ERROR_OK;
676 }
677
678 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
679 {
680 struct davinci_nand *info;
681 struct target *target;
682 unsigned long chip, aemif;
683 enum ecc eccmode;
684 int chipsel;
685
686 /* arguments:
687 * - "davinci"
688 * - target
689 * - nand chip address
690 * - ecc mode
691 * - aemif address
692 * Plus someday, optionally, ALE and CLE masks.
693 */
694 if (CMD_ARGC < 5) {
695 LOG_ERROR("parameters: %s target "
696 "chip_addr hwecc_mode aemif_addr",
697 CMD_ARGV[0]);
698 goto fail;
699 }
700
701 target = get_target(CMD_ARGV[1]);
702 if (!target) {
703 LOG_ERROR("invalid target %s", CMD_ARGV[1]);
704 goto fail;
705 }
706
707 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
708 if (chip == 0) {
709 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
710 goto fail;
711 }
712
713 if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
714 eccmode = HWECC1;
715 else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
716 eccmode = HWECC4;
717 else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
718 eccmode = HWECC4_INFIX;
719 else {
720 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
721 goto fail;
722 }
723
724 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
725 if (aemif == 0) {
726 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
727 goto fail;
728 }
729
730 /* REVISIT what we'd *like* to do is look up valid ranges using
731 * target-specific declarations, and not even need to pass the
732 * AEMIF controller address.
733 */
734 if (aemif == 0x01e00000 /* dm6446, dm357 */
735 || aemif == 0x01e10000 /* dm335, dm355 */
736 || aemif == 0x01d10000 /* dm365 */
737 ) {
738 if (chip < 0x02000000 || chip >= 0x0a000000) {
739 LOG_ERROR("NAND address %08lx out of range?", chip);
740 goto fail;
741 }
742 chipsel = (chip - 0x02000000) >> 25;
743 } else {
744 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
745 goto fail;
746 }
747
748 info = calloc(1, sizeof *info);
749 if (info == NULL)
750 goto fail;
751
752 info->target = target;
753 info->eccmode = eccmode;
754 info->chipsel = chipsel;
755 info->aemif = aemif;
756 info->data = chip;
757 info->cmd = chip | 0x10;
758 info->addr = chip | 0x08;
759
760 nand->controller_priv = info;
761
762 info->io.target = target;
763 info->io.data = info->data;
764 info->io.op = ARM_NAND_NONE;
765
766 /* NOTE: for now we don't do any error correction on read.
767 * Nothing else in OpenOCD currently corrects read errors,
768 * and in any case it's *writing* that we care most about.
769 */
770 info->read_page = nand_read_page_raw;
771
772 switch (eccmode) {
773 case HWECC1:
774 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
775 info->write_page = davinci_write_page_ecc1;
776 break;
777 case HWECC4:
778 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
779 info->write_page = davinci_write_page_ecc4;
780 break;
781 case HWECC4_INFIX:
782 /* Same 4-bit ECC HW, with problematic page/ecc layout */
783 info->read_page = davinci_read_page_ecc4infix;
784 info->write_page = davinci_write_page_ecc4infix;
785 break;
786 }
787
788 return ERROR_OK;
789
790 fail:
791 return ERROR_NAND_OPERATION_FAILED;
792 }
793
794 struct nand_flash_controller davinci_nand_controller = {
795 .name = "davinci",
796 .nand_device_command = davinci_nand_device_command,
797 .init = davinci_init,
798 .reset = davinci_reset,
799 .command = davinci_command,
800 .address = davinci_address,
801 .write_data = davinci_write_data,
802 .read_data = davinci_read_data,
803 .write_page = davinci_write_page,
804 .read_page = davinci_read_page,
805 .write_block_data = davinci_write_block_data,
806 .read_block_data = davinci_read_block_data,
807 .nand_ready = davinci_nand_ready,
808 };
Generic flash access through boundary scans