1 /***************************************************************************
2 * Copyright (C) 2009 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include <helper/jim.h>
27 #include "target_type.h"
30 #include "dsp563xx_once.h"
32 #define DSP563XX_JTAG_INS_LEN 4
34 #define JTAG_STATUS_NORMAL 0x01
35 #define JTAG_STATUS_STOPWAIT 0x05
36 #define JTAG_STATUS_BUSY 0x09
37 #define JTAG_STATUS_DEBUG 0x0d
39 #define JTAG_INSTR_EXTEST 0x00
40 #define JTAG_INSTR_SAMPLE_PRELOAD 0x01
41 #define JTAG_INSTR_IDCODE 0x02
42 #define JTAG_INSTR_CLAMP 0x03
43 #define JTAG_INSTR_HIZ 0x04
44 #define JTAG_INSTR_ENABLE_ONCE 0x06
45 #define JTAG_INSTR_DEBUG_REQUEST 0x07
46 #define JTAG_INSTR_BYPASS 0x0F
48 /* forward declarations */
49 int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
);
50 int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
);
52 int dsp563xx_arch_state(struct target
*target
);
53 int dsp563xx_poll(struct target
*target
);
54 int dsp563xx_halt(struct target
*target
);
55 int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
,
56 int handle_breakpoints
, int debug_execution
);
57 int dsp563xx_step(struct target
*target
, int current
, uint32_t address
,
58 int handle_breakpoints
);
60 int dsp563xx_assert_reset(struct target
*target
);
61 int dsp563xx_deassert_reset(struct target
*target
);
62 int dsp563xx_soft_reset_halt(struct target
*target
);
64 /* IR and DR functions */
65 int dsp563xx_jtag_sendinstr(struct jtag_tap
*tap
, uint8_t * ir_in
, uint8_t ir_out
);
66 int dsp563xx_jtag_senddat(struct jtag_tap
*tap
, uint32_t * dr_in
, uint32_t dr_out
,
69 int dsp563xx_read_memory_p(struct target
*target
, uint32_t address
, uint32_t size
,
70 uint32_t count
, uint8_t * buffer
);
71 int dsp563xx_write_memory_p(struct target
*target
, uint32_t address
, uint32_t size
,
72 uint32_t count
, uint8_t * buffer
);
74 #define ASM_REG_R_R0 0x607000
75 #define ASM_REG_R_R1 0x617000
76 #define ASM_REG_R_R2 0x627000
77 #define ASM_REG_R_R3 0x637000
78 #define ASM_REG_R_R4 0x647000
79 #define ASM_REG_R_R5 0x657000
80 #define ASM_REG_R_R6 0x667000
81 #define ASM_REG_R_R7 0x677000
83 #define ASM_REG_W_R0 0x60F400
84 #define ASM_REG_W_R1 0x61F400
85 #define ASM_REG_W_R2 0x62F400
86 #define ASM_REG_W_R3 0x63F400
87 #define ASM_REG_W_R4 0x64F400
88 #define ASM_REG_W_R5 0x65F400
89 #define ASM_REG_W_R6 0x66F400
90 #define ASM_REG_W_R7 0x67F400
92 #define ASM_REG_R_N0 0x707000
93 #define ASM_REG_R_N1 0x717000
94 #define ASM_REG_R_N2 0x727000
95 #define ASM_REG_R_N3 0x737000
96 #define ASM_REG_R_N4 0x747000
97 #define ASM_REG_R_N5 0x757000
98 #define ASM_REG_R_N6 0x767000
99 #define ASM_REG_R_N7 0x777000
101 #define ASM_REG_W_N0 0x70F400
102 #define ASM_REG_W_N1 0x71F400
103 #define ASM_REG_W_N2 0x72F400
104 #define ASM_REG_W_N3 0x73F400
105 #define ASM_REG_W_N4 0x74F400
106 #define ASM_REG_W_N5 0x75F400
107 #define ASM_REG_W_N6 0x76F400
108 #define ASM_REG_W_N7 0x77F400
110 #define ASM_REG_R_M0 0x057020 /* control register m[0..7] */
111 #define ASM_REG_R_M1 0x057021
112 #define ASM_REG_R_M2 0x057022
113 #define ASM_REG_R_M3 0x057023
114 #define ASM_REG_R_M4 0x057024
115 #define ASM_REG_R_M5 0x057025
116 #define ASM_REG_R_M6 0x057026
117 #define ASM_REG_R_M7 0x057027
119 #define ASM_REG_W_M0 0x05F420
120 #define ASM_REG_W_M1 0x05F421
121 #define ASM_REG_W_M2 0x05F422
122 #define ASM_REG_W_M3 0x05F423
123 #define ASM_REG_W_M4 0x05F424
124 #define ASM_REG_W_M5 0x05F425
125 #define ASM_REG_W_M6 0x05F426
126 #define ASM_REG_W_M7 0x05F427
128 #define ASM_REG_R_X0 0x447000
129 #define ASM_REG_R_X1 0x457000
131 #define ASM_REG_W_X0 0x44F400
132 #define ASM_REG_W_X1 0x45F400
134 #define ASM_REG_R_Y0 0x467000
135 #define ASM_REG_R_Y1 0x477000
137 #define ASM_REG_W_Y0 0x46F400
138 #define ASM_REG_W_Y1 0x47F400
140 #define ASM_REG_R_A0 0x507000
141 #define ASM_REG_R_A1 0x547000
142 #define ASM_REG_R_A2 0x527000
144 #define ASM_REG_W_A0 0x50F400
145 #define ASM_REG_W_A1 0x54F400
146 #define ASM_REG_W_A2 0x52F400
148 #define ASM_REG_R_B0 0x517000
149 #define ASM_REG_R_B1 0x557000
150 #define ASM_REG_R_B2 0x537000
152 #define ASM_REG_W_B0 0x51F400
153 #define ASM_REG_W_B1 0x55F400
154 #define ASM_REG_W_B2 0x53F400
156 #define ASM_REG_R_VBA 0x057030 /* control register */
157 #define ASM_REG_W_VBA 0x05F430
159 #define ASM_REG_R_OMR 0x05703A /* control register */
160 #define ASM_REG_W_OMR 0x05F43A
162 #define ASM_REG_R_EP 0x05702A
163 #define ASM_REG_W_EP 0x05F42A
165 #define ASM_REG_R_SC 0x057031 /* stack counter */
166 #define ASM_REG_W_SC 0x05F431
168 #define ASM_REG_R_SZ 0x057038 /* stack size */
169 #define ASM_REG_W_SZ 0x05F438
171 #define ASM_REG_R_SR 0x057039 /* control register, status register */
172 #define ASM_REG_W_SR 0x05F439
174 #define ASM_REG_R_SP 0x05703B /* control register, stack pointer */
175 #define ASM_REG_W_SP 0x05F43B
177 #define ASM_REG_R_SSH 0x05703C /* control register, system stack high */
178 #define ASM_REG_W_SSH 0x05743C
180 #define ASM_REG_R_SSL 0x05703D /* control register, system stack low */
181 #define ASM_REG_W_SSL 0x05F43D
183 #define ASM_REG_R_LA 0x05703E /* control register, loop address */
184 #define ASM_REG_W_LA 0x05F43E
186 #define ASM_REG_R_LC 0x05703F /* control register, loop count */
187 #define ASM_REG_W_LC 0x05F43F
189 #define ASM_REG_R_PC 0x000000
190 #define ASM_REG_W_PC 0x000000
202 {0, "r0", 24, ASM_REG_R_R0
, ASM_REG_W_R0
},
203 {1, "r1", 24, ASM_REG_R_R1
, ASM_REG_W_R1
},
204 {2, "r2", 24, ASM_REG_R_R2
, ASM_REG_W_R2
},
205 {3, "r3", 24, ASM_REG_R_R3
, ASM_REG_W_R3
},
206 {4, "r4", 24, ASM_REG_R_R4
, ASM_REG_W_R4
},
207 {5, "r5", 24, ASM_REG_R_R5
, ASM_REG_W_R5
},
208 {6, "r6", 24, ASM_REG_R_R6
, ASM_REG_W_R6
},
209 {7, "r7", 24, ASM_REG_R_R7
, ASM_REG_W_R7
},
210 {8, "n0", 24, ASM_REG_R_N0
, ASM_REG_W_N0
},
211 {9, "n1", 24, ASM_REG_R_N1
, ASM_REG_W_N1
},
212 {10, "n2", 24, ASM_REG_R_N2
, ASM_REG_W_N2
},
213 {11, "n3", 24, ASM_REG_R_N3
, ASM_REG_W_N3
},
214 {12, "n4", 24, ASM_REG_R_N4
, ASM_REG_W_N4
},
215 {13, "n5", 24, ASM_REG_R_N5
, ASM_REG_W_N5
},
216 {14, "n6", 24, ASM_REG_R_N6
, ASM_REG_W_N6
},
217 {15, "n7", 24, ASM_REG_R_N7
, ASM_REG_W_N7
},
218 {16, "m0", 24, ASM_REG_R_M0
, ASM_REG_W_M0
},
219 {17, "m1", 24, ASM_REG_R_M1
, ASM_REG_W_M1
},
220 {18, "m2", 24, ASM_REG_R_M2
, ASM_REG_W_M2
},
221 {19, "m3", 24, ASM_REG_R_M3
, ASM_REG_W_M3
},
222 {20, "m4", 24, ASM_REG_R_M4
, ASM_REG_W_M4
},
223 {21, "m5", 24, ASM_REG_R_M5
, ASM_REG_W_M5
},
224 {22, "m6", 24, ASM_REG_R_M6
, ASM_REG_W_M6
},
225 {23, "m7", 24, ASM_REG_R_M7
, ASM_REG_W_M7
},
226 {24, "x0", 24, ASM_REG_R_X0
, ASM_REG_W_X0
},
227 {25, "x1", 24, ASM_REG_R_X1
, ASM_REG_W_X1
},
228 {26, "y0", 24, ASM_REG_R_Y0
, ASM_REG_W_Y0
},
229 {27, "y1", 24, ASM_REG_R_Y1
, ASM_REG_W_Y1
},
230 {28, "a0", 24, ASM_REG_R_A0
, ASM_REG_W_A0
},
231 {29, "a1", 24, ASM_REG_R_A1
, ASM_REG_W_A1
},
232 {30, "a2", 8, ASM_REG_R_A2
, ASM_REG_W_A2
},
233 {31, "b0", 24, ASM_REG_R_B0
, ASM_REG_W_B0
},
234 {32, "b1", 24, ASM_REG_R_B1
, ASM_REG_W_B1
},
235 {33, "b2", 8, ASM_REG_R_B2
, ASM_REG_W_B2
},
236 {34, "omr", 24, ASM_REG_R_OMR
, ASM_REG_W_OMR
},
237 {35, "vba", 24, ASM_REG_R_VBA
, ASM_REG_W_VBA
},
238 {36, "ep", 24, ASM_REG_R_EP
, ASM_REG_W_EP
},
239 {37, "sc", 24, ASM_REG_R_SC
, ASM_REG_W_SC
},
240 {38, "sz", 24, ASM_REG_R_SZ
, ASM_REG_W_SZ
},
241 {39, "sr", 24, ASM_REG_R_SR
, ASM_REG_W_SR
},
242 {40, "sp", 24, ASM_REG_R_SP
, ASM_REG_W_SP
},
243 {41, "la", 24, ASM_REG_R_LA
, ASM_REG_W_LA
},
244 {42, "lc", 24, ASM_REG_R_LC
, ASM_REG_W_LC
},
245 {43, "pc", 24, ASM_REG_R_PC
, ASM_REG_W_PC
}
249 static int dsp563xx_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
252 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
255 if (target
->state
!= TARGET_HALTED
)
257 return ERROR_TARGET_NOT_HALTED
;
260 *reg_list_size
= DSP563XX_NUMCOREREGS
;
261 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
263 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
265 (*reg_list
)[i
] = &dsp563xx
->core_cache
->reg_list
[i
];
272 int dsp563xx_read_core_reg(struct target
*target
, int num
)
275 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
276 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
278 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
279 return ERROR_INVALID_ARGUMENTS
;
281 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
282 reg_value
= dsp563xx
->core_regs
[num
];
283 buf_set_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
284 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
285 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
290 int dsp563xx_write_core_reg(struct target
*target
, int num
)
293 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
294 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
296 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
297 return ERROR_INVALID_ARGUMENTS
;
299 reg_value
= buf_get_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32);
300 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
301 dsp563xx
->core_regs
[num
] = reg_value
;
302 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
303 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
308 int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
)
310 struct dsp563xx_common
*dsp563xx
= calloc(1, sizeof(struct dsp563xx_common
));
312 dsp563xx
->jtag_info
.tap
= target
->tap
;
313 target
->arch_info
= dsp563xx
;
314 dsp563xx
->read_core_reg
= dsp563xx_read_core_reg
;
315 dsp563xx
->write_core_reg
= dsp563xx_write_core_reg
;
320 int dsp563xx_get_core_reg(struct reg
*reg
)
324 LOG_DEBUG("%s", __FUNCTION__
);
326 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
327 struct target
*target
= dsp563xx_reg
->target
;
328 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
330 if (target
->state
!= TARGET_HALTED
)
332 return ERROR_TARGET_NOT_HALTED
;
335 retval
= dsp563xx
->read_core_reg(target
, dsp563xx_reg
->num
);
340 int dsp563xx_set_core_reg(struct reg
*reg
, uint8_t * buf
)
342 LOG_DEBUG("%s", __FUNCTION__
);
344 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
345 struct target
*target
= dsp563xx_reg
->target
;
346 uint32_t value
= buf_get_u32(buf
, 0, 32);
348 if (target
->state
!= TARGET_HALTED
)
350 return ERROR_TARGET_NOT_HALTED
;
353 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
360 int dsp563xx_save_context(struct target
*target
)
364 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
365 struct dsp563xx_core_reg
*arch_info
;
367 for (i
= 0; i
< DSP563XX_NUMCOREREGS
- 1; i
++)
370 // if (!dsp563xx->core_cache->reg_list[i].valid)
372 arch_info
= dsp563xx
->core_cache
->reg_list
[i
].arch_info
;
373 dsp563xx_once_execute_dw_ir(target
->tap
, arch_info
->r_cmd
,
375 dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000);
376 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
,
378 dsp563xx
->core_regs
[i
] = data
;
379 dsp563xx
->read_core_reg(target
, i
);
384 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
, &data
);
385 dsp563xx
->core_regs
[i
] = data
;
386 dsp563xx
->read_core_reg(target
, i
);
391 int dsp563xx_restore_context(struct target
*target
)
394 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
395 struct dsp563xx_core_reg
*arch_info
;
397 for (i
= 0; i
< DSP563XX_NUMCOREREGS
- 1; i
++)
399 if (dsp563xx
->core_cache
->reg_list
[i
].dirty
)
401 arch_info
= dsp563xx
->core_cache
->reg_list
[i
].arch_info
;
403 dsp563xx
->write_core_reg(target
, i
);
405 dsp563xx_once_execute_dw_ir(target
->tap
, arch_info
->w_cmd
,
406 dsp563xx
->core_regs
[i
]);
407 dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000);
414 static const struct reg_arch_type dsp563xx_reg_type
= {
415 .get
= dsp563xx_get_core_reg
,
416 .set
= dsp563xx_set_core_reg
,
419 int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
421 /* get pointers to arch-specific information */
422 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
424 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
425 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
426 struct reg
*reg_list
= malloc(sizeof(struct reg
) * DSP563XX_NUMCOREREGS
);
427 struct dsp563xx_core_reg
*arch_info
=
428 malloc(sizeof(struct dsp563xx_core_reg
) * DSP563XX_NUMCOREREGS
);
431 LOG_DEBUG("%s", __FUNCTION__
);
433 /* Build the process context cache */
434 cache
->name
= "dsp563xx registers";
436 cache
->reg_list
= reg_list
;
437 cache
->num_regs
= DSP563XX_NUMCOREREGS
;
439 dsp563xx
->core_cache
= cache
;
441 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
443 arch_info
[i
].num
= dsp563xx_regs
[i
].id
;
444 arch_info
[i
].name
= dsp563xx_regs
[i
].name
;
445 arch_info
[i
].size
= dsp563xx_regs
[i
].bits
;
446 arch_info
[i
].r_cmd
= dsp563xx_regs
[i
].r_cmd
;
447 arch_info
[i
].w_cmd
= dsp563xx_regs
[i
].w_cmd
;
448 arch_info
[i
].target
= target
;
449 arch_info
[i
].dsp563xx_common
= dsp563xx
;
450 reg_list
[i
].name
= dsp563xx_regs
[i
].name
;
451 reg_list
[i
].size
= dsp563xx_regs
[i
].bits
;
452 reg_list
[i
].value
= calloc(1, 4);
453 reg_list
[i
].dirty
= 0;
454 reg_list
[i
].valid
= 0;
455 reg_list
[i
].type
= &dsp563xx_reg_type
;
456 reg_list
[i
].arch_info
= &arch_info
[i
];
462 int dsp563xx_arch_state(struct target
*target
)
464 LOG_DEBUG("%s", __FUNCTION__
);
468 int dsp563xx_jtag_status(struct target
*target
, uint8_t * status
)
474 dsp563xx_jtag_sendinstr(target
->tap
, &ir_in
, JTAG_INSTR_ENABLE_ONCE
);
475 dsp563xx_execute_queue();
482 int dsp563xx_jtag_debug_request(struct target
*target
)
487 while (ir_in
!= JTAG_STATUS_DEBUG
)
489 dsp563xx_jtag_sendinstr(target
->tap
, &ir_in
,
490 JTAG_INSTR_DEBUG_REQUEST
);
491 dsp563xx_execute_queue();
492 LOG_DEBUG("JTAG CMD 7 res: %02X", ir_in
);
493 dsp563xx_jtag_sendinstr(target
->tap
, &ir_in
, JTAG_INSTR_ENABLE_ONCE
);
494 dsp563xx_execute_queue();
495 LOG_DEBUG("JTAG CMD 6 res: %02X", ir_in
);
498 return ERROR_TARGET_FAILURE
;
501 if (ir_in
!= JTAG_STATUS_DEBUG
)
503 return ERROR_TARGET_FAILURE
;
509 int dsp563xx_poll(struct target
*target
)
512 uint32_t once_status
;
514 dsp563xx_jtag_status(target
, &jtag_status
);
516 if ((jtag_status
& 1) != 1)
518 target
->state
= TARGET_UNKNOWN
;
520 ("jtag status contains invalid mode value - communication failure");
521 return ERROR_TARGET_FAILURE
;
524 if (jtag_status
!= JTAG_STATUS_DEBUG
)
526 target
->state
= TARGET_RUNNING
;
529 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
, &once_status
);
531 if ((once_status
& DSP563XX_ONCE_OSCR_DEBUG_M
) == DSP563XX_ONCE_OSCR_DEBUG_M
)
533 target
->state
= TARGET_HALTED
;
540 int dsp563xx_halt(struct target
*target
)
543 uint32_t once_status
;
544 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
546 if (target
->state
== TARGET_HALTED
)
548 LOG_DEBUG("target was already halted");
552 if (target
->state
== TARGET_UNKNOWN
)
554 LOG_WARNING("target was in unknown state when halt was requested");
557 // if ( jtag_status != 0x0d )
559 dsp563xx_jtag_debug_request(target
);
561 /* store pipeline register */
562 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
,
563 &dsp563xx
->pipeline_context
.once_opilr
);
564 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
,
565 &dsp563xx
->pipeline_context
.once_opdbr
);
567 dsp563xx_save_context(target
);
569 dsp563xx_jtag_status(target
, &jtag_status
);
570 LOG_DEBUG("%02X", jtag_status
);
571 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
,
573 LOG_DEBUG("%02X", (unsigned) once_status
);
576 LOG_DEBUG("target->state: %s", target_state_name(target
));
578 LOG_DEBUG("%s", __FUNCTION__
);
583 #define DSP563XX_ASM_CMD_JUMP 0x0AF080
585 int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
,
586 int handle_breakpoints
, int debug_execution
)
588 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
590 LOG_DEBUG("%s", __FUNCTION__
);
592 dsp563xx_restore_context(target
);
596 /* restore pipeline registers and go */
597 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
,
598 dsp563xx
->pipeline_context
.once_opilr
);
599 dsp563xx_once_reg_write(target
->tap
,
600 DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
|
601 DSP563XX_ONCE_OCR_GO
,
602 dsp563xx
->pipeline_context
.once_opdbr
);
606 /* set to go register and jump */
607 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
,
608 DSP563XX_ASM_CMD_JUMP
);
609 dsp563xx_once_reg_write(target
->tap
,
610 DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
611 | DSP563XX_ONCE_OCR_GO
, address
);
614 target
->state
= TARGET_RUNNING
;
619 int dsp563xx_step(struct target
*target
, int current
, uint32_t address
,
620 int handle_breakpoints
)
622 uint32_t once_status
;
624 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
626 if (target
->state
!= TARGET_HALTED
)
628 LOG_DEBUG("target was not halted");
632 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
634 dsp563xx_jtag_debug_request(target
);
636 dsp563xx_restore_context(target
);
638 /* reset trace mode */
639 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, 0x000000);
640 /* enable trace mode */
641 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
,
642 DSP563XX_ONCE_OSCR_TME
);
646 /* on JUMP we need one extra cycle */
650 /* load step counter with N-1 */
651 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OTC
, cnt
);
655 /* restore pipeline registers and go */
656 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
,
657 dsp563xx
->pipeline_context
.once_opilr
);
658 dsp563xx_once_reg_write(target
->tap
,
659 DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
|
660 DSP563XX_ONCE_OCR_GO
,
661 dsp563xx
->pipeline_context
.once_opdbr
);
665 /* set to go register and jump */
666 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
,
667 DSP563XX_ASM_CMD_JUMP
);
668 dsp563xx_once_reg_write(target
->tap
,
669 DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
670 | DSP563XX_ONCE_OCR_GO
, address
);
675 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
,
678 if (once_status
& DSP563XX_ONCE_OSCR_TO
)
680 /* store pipeline register */
681 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
,
682 &dsp563xx
->pipeline_context
.
684 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
,
685 &dsp563xx
->pipeline_context
.
688 dsp563xx_save_context(target
);
690 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABFR
,
692 LOG_DEBUG("%08X", (unsigned) dr_in
);
693 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABDR
,
695 LOG_DEBUG("%08X", (unsigned) dr_in
);
696 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
,
698 LOG_DEBUG("%08X", (unsigned) dr_in
);
700 /* reset trace mode */
701 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
,
711 int dsp563xx_assert_reset(struct target
*target
)
713 target
->state
= TARGET_RESET
;
715 LOG_DEBUG("%s", __FUNCTION__
);
719 int dsp563xx_deassert_reset(struct target
*target
)
721 target
->state
= TARGET_RUNNING
;
723 LOG_DEBUG("%s", __FUNCTION__
);
727 int dsp563xx_soft_reset_halt(struct target
*target
)
729 LOG_DEBUG("%s", __FUNCTION__
);
735 * 46F400 AABBCC move #$aabbcc,y0
736 * 60F400 AABBCC move #$aabbcc,r0
737 * 467000 AABBCC move y0,x:AABBCC
738 * 607000 AABBCC move r0,x:AABBCC
740 * 46E000 move x:(r0),y0
741 * 4EE000 move y:(r0),y0
742 * 07E086 move p:(r0),y0
751 * 61F000 AABBCC move x:AABBCC,r1
752 * 076190 movem r0,p:(r1)
755 int dsp563xx_read_memory_p(struct target
*target
, uint32_t address
,
756 uint32_t size
, uint32_t count
, uint8_t * buffer
)
762 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8"
763 PRIx32
, address
, size
, count
);
765 if (target
->state
!= TARGET_HALTED
)
767 LOG_WARNING("target not halted");
768 return ERROR_TARGET_NOT_HALTED
;
773 for (i
= 0; i
< x
; i
++)
775 dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x60F400, address
+ i
);
776 dsp563xx_once_execute_sw_ir_nq(target
->tap
, 0x07E086);
777 dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x467000, 0xfffffc);
778 dsp563xx_execute_queue();
780 dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, &data
);
796 int dsp563xx_write_memory_p(struct target
*target
, uint32_t address
, uint32_t size
,
797 uint32_t count
, uint8_t * buffer
)
803 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8"
804 PRIx32
"", address
, size
, count
);
806 if (target
->state
!= TARGET_HALTED
)
808 LOG_WARNING("target not halted");
809 return ERROR_TARGET_NOT_HALTED
;
814 for (i
= 0; i
< x
; i
++)
822 data
|= (*buffer
++) << 8;
824 data
|= (*buffer
++) << 16;
826 data
|= (*buffer
++) << 24;
828 // LOG_DEBUG("%08X", data);
830 dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x61F400, address
+ i
);
831 dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x60F400, data
);
832 dsp563xx_once_execute_sw_ir_nq(target
->tap
, 0x076190);
833 dsp563xx_execute_queue();
839 int dsp563xx_jtag_senddat(struct jtag_tap
*tap
, uint32_t * dr_in
, uint32_t dr_out
,
842 return dsp563xx_write_dr_u32(tap
, dr_in
, dr_out
, len
, 1);
845 int dsp563xx_jtag_sendinstr(struct jtag_tap
*tap
, uint8_t * ir_in
, uint8_t ir_out
)
847 return dsp563xx_write_ir_u8(tap
, ir_in
, ir_out
, DSP563XX_JTAG_INS_LEN
, 1);
850 /* IR and DR functions */
851 int dsp563xx_write_ir(struct jtag_tap
*tap
, uint8_t * ir_in
, uint8_t * ir_out
,
856 LOG_ERROR("invalid tap");
859 if (ir_len
!= tap
->ir_length
)
861 LOG_ERROR("invalid ir_len");
866 jtag_add_plain_ir_scan(tap
->ir_length
, ir_out
, ir_in
, TAP_IDLE
);
872 int dsp563xx_write_dr(struct jtag_tap
*tap
, uint8_t * dr_in
, uint8_t * dr_out
,
877 LOG_ERROR("invalid tap");
882 jtag_add_plain_dr_scan(dr_len
, dr_out
, dr_in
, TAP_IDLE
);
888 int dsp563xx_write_ir_u8(struct jtag_tap
*tap
, uint8_t * ir_in
, uint8_t ir_out
,
893 LOG_ERROR("ir_len overflow, maxium is 8");
897 dsp563xx_write_ir(tap
, ir_in
, &ir_out
, ir_len
, rti
);
902 int dsp563xx_write_dr_u8(struct jtag_tap
*tap
, uint8_t * dr_in
, uint8_t dr_out
,
907 LOG_ERROR("dr_len overflow, maxium is 8");
911 dsp563xx_write_dr(tap
, dr_in
, &dr_out
, dr_len
, rti
);
916 int dsp563xx_write_ir_u16(struct jtag_tap
*tap
, uint16_t * ir_in
, uint16_t ir_out
,
921 LOG_ERROR("ir_len overflow, maxium is 16");
925 dsp563xx_write_ir(tap
, (uint8_t *) ir_in
, (uint8_t *) & ir_out
, ir_len
, rti
);
930 int dsp563xx_write_dr_u16(struct jtag_tap
*tap
, uint16_t * dr_in
, uint16_t dr_out
,
935 LOG_ERROR("dr_len overflow, maxium is 16");
939 dsp563xx_write_dr(tap
, (uint8_t *) dr_in
, (uint8_t *) & dr_out
, dr_len
, rti
);
944 int dsp563xx_write_ir_u32(struct jtag_tap
*tap
, uint32_t * ir_in
, uint32_t ir_out
,
949 LOG_ERROR("ir_len overflow, maxium is 32");
953 dsp563xx_write_ir(tap
, (uint8_t *) ir_in
, (uint8_t *) & ir_out
, ir_len
, rti
);
958 int dsp563xx_write_dr_u32(struct jtag_tap
*tap
, uint32_t * dr_in
, uint32_t dr_out
,
963 LOG_ERROR("dr_len overflow, maxium is 32");
967 dsp563xx_write_dr(tap
, (uint8_t *) dr_in
, (uint8_t *) & dr_out
, dr_len
, rti
);
972 int dsp563xx_execute_queue(void)
974 return jtag_execute_queue();
977 /** Holds methods for DSP563XX targets. */
978 struct target_type dsp563xx_target
= {
981 .poll
= dsp563xx_poll
,
982 .arch_state
= dsp563xx_arch_state
,
984 .target_request_data
= NULL
,
986 .get_gdb_reg_list
= dsp563xx_get_gdb_reg_list
,
988 .halt
= dsp563xx_halt
,
989 .resume
= dsp563xx_resume
,
990 .step
= dsp563xx_step
,
992 .assert_reset
= dsp563xx_assert_reset
,
993 .deassert_reset
= dsp563xx_deassert_reset
,
994 .soft_reset_halt
= dsp563xx_soft_reset_halt
,
996 .read_memory
= dsp563xx_read_memory_p
,
997 .write_memory
= dsp563xx_write_memory_p
,
999 .target_create
= dsp563xx_target_create
,
1000 .init_target
= dsp563xx_init_target
,