tcl/target/c100config.tcl

   1
   2 # board(-config) specfic parameters file.
   3
   4 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
   5 proc config {label} {
   6     return [dict get [configC100] $label ]
   7 }
   8
   9 # show the value for the param. with label
  10 proc showconfig {label} {
  11     puts [format "0x%x" [dict get [configC100] $label ]]
  12 }
  13
  14 # Telo board config
  15 # when there are more then one board config
  16 # use soft links to c100board-config.tcl
  17 # so that only the right board-config gets
  18 # included (just like include/configs/board-configs.h
  19 # in u-boot.
  20 proc configC100 {} {
  21     # xtal freq. 24MHz
  22     dict set configC100 CFG_REFCLKFREQ           24000000
  23
  24     # Amba Clk 165MHz
  25     dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000
  26     dict set configC100 w_amba 1
  27     dict set configC100 x_amba 1
  28     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
  29     dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
  30
  31     # Arm Clk 450MHz, must be a multiple of 25 MHz
  32     dict set configC100 CFG_ARM_CLOCK      450000000
  33     dict set configC100 w_arm 0
  34     dict set configC100 x_arm 1
  35     # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
  36     dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
  37
  38
  39 }
  40
  41 # This should be called for reset init event handler
  42 proc setupTelo {} {
  43
  44     # setup GPIO used as control signals for C100
  45     setupGPIO
  46     # This will allow acces to lower 8MB or NOR
  47     lowGPIO5
  48     # setup NOR size,timing,etc.
  49     setupNOR
  50     # setup internals + PLL + DDR2
  51     initC100
  52 }
  53
  54
  55 proc setupNOR {} {
  56     puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
  57     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
  58     set EX_CSEN_REG         [regs EX_CSEN_REG ]
  59     set EX_CS0_SEG_REG      [regs EX_CS0_SEG_REG ]
  60     set EX_CS0_CFG_REG      [regs EX_CS0_CFG_REG ]
  61     set EX_CS0_TMG1_REG     [regs EX_CS0_TMG1_REG ]
  62     set EX_CS0_TMG2_REG     [regs EX_CS0_TMG2_REG ]
  63     set EX_CS0_TMG3_REG     [regs EX_CS0_TMG3_REG ]
  64     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
  65     set EX_MFSM_REG         [regs EX_MFSM_REG ]
  66     set EX_CSFSM_REG        [regs EX_CSFSM_REG ]
  67     set EX_WRFSM_REG        [regs EX_WRFSM_REG ]
  68     set EX_RDFSM_REG        [regs EX_RDFSM_REG ]
  69
  70     # enable Expansion Bus Clock + CS0 (NOR)
  71     mww $EX_CSEN_REG 0x3
  72     # set the address space for CS0=16MB
  73     mww $EX_CS0_SEG_REG 0x7ff
  74     # set the CS0 bus width to 16-bit
  75     mww $EX_CS0_CFG_REG 0x202
  76     # set timings to NOR
  77     mww $EX_CS0_TMG1_REG 0x03034006
  78     mww $EX_CS0_TMG2_REG 0x04040002
  79     #mww $EX_CS0_TMG3_REG
  80     # set EBUS clock 165/5=33MHz
  81     mww $EX_CLOCK_DIV_REG 0x5
  82     # everthing else is OK with default
  83 }
  84
  85 proc bootNOR {} {
  86     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
  87     set BLOCK_RESET_REG        [regs BLOCK_RESET_REG]
  88     set DDR_RST                [regs DDR_RST]
  89
  90     # put DDR controller in reset (so that it comes reset in u-boot)
  91     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
  92     # setup CS0 controller for NOR
  93     setupNOR
  94     # make sure we are accessing the lower part of NOR
  95     lowGPIO5
  96     # set PC to start of NOR (at boot 0x20000000 = 0x0)
  97     reg pc $EXP_CS0_BASEADDR
  98     # run
  99     resume
 100 }
 101 proc setupGPIO {} {
 102     puts "Setting up GPIO block for Telo"
 103     # This is current setup for Telo (see sch. for details):
 104     #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
 105     #GPIO1 irq line for FXS-FXO
 106     #GPIO5 addr22 for NOR flash (access to upper 8MB)
 107     #GPIO17 reset for DECT module.
 108     #GPIO29 CS_n for NAND
 109
 110     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 111     set GPIO_OE_REG                 [regs GPIO_OE_REG]
 112
 113     # set GPIO29=GPIO17=1, GPIO5=0
 114     mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
 115     # enable [as output] GPIO29,GPIO17,GPIO5
 116     mww $GPIO_OE_REG [expr  1<<29 | 1<<17 | 1<<5]
 117 }
 118
 119 proc highGPIO5 {} {
 120     puts "GPIO5 high"
 121     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 122     # set GPIO5=1
 123     mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
 124 }
 125
 126 proc lowGPIO5 {} {
 127     puts "GPIO5 low"
 128     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 129     # set GPIO5=0
 130     mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
 131 }
 132
 133 proc boardID {id} {
 134     # so far built:
 135     # 4'b1111
 136     dict set boardID 15 name "EVT1"
 137     dict set boardID 15 ddr2size 128M
 138     # dict set boardID 15 nandsize 1G
 139     # dict set boardID 15 norsize 16M
 140     # 4'b0000
 141     dict set boardID 0 name "EVT2"
 142     dict set boardID 0 ddr2size 128M
 143     # 4'b0001
 144     dict set boardID 1 name "EVT3"
 145     dict set boardID 1 ddr2size 256M
 146     # 4'b1110
 147     dict set boardID 14 name "EVT3_old"
 148     dict set boardID 14 ddr2size 128M
 149     # 4'b0010
 150     dict set boardID 2 name "EVT4"
 151     dict set boardID 2 ddr2size 256M
 152
 153     return $boardID
 154 }
 155
 156
 157 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
 158 # figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
 159 proc ooma_board_detect {} {
 160     set GPIO_BOOTSTRAP_REG      [regs GPIO_BOOTSTRAP_REG]
 161
 162     # read the current value of the BOOTSRAP pins
 163     set tmp [mrw $GPIO_BOOTSTRAP_REG]
 164     puts [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
 165     # extract the GPBP bits
 166     set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
 167
 168     # display board ID
 169     puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 170     # show it on serial console
 171     putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 172     # return the ddr2 size, used to configure DDR2 on a given board.
 173     return [dict get [boardID $gpbt] $gpbt ddr2size]
 174 }
 175
 176 proc configureDDR2regs_256M {} {
 177
 178     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 179     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 180     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 181     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 182     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 183     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 184     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 185     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 186     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 187     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 188     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 189     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 190     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 191     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 192     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 193     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 194     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 195     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 196     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 197     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 198     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 199
 200     set DENALI_CTL_02_VAL 0x0100000000010100
 201     set DENALI_CTL_11_VAL 0x433a32164a560a00
 202
 203     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
 204     # 01_DATA mod [40]=1, enable BA2
 205     mw64bit $DENALI_CTL_01_DATA  0x0100010100000001
 206     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
 207     mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
 208     mw64bit $DENALI_CTL_04_DATA  0x0000010100000001
 209     mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
 210     mw64bit $DENALI_CTL_06_DATA  0x060a020200020202
 211     mw64bit $DENALI_CTL_07_DATA  0x0000000300000206
 212     mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209
 213     mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a
 214     mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18
 215     # 11_DATA mod [39-32]=16,more refresh
 216     mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
 217     mw64bit $DENALI_CTL_12_DATA  0x0000000000000800
 218     mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
 219     mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
 220     mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000
 221     mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000
 222     mw64bit $DENALI_CTL_17_DATA  0x0000000000000000
 223     mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
 224     mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600
 225     mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8
 226
 227     set wr_dqs_shift 0x40
 228     # start DDRC
 229     mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
 230     # wait int_status[2] (DRAM init complete)
 231     puts -nonewline "Waiting for DDR2 controller to init..."
 232     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 233     while { [expr $tmp & 0x040000] == 0 } {
 234         sleep 1
 235         set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 236     }
 237     puts "done."
 238
 239     # do ddr2 training sequence
 240     # TBD (for now, if you need it, run trainDDR command)
 241 }
 242
 243 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
 244 # The values are computed based on Mindspeed and Nanya datasheets
 245 proc configureDDR2regs_128M {} {
 246
 247     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 248     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 249     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 250     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 251     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 252     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 253     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 254     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 255     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 256     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 257     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 258     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 259     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 260     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 261     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 262     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 263     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 264     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 265     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 266     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 267     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 268
 269
 270     set DENALI_CTL_02_VAL 0x0100010000010100
 271     set DENALI_CTL_11_VAL 0x433A42124A650A37
 272     # set some default values
 273     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
 274     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
 275     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
 276     mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
 277     mw64bit $DENALI_CTL_04_DATA  0x0201010100000201
 278     mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
 279     mw64bit $DENALI_CTL_06_DATA  0x050A020200020202
 280     mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205
 281     mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209
 282     mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00
 283     mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A
 284     mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
 285     mw64bit $DENALI_CTL_12_DATA  0x0000080000000800
 286     mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
 287     mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
 288     mw64bit $DENALI_CTL_15_DATA  0x0508000000000000
 289     mw64bit $DENALI_CTL_16_DATA  0x000020472D200000
 290     mw64bit $DENALI_CTL_17_DATA  0x0000000008000000
 291     mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
 292     mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604
 293     mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8
 294
 295     set wr_dqs_shift 0x40
 296     # start DDRC
 297     mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
 298     # wait int_status[2] (DRAM init complete)
 299     puts -nonewline "Waiting for DDR2 controller to init..."
 300     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 301     while { [expr $tmp & 0x040000] == 0 } {
 302         sleep 1
 303         set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 304     }
 305     # This is not necessary
 306     #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
 307     puts "done."
 308
 309     # do ddr2 training sequence
 310     # TBD (for now, if you need it, run trainDDR command)
 311 }
 312
 313
 314
 315 proc setupUART0 {} {
 316     # configure UART0 to 115200, 8N1
 317     set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]
 318     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
 319     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
 320     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
 321     set UART0_LCR                   [regs UART0_LCR]
 322     set LCR_DLAB                    [regs LCR_DLAB]
 323     set UART0_DLL                   [regs UART0_DLL]
 324     set UART0_DLH                   [regs UART0_DLH]
 325     set UART0_IIR                   [regs UART0_IIR]
 326     set UART0_IER                   [regs UART0_IER]
 327     set LCR_ONE_STOP                [regs LCR_ONE_STOP]
 328     set LCR_CHAR_LEN_8              [regs LCR_CHAR_LEN_8]
 329     set FCR_XMITRES                 [regs FCR_XMITRES]
 330     set FCR_RCVRRES                 [regs FCR_RCVRRES]
 331     set FCR_FIFOEN                  [regs FCR_FIFOEN]
 332     set IER_UUE                     [regs IER_UUE]
 333
 334     # unlock writing to IOCTRL register
 335     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
 336     # enable UART0
 337     mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
 338     # baudrate  115200
 339     # This should really be amba_clk/(16*115200) but amba_clk=165MHz
 340     set tmp 89
 341     # Enable Divisor Latch access
 342     mmw  $UART0_LCR $LCR_DLAB 0x0
 343     # set the divisor to $tmp
 344     mww $UART0_DLL [expr $tmp & 0xff]
 345     mww $UART0_DLH [expr $tmp >> 8]
 346     # Disable Divisor Latch access
 347     mmw  $UART0_LCR 0x0 $LCR_DLAB
 348     # set the UART to 8N1
 349     mmw  $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
 350     # reset FIFO
 351     mmw  $UART0_IIR [expr $FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
 352     #  enable FFUART
 353     mww $UART0_IER $IER_UUE
 354 }
 355
 356 proc putcUART0 {char} {
 357
 358     set UART0_LSR           [regs UART0_LSR]
 359     set UART0_THR           [regs UART0_THR]
 360     set LSR_TEMT            [regs LSR_TEMT]
 361
 362     # convert the 'char' to digit
 363     set tmp [ scan $char %c ]
 364     # /* wait for room in the tx FIFO on FFUART */
 365     while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
 366     mww $UART0_THR $tmp
 367     if { $char == "\n" } { putcUART0 \r }
 368 }
 369
 370 proc putsUART0 {str} {
 371     set index 0
 372     set len [string length $str]
 373     while { $index < $len } {
 374         putcUART0 [string index $str $index]
 375         set index [expr $index + 1]
 376     }
 377 }
 378
 379
 380 proc trainDDR2 {} {
 381     set ARAM_BASEADDR   [regs ARAM_BASEADDR]
 382
 383     # you must have run 'reset init' or u-boot
 384     # load the training code to ARAM
 385     load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
 386     # set PC to start of NOR (at boot 0x20000000 = 0x0)
 387     reg pc $ARAM_BASEADDR
 388     # run
 389     resume
 390 }
 391
 392 proc flashUBOOT {file} {
 393     # this will update uboot on NOR partition
 394     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
 395
 396     # setup CS0 controller for NOR
 397     setupNOR
 398     # make sure we are accessing the lower part of NOR
 399     lowGPIO5
 400     flash probe 0
 401     puts "Erasing sectors 0-3 for uboot"
 402     putsUART0 "Erasing sectors 0-3 for uboot\n"
 403     flash erase_sector 0 0 3
 404     puts "Programming u-boot"
 405     putsUART0 "Programming u-boot..."
 406     memwrite burst enable
 407     flash write_image $file $EXP_CS0_BASEADDR
 408     memwrite burst disable
 409     putsUART0 "done.\n"
 410     putsUART0 "Rebooting, please wait!\n"
 411     reboot
 412 }