tcl/target/c100regs.tcl

   1 # Note that I basically converted
   2 # u-boot/include/asm-arm/arch/comcerto_100.h
   3 # defines
   4
   5 # this is a work-around for 'global' not working under Linux
   6 # access registers by calling this routine.
   7 # For example:
   8 # set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
   9 proc regs {reg} {
  10     return [dict get [regsC100] $reg ]
  11 }
  12
  13 proc showreg {reg} {
  14     puts [format "0x%x" [dict get [regsC100] $reg ]]
  15 }
  16
  17 proc regsC100 {} {
  18 #/* memcore */
  19 #/* device memory base addresses */
  20 #// device memory sizes
  21 #/* ARAM SIZE=64K */
  22 dict set regsC100 ARAM_SIZE             0x00010000
  23 dict set regsC100 ARAM_BASEADDR 0x0A000000
  24
  25 #/* Hardware Interface Units */
  26 dict set regsC100 APB_BASEADDR  0x10000000
  27 #/* APB_SIZE=16M address range */
  28 dict set regsC100 APB_SIZE              0x01000000
  29
  30 dict set regsC100 EXP_CS0_BASEADDR       0x20000000
  31 dict set regsC100 EXP_CS1_BASEADDR       0x24000000
  32 dict set regsC100 EXP_CS2_BASEADDR       0x28000000
  33 dict set regsC100 EXP_CS3_BASEADDR       0x2C000000
  34 dict set regsC100 EXP_CS4_BASEADDR       0x30000000
  35
  36 dict set regsC100 DDR_BASEADDR           0x80000000
  37
  38 dict set regsC100 TDM_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000]
  39 dict set regsC100 PHI_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000]
  40 dict set regsC100 TDMA_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000]
  41 dict set regsC100 ASA_DDR_BASEADDR              [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000]
  42 dict set regsC100 ASA_ARAM_BASEADDR             [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000]
  43 dict set regsC100 TIMER_BASEADDR                [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000]
  44 dict set regsC100 ASD_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000]
  45 dict set regsC100 GPIO_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000]
  46 dict set regsC100 UART0_BASEADDR                [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000]
  47 dict set regsC100 UART1_BASEADDR                [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000]
  48 dict set regsC100 SPI_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000]
  49 dict set regsC100 I2C_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000]
  50 dict set regsC100 INTC_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000]
  51 dict set regsC100 CLKCORE_BASEADDR              [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
  52 dict set regsC100 PUI_BASEADDR          [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
  53 dict set regsC100 GEMAC_BASEADDR                [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000]
  54 dict set regsC100 IDMA_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000]
  55 dict set regsC100 MEMCORE_BASEADDR              [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000]
  56 dict set regsC100 ASA_EBUS_BASEADDR             [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000]
  57 dict set regsC100 ASA_AAB_BASEADDR              [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000]
  58 dict set regsC100 GEMAC1_BASEADDR               [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000]
  59 dict set regsC100 EBUS_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000]
  60 dict set regsC100 MDMA_BASEADDR         [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000]
  61
  62
  63 #////////////////////////////////////////////////////////////
  64 #//     AHB block                                                                                           //
  65 #////////////////////////////////////////////////////////////
  66 dict set regsC100 ASA_ARAM_PRI_REG      [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00]
  67 dict set regsC100 ASA_ARAM_TC_REG       [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04]
  68 dict set regsC100 ASA_ARAM_TC_CR_REG    [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08]
  69 dict set regsC100 ASA_ARAM_STAT_REG     [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C]
  70
  71 dict set regsC100 ASA_EBUS_PRI_REG      [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00]
  72 dict set regsC100 ASA_EBUS_TC_REG       [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04]
  73 dict set regsC100 ASA_EBUS_TC_CR_REG    [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08]
  74 dict set regsC100 ASA_EBUS_STAT_REG     [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C]
  75
  76 dict set regsC100 IDMA_MASTER           0
  77 dict set regsC100 TDMA_MASTER           1
  78 dict set regsC100 USBIPSEC_MASTER       2
  79 dict set regsC100 ARM0_MASTER           3
  80 dict set regsC100 ARM1_MASTER           4
  81 dict set regsC100 MDMA_MASTER           5
  82
  83 #define IDMA_PRIORITY(level) (level)
  84 #define TDM_PRIORITY(level) (level << 4)
  85 #define USBIPSEC_PRIORITY(level) (level << 8)
  86 #define ARM0_PRIORITY(level) (level << 12)
  87 #define ARM1_PRIORITY(level) (level << 16)
  88 #define MDMA_PRIORITY(level) (level << 20)
  89
  90 dict set regsC100 ASA_TC_REQIDMAEN       [expr 1<<18]
  91 dict set regsC100 ASA_TC_REQTDMEN        [expr 1<<19]
  92 dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20]
  93 dict set regsC100 ASA_TC_REQARM0EN       [expr 1<<21]
  94 dict set regsC100 ASA_TC_REQARM1EN       [expr 1<<22]
  95 dict set regsC100 ASA_TC_REQMDMAEN       [expr 1<<23]
  96
  97 dict set regsC100 MEMORY_BASE_ADDR      0x80000000
  98 dict set regsC100 MEMORY_MAX_ADDR       [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10]
  99 dict set regsC100 MEMORY_CR             [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14]
 100 dict set regsC100 ROM_REMAP_EN  0x1
 101
 102 #define HAL_asb_priority(level) \
 103 #*(volatile unsigned *)ASA_PRI_REG = level
 104
 105 #define HAL_aram_priority(level) \
 106 #*(volatile unsigned *)ASA_ARAM_PRI_REG = level
 107
 108 #define HAL_aram_arbitration(arbitration_mask) \
 109 #*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
 110
 111 #define HAL_aram_defmaster(mask) \
 112 #*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
 113
 114 #////////////////////////////////////////////////////////////
 115 #// INTC block                                            //
 116 #////////////////////////////////////////////////////////////
 117
 118 dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18]
 119
 120 #////////////////////////////////////////////////////////////
 121 #// TIMER block                                           //
 122 #////////////////////////////////////////////////////////////
 123
 124 dict set regsC100 TIMER0_CNTR_REG       [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00]
 125 dict set regsC100 TIMER0_CURR_COUNT     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04]
 126 dict set regsC100 TIMER1_CNTR_REG       [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08]
 127 dict set regsC100 TIMER1_CURR_COUNT     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C]
 128
 129 dict set regsC100 TIMER2_CNTR_REG       [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18]
 130 dict set regsC100 TIMER2_LBOUND_REG     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10]
 131 dict set regsC100 TIMER2_HBOUND_REG     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14]
 132 dict set regsC100 TIMER2_CURR_COUNT     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C]
 133
 134 dict set regsC100 TIMER3_LOBND  [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20]
 135 dict set regsC100 TIMER3_HIBND  [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24]
 136 dict set regsC100 TIMER3_CTRL           [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28]
 137 dict set regsC100 TIMER3_CURR_COUNT     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C]
 138
 139 dict set regsC100 TIMER_MASK            [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40]
 140 dict set regsC100 TIMER_STATUS  [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
 141 dict set regsC100 TIMER_ACK             [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
 142 dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0]
 143 dict set regsC100 TIMER_WDT_CONTROL     [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4]
 144 dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8]
 145
 146
 147
 148 #////////////////////////////////////////////////////////////
 149 #//  EBUS block
 150 #////////////////////////////////////////////////////////////
 151
 152 dict set regsC100 EX_SWRST_REG          [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00]
 153 dict set regsC100 EX_CSEN_REG                   [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04]
 154 dict set regsC100 EX_CS0_SEG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08]
 155 dict set regsC100 EX_CS1_SEG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C]
 156 dict set regsC100 EX_CS2_SEG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10]
 157 dict set regsC100 EX_CS3_SEG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14]
 158 dict set regsC100 EX_CS4_SEG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18]
 159 dict set regsC100 EX_CS0_CFG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C]
 160 dict set regsC100 EX_CS1_CFG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20]
 161 dict set regsC100 EX_CS2_CFG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24]
 162 dict set regsC100 EX_CS3_CFG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28]
 163 dict set regsC100 EX_CS4_CFG_REG                [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C]
 164 dict set regsC100 EX_CS0_TMG1_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30]
 165 dict set regsC100 EX_CS1_TMG1_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34]
 166 dict set regsC100 EX_CS2_TMG1_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38]
 167 dict set regsC100 EX_CS3_TMG1_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C]
 168 dict set regsC100 EX_CS4_TMG1_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40]
 169 dict set regsC100 EX_CS0_TMG2_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44]
 170 dict set regsC100 EX_CS1_TMG2_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48]
 171 dict set regsC100 EX_CS2_TMG2_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C]
 172 dict set regsC100 EX_CS3_TMG2_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50]
 173 dict set regsC100 EX_CS4_TMG2_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54]
 174 dict set regsC100 EX_CS0_TMG3_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58]
 175 dict set regsC100 EX_CS1_TMG3_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C]
 176 dict set regsC100 EX_CS2_TMG3_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60]
 177 dict set regsC100 EX_CS3_TMG3_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64]
 178 dict set regsC100 EX_CS4_TMG3_REG               [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68]
 179 dict set regsC100 EX_CLOCK_DIV_REG              [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C]
 180
 181 dict set regsC100 EX_MFSM_REG           [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
 182 dict set regsC100 EX_MFSM_REG           [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
 183 dict set regsC100 EX_CSFSM_REG          [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104]
 184 dict set regsC100 EX_WRFSM_REG          [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108]
 185 dict set regsC100 EX_RDFSM_REG          [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C]
 186
 187
 188 dict set regsC100 EX_CLK_EN             0x00000001
 189 dict set regsC100 EX_CSBOOT_EN  0x00000002
 190 dict set regsC100 EX_CS0_EN             0x00000002
 191 dict set regsC100 EX_CS1_EN             0x00000004
 192 dict set regsC100 EX_CS2_EN             0x00000008
 193 dict set regsC100 EX_CS3_EN             0x00000010
 194 dict set regsC100 EX_CS4_EN             0x00000020
 195
 196 dict set regsC100 EX_MEM_BUS_8  0x00000000
 197 dict set regsC100 EX_MEM_BUS_16       0x00000002
 198 dict set regsC100 EX_MEM_BUS_32 0x00000004
 199 dict set regsC100 EX_CS_HIGH            0x00000008
 200 dict set regsC100 EX_WE_HIGH            0x00000010
 201 dict set regsC100 EX_RE_HIGH            0x00000020
 202 dict set regsC100 EX_ALE_MODE           0x00000040
 203 dict set regsC100 EX_STRB_MODE  0x00000080
 204 dict set regsC100 EX_DM_MODE            0x00000100
 205 dict set regsC100 EX_NAND_MODE  0x00000200
 206 dict set regsC100 EX_RDY_EN             0x00000400
 207 dict set regsC100 EX_RDY_EDGE           0x00000800
 208
 209 #////////////////////////////////////////////////////////////
 210 #//  GPIO block
 211 #////////////////////////////////////////////////////////////
 212
 213 # GPIO outputs register
 214 dict set regsC100 GPIO_OUTPUT_REG               [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
 215 # GPIO Output Enable register
 216 dict set regsC100 GPIO_OE_REG                   [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
 217 dict set regsC100 GPIO_HI_INT_ENABLE_REG        [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
 218 dict set regsC100 GPIO_LO_INT_ENABLE_REG        [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
 219 # GPIO input register
 220 dict set regsC100 GPIO_INPUT_REG                [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10]
 221 dict set regsC100 APB_ACCESS_WS_REG             [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14]
 222 dict set regsC100 MUX_CONF_REG          [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18]
 223 dict set regsC100 SYSCONF_REG                   [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C]
 224 dict set regsC100 GPIO_ARM_ID_REG               [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30]
 225 dict set regsC100 GPIO_BOOTSTRAP_REG            [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40]
 226 dict set regsC100 GPIO_LOCK_REG         [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38]
 227 dict set regsC100 GPIO_IOCTRL_REG               [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44]
 228 dict set regsC100 GPIO_DEVID_REG                [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50]
 229
 230 dict set regsC100 GPIO_IOCTRL_A15A16    0x00000001
 231 dict set regsC100 GPIO_IOCTRL_A17A18    0x00000002
 232 dict set regsC100 GPIO_IOCTRL_A19A21    0x00000004
 233 dict set regsC100 GPIO_IOCTRL_TMREVT0   0x00000008
 234 dict set regsC100 GPIO_IOCTRL_TMREVT1   0x00000010
 235 dict set regsC100 GPIO_IOCTRL_GPBT3     0x00000020
 236 dict set regsC100 GPIO_IOCTRL_I2C       0x00000040
 237 dict set regsC100 GPIO_IOCTRL_UART0     0x00000080
 238 dict set regsC100 GPIO_IOCTRL_UART1     0x00000100
 239 dict set regsC100 GPIO_IOCTRL_SPI       0x00000200
 240 dict set regsC100 GPIO_IOCTRL_HBMODE    0x00000400
 241
 242 dict set regsC100 GPIO_IOCTRL_VAL       0x55555555
 243
 244 dict set regsC100 GPIO_0                        0x01
 245 dict set regsC100 GPIO_1                        0x02
 246 dict set regsC100 GPIO_2                        0x04
 247 dict set regsC100 GPIO_3                        0x08
 248 dict set regsC100 GPIO_4                        0x10
 249 dict set regsC100 GPIO_5                        0x20
 250 dict set regsC100 GPIO_6                        0x40
 251 dict set regsC100 GPIO_7                        0x80
 252
 253 dict set regsC100 GPIO_RISING_EDGE      1
 254 dict set regsC100 GPIO_FALLING_EDGE     2
 255 dict set regsC100 GPIO_BOTH_EDGES       3
 256
 257 #////////////////////////////////////////////////////////////
 258 #// UART
 259 #////////////////////////////////////////////////////////////
 260
 261 dict set regsC100 UART0_RBR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
 262 dict set regsC100 UART0_THR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
 263 dict set regsC100 UART0_DLL             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
 264 dict set regsC100 UART0_IER             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
 265 dict set regsC100 UART0_DLH             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
 266 dict set regsC100 UART0_IIR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
 267 dict set regsC100 UART0_FCR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
 268 dict set regsC100 UART0_LCR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C]
 269 dict set regsC100 UART0_MCR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10]
 270 dict set regsC100 UART0_LSR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14]
 271 dict set regsC100 UART0_MSR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18]
 272 dict set regsC100 UART0_SCR             [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C]
 273
 274 dict set regsC100 UART1_RBR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
 275 dict set regsC100 UART1_THR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
 276 dict set regsC100 UART1_DLL             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
 277 dict set regsC100 UART1_IER             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
 278 dict set regsC100 UART1_DLH             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
 279 dict set regsC100 UART1_IIR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
 280 dict set regsC100 UART1_FCR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
 281 dict set regsC100 UART1_LCR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C]
 282 dict set regsC100 UART1_MCR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10]
 283 dict set regsC100 UART1_LSR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14]
 284 dict set regsC100 UART1_MSR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18]
 285 dict set regsC100 UART1_SCR             [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
 286
 287 # /* default */
 288 dict set regsC100 LCR_CHAR_LEN_5                0x00
 289 dict set regsC100 LCR_CHAR_LEN_6                0x01
 290 dict set regsC100 LCR_CHAR_LEN_7                0x02
 291 dict set regsC100 LCR_CHAR_LEN_8                0x03
 292 #/* One stop bit! - default */
 293 dict set regsC100 LCR_ONE_STOP          0x00
 294 #/* Two stop bit! */
 295 dict set regsC100 LCR_TWO_STOP          0x04
 296 #/* Parity Enable */
 297 dict set regsC100 LCR_PEN                       0x08
 298 dict set regsC100 LCR_PARITY_NONE               0x00
 299 #/* Even Parity Select */
 300 dict set regsC100 LCR_EPS                       0x10
 301 #/* Enable Parity  Stuff */
 302 dict set regsC100 LCR_PS                        0x20
 303 #/* Start Break */
 304 dict set regsC100 LCR_SBRK                      0x40
 305 #/* Parity Stuff Bit */
 306 dict set regsC100 LCR_PSB                       0x80
 307 #/* UART 16550 Divisor Latch Assess */
 308 dict set regsC100 LCR_DLAB                      0x80
 309
 310 #/* FIFO Error Status */
 311 dict set regsC100 LSR_FIFOE             [expr 1 << 7]
 312 #/* Transmitter Empty */
 313 dict set regsC100 LSR_TEMT              [expr 1 << 6]
 314 #/* Transmit Data Request */
 315 dict set regsC100 LSR_TDRQ              [expr 1 << 5]
 316 #/* Break Interrupt */
 317 dict set regsC100 LSR_BI                        [expr 1 << 4]
 318 #/* Framing Error */
 319 dict set regsC100 LSR_FE                        [expr 1 << 3]
 320 #/* Parity Error */
 321 dict set regsC100 LSR_PE                        [expr 1 << 2]
 322 #/* Overrun Error */
 323 dict set regsC100 LSR_OE                        [expr 1 << 1]
 324 #/* Data Ready */
 325 dict set regsC100 LSR_DR                        [expr 1 << 0]
 326
 327 #/* DMA Requests Enable */
 328 dict set regsC100 IER_DMAE                      [expr 1 << 7]
 329 #/* UART Unit Enable */
 330 dict set regsC100 IER_UUE                       [expr 1 << 6]
 331 #/* NRZ coding Enable */
 332 dict set regsC100 IER_NRZE                      [expr 1 << 5]
 333 #/* Receiver Time Out Interrupt Enable */
 334 dict set regsC100 IER_RTIOE                     [expr 1 << 4]
 335 #/* Modem Interrupt Enable */
 336 dict set regsC100 IER_MIE                       [expr 1 << 3]
 337 #/* Receiver Line Status Interrupt Enable */
 338 dict set regsC100 IER_RLSE                      [expr 1 << 2]
 339 #/* Transmit Data request Interrupt Enable */
 340 dict set regsC100 IER_TIE                       [expr 1 << 1]
 341 #/* Receiver Data Available Interrupt Enable */
 342 dict set regsC100 IER_RAVIE                     [expr 1 << 0]
 343
 344 #/* FIFO Mode Enable Status */
 345 dict set regsC100 IIR_FIFOES1                   [expr 1 << 7]
 346 #/* FIFO Mode Enable Status */
 347 dict set regsC100 IIR_FIFOES0                   [expr 1 << 6]
 348 #/* Time Out Detected */
 349 dict set regsC100 IIR_TOD                       [expr 1 << 3]
 350 #/* Interrupt Source Encoded */
 351 dict set regsC100 IIR_IID2                      [expr 1 << 2]
 352 #/* Interrupt Source Encoded */
 353 dict set regsC100 IIR_IID1                      [expr 1 << 1]
 354 #/* Interrupt Pending (active low) */
 355 dict set regsC100 IIR_IP                        [expr 1 << 0]
 356
 357 #/* UART 16550 FIFO Control Register */
 358 dict set regsC100 FCR_FIFOEN            0x01
 359 dict set regsC100 FCR_RCVRRES           0x02
 360 dict set regsC100 FCR_XMITRES           0x04
 361
 362 #/* Interrupt Enable Register */
 363 #// UART 16550
 364 #// Enable Received Data Available Interrupt
 365 dict set regsC100 IER_RXTH              0x01
 366 #// Enable Transmitter Empty Interrupt
 367 dict set regsC100 IER_TXTH              0x02
 368
 369
 370
 371 #////////////////////////////////////////////////////////////
 372 #// CLK  + RESET block
 373 #////////////////////////////////////////////////////////////
 374
 375 dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
 376 dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04]
 377 dict set regsC100 CLKCORE_PLL_STATUS            [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08]
 378 dict set regsC100 CLKCORE_CLKDIV_CNTRL  [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C]
 379 dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10]
 380 dict set regsC100 CLKCORE_FSYNC_CNTRL           [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14]
 381 dict set regsC100 CLKCORE_CLK_PWR_DWN           [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18]
 382 dict set regsC100 CLKCORE_RNG_CNTRL             [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C]
 383 dict set regsC100 CLKCORE_RNG_STATUS            [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20]
 384 dict set regsC100 CLKCORE_ARM_CLK_CNTRL2        [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24]
 385 dict set regsC100 CLKCORE_TDM_REF_DIV_RST       [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40]
 386
 387 dict set regsC100 ARM_PLL_BY_CTRL       0x80000000
 388 dict set regsC100 ARM_AHB_BYP           0x04000000
 389 dict set regsC100 PLL_DISABLE           0x02000000
 390 dict set regsC100 PLL_CLK_BYPASS        0x01000000
 391
 392 dict set regsC100 AHB_PLL_BY_CTRL       0x80000000
 393 dict set regsC100 DIV_BYPASS            0x40000000
 394 dict set regsC100 SYNC_MODE             0x20000000
 395
 396 dict set regsC100 EPHY_CLKDIV_BYPASS    0x00200000
 397 dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT       16
 398 dict set regsC100 PUI_CLKDIV_BYPASS     0x00004000
 399 dict set regsC100 PUI_CLKDIV_SRCCLK     0x00002000
 400 dict set regsC100 PUI_CLKDIV_RATIO_SHIFT        8
 401 dict set regsC100 PCI_CLKDIV_BYPASS     0x00000020
 402 dict set regsC100 PCI_CLKDIV_RATIO_SHIFT        0
 403
 404 dict set regsC100 ARM0_CLK_PD           0x00200000
 405 dict set regsC100 ARM1_CLK_PD           0x00100000
 406 dict set regsC100 EPHY_CLK_PD           0x00080000
 407 dict set regsC100 TDM_CLK_PD            0x00040000
 408 dict set regsC100 PUI_CLK_PD            0x00020000
 409 dict set regsC100 PCI_CLK_PD            0x00010000
 410 dict set regsC100 MDMA_AHBCLK_PD        0x00000400
 411 dict set regsC100 I2CSPI_AHBCLK_PD      0x00000200
 412 dict set regsC100 UART_AHBCLK_PD        0x00000100
 413 dict set regsC100 IPSEC_AHBCLK_PD       0x00000080
 414 dict set regsC100 TDM_AHBCLK_PD 0x00000040
 415 dict set regsC100 USB1_AHBCLK_PD        0x00000020
 416 dict set regsC100 USB0_AHBCLK_PD        0x00000010
 417 dict set regsC100 GEMAC1_AHBCLK_PD      0x00000008
 418 dict set regsC100 GEMAC0_AHBCLK_PD      0x00000004
 419 dict set regsC100 PUI_AHBCLK_PD 0x00000002
 420 dict set regsC100 HIF_AHBCLK_PD 0x00000001
 421
 422 dict set regsC100 ARM1_DIV_BP           0x00001000
 423 dict set regsC100 ARM1_DIV_VAL_SHIFT    8
 424 dict set regsC100 ARM0_DIV_BP           0x00000010
 425 dict set regsC100 ARM0_DIV_VAL_SHIFT    0
 426
 427 dict set regsC100 AHBCLK_PLL_LOCK       0x00000002
 428 dict set regsC100 FCLK_PLL_LOCK 0x00000001
 429
 430
 431 #// reset block
 432 dict set regsC100 BLOCK_RESET_REG               [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100]
 433 dict set regsC100 CSP_RESET_REG         [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104]
 434
 435 dict set regsC100 RNG_RST               0x1000
 436 dict set regsC100 IPSEC_RST             0x0800
 437 dict set regsC100 DDR_RST               0x0400
 438 dict set regsC100 USB1_PHY_RST  0x0200
 439 dict set regsC100 USB0_PHY_RST  0x0100
 440 dict set regsC100 USB1_RST              0x0080
 441 dict set regsC100 USB0_RST              0x0040
 442 dict set regsC100 GEMAC1_RST            0x0020
 443 dict set regsC100 GEMAC0_RST            0x0010
 444 dict set regsC100 TDM_RST               0x0008
 445 dict set regsC100 PUI_RST               0x0004
 446 dict set regsC100 HIF_RST               0x0002
 447 dict set regsC100 PCI_RST               0x0001
 448
 449 #////////////////////////////////////////////////////////////////
 450 #//     DDR  CONTROLLER block
 451 #////////////////////////////////////////////////////////////////
 452
 453 dict set regsC100 DDR_CONFIG_BASEADDR   0x0D000000
 454 dict set regsC100 DENALI_CTL_00_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00]
 455 dict set regsC100 DENALI_CTL_01_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08]
 456 dict set regsC100 DENALI_CTL_02_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10]
 457 dict set regsC100 DENALI_CTL_03_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18]
 458 dict set regsC100 DENALI_CTL_04_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20]
 459 dict set regsC100 DENALI_CTL_05_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28]
 460 dict set regsC100 DENALI_CTL_06_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30]
 461 dict set regsC100 DENALI_CTL_07_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38]
 462 dict set regsC100 DENALI_CTL_08_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40]
 463 dict set regsC100 DENALI_CTL_09_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48]
 464 dict set regsC100 DENALI_CTL_10_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50]
 465 dict set regsC100 DENALI_CTL_11_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58]
 466 dict set regsC100 DENALI_CTL_12_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60]
 467 dict set regsC100 DENALI_CTL_13_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68]
 468 dict set regsC100 DENALI_CTL_14_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70]
 469 dict set regsC100 DENALI_CTL_15_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78]
 470 dict set regsC100 DENALI_CTL_16_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80]
 471 dict set regsC100 DENALI_CTL_17_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88]
 472 dict set regsC100 DENALI_CTL_18_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90]
 473 dict set regsC100 DENALI_CTL_19_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98]
 474 dict set regsC100 DENALI_CTL_20_DATA    [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0]
 475
 476 # 32-bit value
 477 dict set regsC100 DENALI_READY_CHECK         [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44]
 478 # 8-bit
 479 dict set regsC100 DENALI_WR_DQS              [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D]
 480 # 8-bit
 481 dict set regsC100 DENALI_DQS_OUT             [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A]
 482 # 8-bit
 483 dict set regsC100 DENALI_DQS_DELAY0          [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F]
 484 # 8-bit
 485 dict set regsC100 DENALI_DQS_DELAY1          [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50]
 486 # 8-bit
 487 dict set regsC100 DENALI_DQS_DELAY2          [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51]
 488 # 8-bit
 489 dict set regsC100 DENALI_DQS_DELAY3          [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52]
 490
 491
 492 # end of proc regsC100
 493 }