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ARM7/9 minor cleanups
[openocd/ellerodev.git] / src / target / arm7_9_common.c
blobbaf3e45b334445174e98cd5199b4c23b5f85418c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007-2009 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * Copyright (C) 2009 by David Brownell *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
30 ***************************************************************************/
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "breakpoints.h"
36 #include "embeddedice.h"
37 #include "target_request.h"
38 #include "etm.h"
39 #include <helper/time_support.h>
40 #include "arm_simulator.h"
41 #include "arm_semihosting.h"
42 #include "algorithm.h"
43 #include "register.h"
44 #include "armv4_5.h"
45
46
47 /**
48 * @file
49 * Hold common code supporting the ARM7 and ARM9 core generations.
50 *
51 * While the ARM core implementations evolved substantially during these
52 * two generations, they look quite similar from the JTAG perspective.
53 * Both have similar debug facilities, based on the same two scan chains
54 * providing access to the core and to an EmbeddedICE module. Both can
55 * support similar ETM and ETB modules, for tracing. And both expose
56 * what could be viewed as "ARM Classic", with multiple processor modes,
57 * shadowed registers, and support for the Thumb instruction set.
58 *
59 * Processor differences include things like presence or absence of MMU
60 * and cache, pipeline sizes, use of a modified Harvard Architecure
61 * (with separate instruction and data busses from the CPU), support
62 * for cpu clock gating during idle, and more.
63 */
64
65 static int arm7_9_debug_entry(struct target *target);
66
67 /**
68 * Clear watchpoints for an ARM7/9 target.
69 *
70 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
71 * @return JTAG error status after executing queue
72 */
73 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
74 {
75 LOG_DEBUG("-");
76 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
77 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
78 arm7_9->sw_breakpoint_count = 0;
79 arm7_9->sw_breakpoints_added = 0;
80 arm7_9->wp0_used = 0;
81 arm7_9->wp1_used = arm7_9->wp1_used_default;
82 arm7_9->wp_available = arm7_9->wp_available_max;
83
84 return jtag_execute_queue();
85 }
86
87 /**
88 * Assign a watchpoint to one of the two available hardware comparators in an
89 * ARM7 or ARM9 target.
90 *
91 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
92 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
93 */
94 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
95 {
96 if (!arm7_9->wp0_used)
97 {
98 arm7_9->wp0_used = 1;
99 breakpoint->set = 1;
100 arm7_9->wp_available--;
101 }
102 else if (!arm7_9->wp1_used)
103 {
104 arm7_9->wp1_used = 1;
105 breakpoint->set = 2;
106 arm7_9->wp_available--;
107 }
108 else
109 {
110 LOG_ERROR("BUG: no hardware comparator available");
111 }
112 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
113 breakpoint->unique_id,
114 breakpoint->address,
115 breakpoint->set );
116 }
117
118 /**
119 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
120 *
121 * @param arm7_9 Pointer to common struct for ARM7/9 targets
122 * @return Error codes if there is a problem finding a watchpoint or the result
123 * of executing the JTAG queue
124 */
125 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
126 {
127 if (arm7_9->sw_breakpoints_added)
128 {
129 return ERROR_OK;
130 }
131 if (arm7_9->wp_available < 1)
132 {
133 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
135 }
136 arm7_9->wp_available--;
137
138 /* pick a breakpoint unit */
139 if (!arm7_9->wp0_used)
140 {
141 arm7_9->sw_breakpoints_added = 1;
142 arm7_9->wp0_used = 3;
143 } else if (!arm7_9->wp1_used)
144 {
145 arm7_9->sw_breakpoints_added = 2;
146 arm7_9->wp1_used = 3;
147 }
148 else
149 {
150 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
151 return ERROR_FAIL;
152 }
153
154 if (arm7_9->sw_breakpoints_added == 1)
155 {
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 }
162 else if (arm7_9->sw_breakpoints_added == 2)
163 {
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
165 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
166 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
169 }
170 else
171 {
172 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
173 return ERROR_FAIL;
174 }
175 LOG_DEBUG("SW BP using hw wp: %d",
176 arm7_9->sw_breakpoints_added );
177
178 return jtag_execute_queue();
179 }
180
181 /**
182 * Setup the common pieces for an ARM7/9 target after reset or on startup.
183 *
184 * @param target Pointer to an ARM7/9 target to setup
185 * @return Result of clearing the watchpoints on the target
186 */
187 int arm7_9_setup(struct target *target)
188 {
189 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
190
191 return arm7_9_clear_watchpoints(arm7_9);
192 }
193
194 /**
195 * Set either a hardware or software breakpoint on an ARM7/9 target. The
196 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
197 * might have erased the values in Embedded ICE.
198 *
199 * @param target Pointer to the target device to set the breakpoints on
200 * @param breakpoint Pointer to the breakpoint to be set
201 * @return For hardware breakpoints, this is the result of executing the JTAG
202 * queue. For software breakpoints, this will be the status of the
203 * required memory reads and writes
204 */
205 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
206 {
207 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
208 int retval = ERROR_OK;
209
210 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
211 breakpoint->unique_id,
212 breakpoint->address,
213 breakpoint->type);
214
215 if (target->state != TARGET_HALTED)
216 {
217 LOG_WARNING("target not halted");
218 return ERROR_TARGET_NOT_HALTED;
219 }
220
221 if (breakpoint->type == BKPT_HARD)
222 {
223 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
224 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
225
226 /* reassign a hw breakpoint */
227 if (breakpoint->set == 0)
228 {
229 arm7_9_assign_wp(arm7_9, breakpoint);
230 }
231
232 if (breakpoint->set == 1)
233 {
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
236 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
237 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
239 }
240 else if (breakpoint->set == 2)
241 {
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
243 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
244 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
246 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
247 }
248 else
249 {
250 LOG_ERROR("BUG: no hardware comparator available");
251 return ERROR_OK;
252 }
253
254 retval = jtag_execute_queue();
255 }
256 else if (breakpoint->type == BKPT_SOFT)
257 {
258 /* did we already set this breakpoint? */
259 if (breakpoint->set)
260 return ERROR_OK;
261
262 if (breakpoint->length == 4)
263 {
264 uint32_t verify = 0xffffffff;
265 /* keep the original instruction in target endianness */
266 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
267 {
268 return retval;
269 }
270 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
271 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
272 {
273 return retval;
274 }
275
276 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
277 {
278 return retval;
279 }
280 if (verify != arm7_9->arm_bkpt)
281 {
282 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
283 return ERROR_OK;
284 }
285 }
286 else
287 {
288 uint16_t verify = 0xffff;
289 /* keep the original instruction in target endianness */
290 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
291 {
292 return retval;
293 }
294 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
295 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
296 {
297 return retval;
298 }
299
300 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
301 {
302 return retval;
303 }
304 if (verify != arm7_9->thumb_bkpt)
305 {
306 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
307 return ERROR_OK;
308 }
309 }
310
311 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
312 return retval;
313
314 arm7_9->sw_breakpoint_count++;
315
316 breakpoint->set = 1;
317 }
318
319 return retval;
320 }
321
322 /**
323 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
324 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
325 * will be updated. Otherwise, the software breakpoint will be restored to its
326 * original instruction if it hasn't already been modified.
327 *
328 * @param target Pointer to ARM7/9 target to unset the breakpoint from
329 * @param breakpoint Pointer to breakpoint to be unset
330 * @return For hardware breakpoints, this is the result of executing the JTAG
331 * queue. For software breakpoints, this will be the status of the
332 * required memory reads and writes
333 */
334 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
335 {
336 int retval = ERROR_OK;
337 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
338
339 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
340 breakpoint->unique_id,
341 breakpoint->address );
342
343 if (!breakpoint->set)
344 {
345 LOG_WARNING("breakpoint not set");
346 return ERROR_OK;
347 }
348
349 if (breakpoint->type == BKPT_HARD)
350 {
351 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
352 breakpoint->unique_id,
353 breakpoint->set );
354 if (breakpoint->set == 1)
355 {
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
357 arm7_9->wp0_used = 0;
358 arm7_9->wp_available++;
359 }
360 else if (breakpoint->set == 2)
361 {
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
363 arm7_9->wp1_used = 0;
364 arm7_9->wp_available++;
365 }
366 retval = jtag_execute_queue();
367 breakpoint->set = 0;
368 }
369 else
370 {
371 /* restore original instruction (kept in target endianness) */
372 if (breakpoint->length == 4)
373 {
374 uint32_t current_instr;
375 /* check that user program as not modified breakpoint instruction */
376 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
377 {
378 return retval;
379 }
380 if (current_instr == arm7_9->arm_bkpt)
381 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
382 {
383 return retval;
384 }
385 }
386 else
387 {
388 uint16_t current_instr;
389 /* check that user program as not modified breakpoint instruction */
390 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
391 {
392 return retval;
393 }
394 if (current_instr == arm7_9->thumb_bkpt)
395 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
396 {
397 return retval;
398 }
399 }
400
401 if (--arm7_9->sw_breakpoint_count==0)
402 {
403 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
404 if (arm7_9->sw_breakpoints_added == 1)
405 {
406 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
407 }
408 else if (arm7_9->sw_breakpoints_added == 2)
409 {
410 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
411 }
412 }
413
414 breakpoint->set = 0;
415 }
416
417 return retval;
418 }
419
420 /**
421 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
422 * dangling breakpoints and that the desired breakpoint can be added.
423 *
424 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
425 * @param breakpoint Pointer to the breakpoint to be added
426 * @return An error status if there is a problem adding the breakpoint or the
427 * result of setting the breakpoint
428 */
429 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
430 {
431 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
432
433 if (arm7_9->breakpoint_count == 0)
434 {
435 /* make sure we don't have any dangling breakpoints. This is vital upon
436 * GDB connect/disconnect
437 */
438 arm7_9_clear_watchpoints(arm7_9);
439 }
440
441 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
442 {
443 LOG_INFO("no watchpoint unit available for hardware breakpoint");
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
445 }
446
447 if ((breakpoint->length != 2) && (breakpoint->length != 4))
448 {
449 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
450 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
451 }
452
453 if (breakpoint->type == BKPT_HARD)
454 {
455 arm7_9_assign_wp(arm7_9, breakpoint);
456 }
457
458 arm7_9->breakpoint_count++;
459
460 return arm7_9_set_breakpoint(target, breakpoint);
461 }
462
463 /**
464 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
465 * dangling breakpoints and updates available watchpoints if it is a hardware
466 * breakpoint.
467 *
468 * @param target Pointer to the target to have a breakpoint removed
469 * @param breakpoint Pointer to the breakpoint to be removed
470 * @return Error status if there was a problem unsetting the breakpoint or the
471 * watchpoints could not be cleared
472 */
473 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
474 {
475 int retval = ERROR_OK;
476 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
477
478 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
479 {
480 return retval;
481 }
482
483 if (breakpoint->type == BKPT_HARD)
484 arm7_9->wp_available++;
485
486 arm7_9->breakpoint_count--;
487 if (arm7_9->breakpoint_count == 0)
488 {
489 /* make sure we don't have any dangling breakpoints */
490 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
491 {
492 return retval;
493 }
494 }
495
496 return ERROR_OK;
497 }
498
499 /**
500 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
501 * considered a bug to call this function when there are no available watchpoint
502 * units.
503 *
504 * @param target Pointer to an ARM7/9 target to set a watchpoint on
505 * @param watchpoint Pointer to the watchpoint to be set
506 * @return Error status if watchpoint set fails or the result of executing the
507 * JTAG queue
508 */
509 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
510 {
511 int retval = ERROR_OK;
512 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
513 int rw_mask = 1;
514 uint32_t mask;
515
516 mask = watchpoint->length - 1;
517
518 if (target->state != TARGET_HALTED)
519 {
520 LOG_WARNING("target not halted");
521 return ERROR_TARGET_NOT_HALTED;
522 }
523
524 if (watchpoint->rw == WPT_ACCESS)
525 rw_mask = 0;
526 else
527 rw_mask = 1;
528
529 if (!arm7_9->wp0_used)
530 {
531 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
532 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
534 if (watchpoint->mask != 0xffffffffu)
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
536 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
538
539 if ((retval = jtag_execute_queue()) != ERROR_OK)
540 {
541 return retval;
542 }
543 watchpoint->set = 1;
544 arm7_9->wp0_used = 2;
545 }
546 else if (!arm7_9->wp1_used)
547 {
548 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
549 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
551 if (watchpoint->mask != 0xffffffffu)
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
553 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
555
556 if ((retval = jtag_execute_queue()) != ERROR_OK)
557 {
558 return retval;
559 }
560 watchpoint->set = 2;
561 arm7_9->wp1_used = 2;
562 }
563 else
564 {
565 LOG_ERROR("BUG: no hardware comparator available");
566 return ERROR_OK;
567 }
568
569 return ERROR_OK;
570 }
571
572 /**
573 * Unset an existing watchpoint and clear the used watchpoint unit.
574 *
575 * @param target Pointer to the target to have the watchpoint removed
576 * @param watchpoint Pointer to the watchpoint to be removed
577 * @return Error status while trying to unset the watchpoint or the result of
578 * executing the JTAG queue
579 */
580 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
581 {
582 int retval = ERROR_OK;
583 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
584
585 if (target->state != TARGET_HALTED)
586 {
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED;
589 }
590
591 if (!watchpoint->set)
592 {
593 LOG_WARNING("breakpoint not set");
594 return ERROR_OK;
595 }
596
597 if (watchpoint->set == 1)
598 {
599 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
600 if ((retval = jtag_execute_queue()) != ERROR_OK)
601 {
602 return retval;
603 }
604 arm7_9->wp0_used = 0;
605 }
606 else if (watchpoint->set == 2)
607 {
608 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
609 if ((retval = jtag_execute_queue()) != ERROR_OK)
610 {
611 return retval;
612 }
613 arm7_9->wp1_used = 0;
614 }
615 watchpoint->set = 0;
616
617 return ERROR_OK;
618 }
619
620 /**
621 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
622 * available, an error response is returned.
623 *
624 * @param target Pointer to the ARM7/9 target to add a watchpoint to
625 * @param watchpoint Pointer to the watchpoint to be added
626 * @return Error status while trying to add the watchpoint
627 */
628 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
629 {
630 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
631
632 if (arm7_9->wp_available < 1)
633 {
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
635 }
636
637 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
638 {
639 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
640 }
641
642 arm7_9->wp_available--;
643
644 return ERROR_OK;
645 }
646
647 /**
648 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
649 * the used watchpoint unit will be reopened.
650 *
651 * @param target Pointer to the target to remove a watchpoint from
652 * @param watchpoint Pointer to the watchpoint to be removed
653 * @return Result of trying to unset the watchpoint
654 */
655 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
656 {
657 int retval = ERROR_OK;
658 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
659
660 if (watchpoint->set)
661 {
662 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
663 {
664 return retval;
665 }
666 }
667
668 arm7_9->wp_available++;
669
670 return ERROR_OK;
671 }
672
673 /**
674 * Restarts the target by sending a RESTART instruction and moving the JTAG
675 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
676 * asserted by the processor.
677 *
678 * @param target Pointer to target to issue commands to
679 * @return Error status if there is a timeout or a problem while executing the
680 * JTAG queue
681 */
682 int arm7_9_execute_sys_speed(struct target *target)
683 {
684 int retval;
685 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
686 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
687 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
688
689 /* set RESTART instruction */
690 jtag_set_end_state(TAP_IDLE);
691 if (arm7_9->need_bypass_before_restart) {
692 arm7_9->need_bypass_before_restart = 0;
693 arm_jtag_set_instr(jtag_info, 0xf, NULL);
694 }
695 arm_jtag_set_instr(jtag_info, 0x4, NULL);
696
697 long long then = timeval_ms();
698 int timeout;
699 while (!(timeout = ((timeval_ms()-then) > 1000)))
700 {
701 /* read debug status register */
702 embeddedice_read_reg(dbg_stat);
703 if ((retval = jtag_execute_queue()) != ERROR_OK)
704 return retval;
705 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
706 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
707 break;
708 if (debug_level >= 3)
709 {
710 alive_sleep(100);
711 } else
712 {
713 keep_alive();
714 }
715 }
716 if (timeout)
717 {
718 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
719 return ERROR_TARGET_TIMEOUT;
720 }
721
722 return ERROR_OK;
723 }
724
725 /**
726 * Restarts the target by sending a RESTART instruction and moving the JTAG
727 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
728 * waiting until they are.
729 *
730 * @param target Pointer to the target to issue commands to
731 * @return Always ERROR_OK
732 */
733 int arm7_9_execute_fast_sys_speed(struct target *target)
734 {
735 static int set = 0;
736 static uint8_t check_value[4], check_mask[4];
737
738 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
739 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
740 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
741
742 /* set RESTART instruction */
743 jtag_set_end_state(TAP_IDLE);
744 if (arm7_9->need_bypass_before_restart) {
745 arm7_9->need_bypass_before_restart = 0;
746 arm_jtag_set_instr(jtag_info, 0xf, NULL);
747 }
748 arm_jtag_set_instr(jtag_info, 0x4, NULL);
749
750 if (!set)
751 {
752 /* check for DBGACK and SYSCOMP set (others don't care) */
753
754 /* NB! These are constants that must be available until after next jtag_execute() and
755 * we evaluate the values upon first execution in lieu of setting up these constants
756 * during early setup.
757 * */
758 buf_set_u32(check_value, 0, 32, 0x9);
759 buf_set_u32(check_mask, 0, 32, 0x9);
760 set = 1;
761 }
762
763 /* read debug status register */
764 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
765
766 return ERROR_OK;
767 }
768
769 /**
770 * Get some data from the ARM7/9 target.
771 *
772 * @param target Pointer to the ARM7/9 target to read data from
773 * @param size The number of 32bit words to be read
774 * @param buffer Pointer to the buffer that will hold the data
775 * @return The result of receiving data from the Embedded ICE unit
776 */
777 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
778 {
779 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
780 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
781 uint32_t *data;
782 int retval = ERROR_OK;
783 uint32_t i;
784
785 data = malloc(size * (sizeof(uint32_t)));
786
787 retval = embeddedice_receive(jtag_info, data, size);
788
789 /* return the 32-bit ints in the 8-bit array */
790 for (i = 0; i < size; i++)
791 {
792 h_u32_to_le(buffer + (i * 4), data[i]);
793 }
794
795 free(data);
796
797 return retval;
798 }
799
800 /**
801 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
802 * target is running and the DCC control register has the W bit high, this will
803 * execute the request on the target.
804 *
805 * @param priv Void pointer expected to be a struct target pointer
806 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
807 * from the Embedded ICE unit
808 */
809 int arm7_9_handle_target_request(void *priv)
810 {
811 int retval = ERROR_OK;
812 struct target *target = priv;
813 if (!target_was_examined(target))
814 return ERROR_OK;
815 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
816 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
817 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
818
819 if (!target->dbg_msg_enabled)
820 return ERROR_OK;
821
822 if (target->state == TARGET_RUNNING)
823 {
824 /* read DCC control register */
825 embeddedice_read_reg(dcc_control);
826 if ((retval = jtag_execute_queue()) != ERROR_OK)
827 {
828 return retval;
829 }
830
831 /* check W bit */
832 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
833 {
834 uint32_t request;
835
836 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
837 {
838 return retval;
839 }
840 if ((retval = target_request(target, request)) != ERROR_OK)
841 {
842 return retval;
843 }
844 }
845 }
846
847 return ERROR_OK;
848 }
849
850 /**
851 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
852 * is manipulated to the right halted state based on its current state. This is
853 * what happens:
854 *
855 * <table>
856 * <tr><th > State</th><th > Action</th></tr>
857 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
858 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
859 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
860 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
861 * </table>
862 *
863 * If the target does not end up in the halted state, a warning is produced. If
864 * DBGACK is cleared, then the target is expected to either be running or
865 * running in debug.
866 *
867 * @param target Pointer to the ARM7/9 target to poll
868 * @return ERROR_OK or an error status if a command fails
869 */
870 int arm7_9_poll(struct target *target)
871 {
872 int retval;
873 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
874 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
875
876 /* read debug status register */
877 embeddedice_read_reg(dbg_stat);
878 if ((retval = jtag_execute_queue()) != ERROR_OK)
879 {
880 return retval;
881 }
882
883 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
884 {
885 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
886 if (target->state == TARGET_UNKNOWN)
887 {
888 /* Starting OpenOCD with target in debug-halt */
889 target->state = TARGET_RUNNING;
890 LOG_DEBUG("DBGACK already set during server startup.");
891 }
892 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
893 {
894 target->state = TARGET_HALTED;
895
896 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
897 return retval;
898
899 if (arm_semihosting(target, &retval) != 0)
900 return retval;
901
902 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
903 {
904 return retval;
905 }
906 }
907 if (target->state == TARGET_DEBUG_RUNNING)
908 {
909 target->state = TARGET_HALTED;
910 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
911 return retval;
912
913 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
914 {
915 return retval;
916 }
917 }
918 if (target->state != TARGET_HALTED)
919 {
920 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
921 }
922 }
923 else
924 {
925 if (target->state != TARGET_DEBUG_RUNNING)
926 target->state = TARGET_RUNNING;
927 }
928
929 return ERROR_OK;
930 }
931
932 /**
933 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
934 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
935 * affected) completely stop the JTAG clock while the core is held in reset
936 * (SRST). It isn't possible to program the halt condition once reset is
937 * asserted, hence a hook that allows the target to set up its reset-halt
938 * condition is setup prior to asserting reset.
939 *
940 * @param target Pointer to an ARM7/9 target to assert reset on
941 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
942 */
943 int arm7_9_assert_reset(struct target *target)
944 {
945 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
946 enum reset_types jtag_reset_config = jtag_get_reset_config();
947
948 LOG_DEBUG("target->state: %s",
949 target_state_name(target));
950
951 if (!(jtag_reset_config & RESET_HAS_SRST))
952 {
953 LOG_ERROR("Can't assert SRST");
954 return ERROR_FAIL;
955 }
956
957 /* At this point trst has been asserted/deasserted once. We would
958 * like to program EmbeddedICE while SRST is asserted, instead of
959 * depending on SRST to leave that module alone. However, many CPUs
960 * gate the JTAG clock while SRST is asserted; or JTAG may need
961 * clock stability guarantees (adaptive clocking might help).
962 *
963 * So we assume JTAG access during SRST is off the menu unless it's
964 * been specifically enabled.
965 */
966 bool srst_asserted = false;
967
968 if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
969 && (jtag_reset_config & RESET_SRST_NO_GATING))
970 {
971 jtag_add_reset(0, 1);
972 srst_asserted = true;
973 }
974
975 if (target->reset_halt)
976 {
977 /*
978 * For targets that don't support communication while SRST is
979 * asserted, we need to set up the reset vector catch first.
980 *
981 * When we use TRST+SRST and that's equivalent to a power-up
982 * reset, these settings may well be reset anyway; so setting
983 * them here won't matter.
984 */
985 if (arm7_9->has_vector_catch)
986 {
987 /* program vector catch register to catch reset */
988 embeddedice_write_reg(&arm7_9->eice_cache
989 ->reg_list[EICE_VEC_CATCH], 0x1);
990
991 /* extra runtest added as issues were found with
992 * certain ARM9 cores (maybe more) - AT91SAM9260
993 * and STR9
994 */
995 jtag_add_runtest(1, jtag_get_end_state());
996 }
997 else
998 {
999 /* program watchpoint unit to match on reset vector
1000 * address
1001 */
1002 embeddedice_write_reg(&arm7_9->eice_cache
1003 ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1004 embeddedice_write_reg(&arm7_9->eice_cache
1005 ->reg_list[EICE_W0_ADDR_MASK], 0x3);
1006 embeddedice_write_reg(&arm7_9->eice_cache
1007 ->reg_list[EICE_W0_DATA_MASK],
1008 0xffffffff);
1009 embeddedice_write_reg(&arm7_9->eice_cache
1010 ->reg_list[EICE_W0_CONTROL_VALUE],
1011 EICE_W_CTRL_ENABLE);
1012 embeddedice_write_reg(&arm7_9->eice_cache
1013 ->reg_list[EICE_W0_CONTROL_MASK],
1014 ~EICE_W_CTRL_nOPC & 0xff);
1015 }
1016 }
1017
1018 /* here we should issue an SRST only, but we may have to assert TRST as well */
1019 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1020 {
1021 jtag_add_reset(1, 1);
1022 } else if (!srst_asserted)
1023 {
1024 jtag_add_reset(0, 1);
1025 }
1026
1027 target->state = TARGET_RESET;
1028 jtag_add_sleep(50000);
1029
1030 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1031
1032 if (target->reset_halt
1033 && !(jtag_reset_config & RESET_SRST_PULLS_TRST))
1034 {
1035 /* debug entry was prepared above */
1036 target->debug_reason = DBG_REASON_DBGRQ;
1037 }
1038
1039 return ERROR_OK;
1040 }
1041
1042 /**
1043 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1044 * and the target is being reset into a halt, a warning will be triggered
1045 * because it is not possible to reset into a halted mode in this case. The
1046 * target is halted using the target's functions.
1047 *
1048 * @param target Pointer to the target to have the reset deasserted
1049 * @return ERROR_OK or an error from polling or halting the target
1050 */
1051 int arm7_9_deassert_reset(struct target *target)
1052 {
1053 int retval = ERROR_OK;
1054 LOG_DEBUG("target->state: %s",
1055 target_state_name(target));
1056
1057 /* deassert reset lines */
1058 jtag_add_reset(0, 0);
1059
1060 enum reset_types jtag_reset_config = jtag_get_reset_config();
1061 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1062 {
1063 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1064 /* set up embedded ice registers again */
1065 if ((retval = target_examine_one(target)) != ERROR_OK)
1066 return retval;
1067
1068 if ((retval = target_poll(target)) != ERROR_OK)
1069 {
1070 return retval;
1071 }
1072
1073 if ((retval = target_halt(target)) != ERROR_OK)
1074 {
1075 return retval;
1076 }
1077
1078 }
1079 return retval;
1080 }
1081
1082 /**
1083 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1084 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1085 * vector catch was used, it is restored. Otherwise, the control value is
1086 * restored and the watchpoint unit is restored if it was in use.
1087 *
1088 * @param target Pointer to the ARM7/9 target to have halt cleared
1089 * @return Always ERROR_OK
1090 */
1091 int arm7_9_clear_halt(struct target *target)
1092 {
1093 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1094 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1095
1096 /* we used DBGRQ only if we didn't come out of reset */
1097 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1098 {
1099 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1100 */
1101 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1102 embeddedice_store_reg(dbg_ctrl);
1103 }
1104 else
1105 {
1106 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1107 {
1108 /* if we came out of reset, and vector catch is supported, we used
1109 * vector catch to enter debug state
1110 * restore the register in that case
1111 */
1112 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1113 }
1114 else
1115 {
1116 /* restore registers if watchpoint unit 0 was in use
1117 */
1118 if (arm7_9->wp0_used)
1119 {
1120 if (arm7_9->debug_entry_from_reset)
1121 {
1122 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1123 }
1124 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1125 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1126 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1127 }
1128 /* control value always has to be restored, as it was either disabled,
1129 * or enabled with possibly different bits
1130 */
1131 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1132 }
1133 }
1134
1135 return ERROR_OK;
1136 }
1137
1138 /**
1139 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1140 * and then there is a wait until the processor shows the halt. This wait can
1141 * timeout and results in an error being returned. The software reset involves
1142 * clearing the halt, updating the debug control register, changing to ARM mode,
1143 * reset of the program counter, and reset of all of the registers.
1144 *
1145 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1146 * @return Error status if any of the commands fail, otherwise ERROR_OK
1147 */
1148 int arm7_9_soft_reset_halt(struct target *target)
1149 {
1150 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1151 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1152 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1153 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1154 int i;
1155 int retval;
1156
1157 /* FIX!!! replace some of this code with tcl commands
1158 *
1159 * halt # the halt command is synchronous
1160 * armv4_5 core_state arm
1161 *
1162 */
1163
1164 if ((retval = target_halt(target)) != ERROR_OK)
1165 return retval;
1166
1167 long long then = timeval_ms();
1168 int timeout;
1169 while (!(timeout = ((timeval_ms()-then) > 1000)))
1170 {
1171 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1172 break;
1173 embeddedice_read_reg(dbg_stat);
1174 if ((retval = jtag_execute_queue()) != ERROR_OK)
1175 return retval;
1176 if (debug_level >= 3)
1177 {
1178 alive_sleep(100);
1179 } else
1180 {
1181 keep_alive();
1182 }
1183 }
1184 if (timeout)
1185 {
1186 LOG_ERROR("Failed to halt CPU after 1 sec");
1187 return ERROR_TARGET_TIMEOUT;
1188 }
1189 target->state = TARGET_HALTED;
1190
1191 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1192 * ensure that DBGRQ is cleared
1193 */
1194 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1195 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1196 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1197 embeddedice_store_reg(dbg_ctrl);
1198
1199 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1200 {
1201 return retval;
1202 }
1203
1204 /* if the target is in Thumb state, change to ARM state */
1205 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1206 {
1207 uint32_t r0_thumb, pc_thumb;
1208 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1209 /* Entered debug from Thumb mode */
1210 armv4_5->core_state = ARM_STATE_THUMB;
1211 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1212 }
1213
1214 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1215
1216 /* all register content is now invalid */
1217 register_cache_invalidate(armv4_5->core_cache);
1218
1219 /* SVC, ARM state, IRQ and FIQ disabled */
1220 uint32_t cpsr;
1221
1222 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1223 cpsr &= ~0xff;
1224 cpsr |= 0xd3;
1225 arm_set_cpsr(armv4_5, cpsr);
1226 armv4_5->cpsr->dirty = 1;
1227
1228 /* start fetching from 0x0 */
1229 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1230 armv4_5->core_cache->reg_list[15].dirty = 1;
1231 armv4_5->core_cache->reg_list[15].valid = 1;
1232
1233 /* reset registers */
1234 for (i = 0; i <= 14; i++)
1235 {
1236 struct reg *r = arm_reg_current(armv4_5, i);
1237
1238 buf_set_u32(r->value, 0, 32, 0xffffffff);
1239 r->dirty = 1;
1240 r->valid = 1;
1241 }
1242
1243 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1244 {
1245 return retval;
1246 }
1247
1248 return ERROR_OK;
1249 }
1250
1251 /**
1252 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1253 * line or by programming a watchpoint to trigger on any address. It is
1254 * considered a bug to call this function while the target is in the
1255 * TARGET_RESET state.
1256 *
1257 * @param target Pointer to the ARM7/9 target to be halted
1258 * @return Always ERROR_OK
1259 */
1260 int arm7_9_halt(struct target *target)
1261 {
1262 if (target->state == TARGET_RESET)
1263 {
1264 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1265 return ERROR_OK;
1266 }
1267
1268 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1269 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1270
1271 LOG_DEBUG("target->state: %s",
1272 target_state_name(target));
1273
1274 if (target->state == TARGET_HALTED)
1275 {
1276 LOG_DEBUG("target was already halted");
1277 return ERROR_OK;
1278 }
1279
1280 if (target->state == TARGET_UNKNOWN)
1281 {
1282 LOG_WARNING("target was in unknown state when halt was requested");
1283 }
1284
1285 if (arm7_9->use_dbgrq)
1286 {
1287 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1288 */
1289 if (arm7_9->set_special_dbgrq) {
1290 arm7_9->set_special_dbgrq(target);
1291 } else {
1292 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1293 embeddedice_store_reg(dbg_ctrl);
1294 }
1295 }
1296 else
1297 {
1298 /* program watchpoint unit to match on any address
1299 */
1300 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1301 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1302 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1303 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1304 }
1305
1306 target->debug_reason = DBG_REASON_DBGRQ;
1307
1308 return ERROR_OK;
1309 }
1310
1311 /**
1312 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1313 * ARM. The JTAG queue is then executed and the reason for debug entry is
1314 * examined. Once done, the target is verified to be halted and the processor
1315 * is forced into ARM mode. The core registers are saved for the current core
1316 * mode and the program counter (register 15) is updated as needed. The core
1317 * registers and CPSR and SPSR are saved for restoration later.
1318 *
1319 * @param target Pointer to target that is entering debug mode
1320 * @return Error code if anything fails, otherwise ERROR_OK
1321 */
1322 static int arm7_9_debug_entry(struct target *target)
1323 {
1324 int i;
1325 uint32_t context[16];
1326 uint32_t* context_p[16];
1327 uint32_t r0_thumb, pc_thumb;
1328 uint32_t cpsr, cpsr_mask = 0;
1329 int retval;
1330 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1331 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1332 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1333 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1334
1335 #ifdef _DEBUG_ARM7_9_
1336 LOG_DEBUG("-");
1337 #endif
1338
1339 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1340 * ensure that DBGRQ is cleared
1341 */
1342 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1343 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1344 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1345 embeddedice_store_reg(dbg_ctrl);
1346
1347 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1348 {
1349 return retval;
1350 }
1351
1352 if ((retval = jtag_execute_queue()) != ERROR_OK)
1353 {
1354 return retval;
1355 }
1356
1357 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1358 return retval;
1359
1360
1361 if (target->state != TARGET_HALTED)
1362 {
1363 LOG_WARNING("target not halted");
1364 return ERROR_TARGET_NOT_HALTED;
1365 }
1366
1367 /* if the target is in Thumb state, change to ARM state */
1368 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1369 {
1370 LOG_DEBUG("target entered debug from Thumb state");
1371 /* Entered debug from Thumb mode */
1372 armv4_5->core_state = ARM_STATE_THUMB;
1373 cpsr_mask = 1 << 5;
1374 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1375 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1376 ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1377 } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1378 /* \todo Get some vaguely correct handling of Jazelle, if
1379 * anyone ever uses it and full info becomes available.
1380 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1381 * B.7.3 for the reverse. That'd be the bare minimum...
1382 */
1383 LOG_DEBUG("target entered debug from Jazelle state");
1384 armv4_5->core_state = ARM_STATE_JAZELLE;
1385 cpsr_mask = 1 << 24;
1386 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1387 } else {
1388 LOG_DEBUG("target entered debug from ARM state");
1389 /* Entered debug from ARM mode */
1390 armv4_5->core_state = ARM_STATE_ARM;
1391 }
1392
1393 for (i = 0; i < 16; i++)
1394 context_p[i] = &context[i];
1395 /* save core registers (r0 - r15 of current core mode) */
1396 arm7_9->read_core_regs(target, 0xffff, context_p);
1397
1398 arm7_9->read_xpsr(target, &cpsr, 0);
1399
1400 if ((retval = jtag_execute_queue()) != ERROR_OK)
1401 return retval;
1402
1403 /* Sync our CPSR copy with J or T bits EICE reported, but
1404 * which we then erased by putting the core into ARM mode.
1405 */
1406 arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
1407
1408 if (!is_arm_mode(armv4_5->core_mode))
1409 {
1410 target->state = TARGET_UNKNOWN;
1411 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1412 return ERROR_TARGET_FAILURE;
1413 }
1414
1415 LOG_DEBUG("target entered debug state in %s mode",
1416 arm_mode_name(armv4_5->core_mode));
1417
1418 if (armv4_5->core_state == ARM_STATE_THUMB)
1419 {
1420 LOG_DEBUG("thumb state, applying fixups");
1421 context[0] = r0_thumb;
1422 context[15] = pc_thumb;
1423 } else if (armv4_5->core_state == ARM_STATE_ARM)
1424 {
1425 /* adjust value stored by STM */
1426 context[15] -= 3 * 4;
1427 }
1428
1429 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1430 context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1431 else
1432 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1433
1434 for (i = 0; i <= 15; i++)
1435 {
1436 struct reg *r = arm_reg_current(armv4_5, i);
1437
1438 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1439
1440 buf_set_u32(r->value, 0, 32, context[i]);
1441 /* r0 and r15 (pc) have to be restored later */
1442 r->dirty = (i == 0) || (i == 15);
1443 r->valid = 1;
1444 }
1445
1446 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1447
1448 /* exceptions other than USR & SYS have a saved program status register */
1449 if (armv4_5->spsr) {
1450 uint32_t spsr;
1451 arm7_9->read_xpsr(target, &spsr, 1);
1452 if ((retval = jtag_execute_queue()) != ERROR_OK)
1453 {
1454 return retval;
1455 }
1456 buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
1457 armv4_5->spsr->dirty = 0;
1458 armv4_5->spsr->valid = 1;
1459 }
1460
1461 if ((retval = jtag_execute_queue()) != ERROR_OK)
1462 return retval;
1463
1464 if (arm7_9->post_debug_entry)
1465 arm7_9->post_debug_entry(target);
1466
1467 return ERROR_OK;
1468 }
1469
1470 /**
1471 * Validate the full context for an ARM7/9 target in all processor modes. If
1472 * there are any invalid registers for the target, they will all be read. This
1473 * includes the PSR.
1474 *
1475 * @param target Pointer to the ARM7/9 target to capture the full context from
1476 * @return Error if the target is not halted, has an invalid core mode, or if
1477 * the JTAG queue fails to execute
1478 */
1479 int arm7_9_full_context(struct target *target)
1480 {
1481 int i;
1482 int retval;
1483 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1484 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1485
1486 LOG_DEBUG("-");
1487
1488 if (target->state != TARGET_HALTED)
1489 {
1490 LOG_WARNING("target not halted");
1491 return ERROR_TARGET_NOT_HALTED;
1492 }
1493
1494 if (!is_arm_mode(armv4_5->core_mode))
1495 return ERROR_FAIL;
1496
1497 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1498 * SYS shares registers with User, so we don't touch SYS
1499 */
1500 for (i = 0; i < 6; i++)
1501 {
1502 uint32_t mask = 0;
1503 uint32_t* reg_p[16];
1504 int j;
1505 int valid = 1;
1506
1507 /* check if there are invalid registers in the current mode
1508 */
1509 for (j = 0; j <= 16; j++)
1510 {
1511 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1512 valid = 0;
1513 }
1514
1515 if (!valid)
1516 {
1517 uint32_t tmp_cpsr;
1518
1519 /* change processor mode (and mask T bit) */
1520 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1521 & 0xe0;
1522 tmp_cpsr |= armv4_5_number_to_mode(i);
1523 tmp_cpsr &= ~0x20;
1524 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1525
1526 for (j = 0; j < 15; j++)
1527 {
1528 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1529 {
1530 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1531 mask |= 1 << j;
1532 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1533 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1534 }
1535 }
1536
1537 /* if only the PSR is invalid, mask is all zeroes */
1538 if (mask)
1539 arm7_9->read_core_regs(target, mask, reg_p);
1540
1541 /* check if the PSR has to be read */
1542 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1543 {
1544 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1545 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1546 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1547 }
1548 }
1549 }
1550
1551 /* restore processor mode (mask T bit) */
1552 arm7_9->write_xpsr_im8(target,
1553 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1554 0, 0);
1555
1556 if ((retval = jtag_execute_queue()) != ERROR_OK)
1557 {
1558 return retval;
1559 }
1560 return ERROR_OK;
1561 }
1562
1563 /**
1564 * Restore the processor context on an ARM7/9 target. The full processor
1565 * context is analyzed to see if any of the registers are dirty on this end, but
1566 * have a valid new value. If this is the case, the processor is changed to the
1567 * appropriate mode and the new register values are written out to the
1568 * processor. If there happens to be a dirty register with an invalid value, an
1569 * error will be logged.
1570 *
1571 * @param target Pointer to the ARM7/9 target to have its context restored
1572 * @return Error status if the target is not halted or the core mode in the
1573 * armv4_5 struct is invalid.
1574 */
1575 int arm7_9_restore_context(struct target *target)
1576 {
1577 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1578 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1579 struct reg *reg;
1580 struct arm_reg *reg_arch_info;
1581 enum arm_mode current_mode = armv4_5->core_mode;
1582 int i, j;
1583 int dirty;
1584 int mode_change;
1585
1586 LOG_DEBUG("-");
1587
1588 if (target->state != TARGET_HALTED)
1589 {
1590 LOG_WARNING("target not halted");
1591 return ERROR_TARGET_NOT_HALTED;
1592 }
1593
1594 if (arm7_9->pre_restore_context)
1595 arm7_9->pre_restore_context(target);
1596
1597 if (!is_arm_mode(armv4_5->core_mode))
1598 return ERROR_FAIL;
1599
1600 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1601 * SYS shares registers with User, so we don't touch SYS
1602 */
1603 for (i = 0; i < 6; i++)
1604 {
1605 LOG_DEBUG("examining %s mode",
1606 arm_mode_name(armv4_5->core_mode));
1607 dirty = 0;
1608 mode_change = 0;
1609 /* check if there are dirty registers in the current mode
1610 */
1611 for (j = 0; j <= 16; j++)
1612 {
1613 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1614 reg_arch_info = reg->arch_info;
1615 if (reg->dirty == 1)
1616 {
1617 if (reg->valid == 1)
1618 {
1619 dirty = 1;
1620 LOG_DEBUG("examining dirty reg: %s", reg->name);
1621 if ((reg_arch_info->mode != ARM_MODE_ANY)
1622 && (reg_arch_info->mode != current_mode)
1623 && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
1624 && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
1625 {
1626 mode_change = 1;
1627 LOG_DEBUG("require mode change");
1628 }
1629 }
1630 else
1631 {
1632 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1633 }
1634 }
1635 }
1636
1637 if (dirty)
1638 {
1639 uint32_t mask = 0x0;
1640 int num_regs = 0;
1641 uint32_t regs[16];
1642
1643 if (mode_change)
1644 {
1645 uint32_t tmp_cpsr;
1646
1647 /* change processor mode (mask T bit) */
1648 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1649 0, 8) & 0xe0;
1650 tmp_cpsr |= armv4_5_number_to_mode(i);
1651 tmp_cpsr &= ~0x20;
1652 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1653 current_mode = armv4_5_number_to_mode(i);
1654 }
1655
1656 for (j = 0; j <= 14; j++)
1657 {
1658 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1659 reg_arch_info = reg->arch_info;
1660
1661
1662 if (reg->dirty == 1)
1663 {
1664 regs[j] = buf_get_u32(reg->value, 0, 32);
1665 mask |= 1 << j;
1666 num_regs++;
1667 reg->dirty = 0;
1668 reg->valid = 1;
1669 LOG_DEBUG("writing register %i mode %s "
1670 "with value 0x%8.8" PRIx32, j,
1671 arm_mode_name(armv4_5->core_mode),
1672 regs[j]);
1673 }
1674 }
1675
1676 if (mask)
1677 {
1678 arm7_9->write_core_regs(target, mask, regs);
1679 }
1680
1681 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1682 reg_arch_info = reg->arch_info;
1683 if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
1684 {
1685 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1686 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1687 }
1688 }
1689 }
1690
1691 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1692 {
1693 /* restore processor mode (mask T bit) */
1694 uint32_t tmp_cpsr;
1695
1696 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1697 tmp_cpsr |= armv4_5_number_to_mode(i);
1698 tmp_cpsr &= ~0x20;
1699 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1700 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1701 }
1702 else if (armv4_5->cpsr->dirty)
1703 {
1704 /* CPSR has been changed, full restore necessary (mask T bit) */
1705 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1706 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1707 arm7_9->write_xpsr(target,
1708 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1709 & ~0x20, 0);
1710 armv4_5->cpsr->dirty = 0;
1711 armv4_5->cpsr->valid = 1;
1712 }
1713
1714 /* restore PC */
1715 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1716 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1717 armv4_5->core_cache->reg_list[15].dirty = 0;
1718
1719 if (arm7_9->post_restore_context)
1720 arm7_9->post_restore_context(target);
1721
1722 return ERROR_OK;
1723 }
1724
1725 /**
1726 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1727 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1728 * restart.
1729 *
1730 * @param target Pointer to the ARM7/9 target to be restarted
1731 * @return Result of executing the JTAG queue
1732 */
1733 int arm7_9_restart_core(struct target *target)
1734 {
1735 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1736 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1737
1738 /* set RESTART instruction */
1739 jtag_set_end_state(TAP_IDLE);
1740 if (arm7_9->need_bypass_before_restart) {
1741 arm7_9->need_bypass_before_restart = 0;
1742 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1743 }
1744 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1745
1746 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1747 return jtag_execute_queue();
1748 }
1749
1750 /**
1751 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1752 * iterated through and are set on the target if they aren't already set.
1753 *
1754 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1755 */
1756 void arm7_9_enable_watchpoints(struct target *target)
1757 {
1758 struct watchpoint *watchpoint = target->watchpoints;
1759
1760 while (watchpoint)
1761 {
1762 if (watchpoint->set == 0)
1763 arm7_9_set_watchpoint(target, watchpoint);
1764 watchpoint = watchpoint->next;
1765 }
1766 }
1767
1768 /**
1769 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1770 * iterated through and are set on the target.
1771 *
1772 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1773 */
1774 void arm7_9_enable_breakpoints(struct target *target)
1775 {
1776 struct breakpoint *breakpoint = target->breakpoints;
1777
1778 /* set any pending breakpoints */
1779 while (breakpoint)
1780 {
1781 arm7_9_set_breakpoint(target, breakpoint);
1782 breakpoint = breakpoint->next;
1783 }
1784 }
1785
1786 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1787 {
1788 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1789 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1790 struct breakpoint *breakpoint = target->breakpoints;
1791 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1792 int err, retval = ERROR_OK;
1793
1794 LOG_DEBUG("-");
1795
1796 if (target->state != TARGET_HALTED)
1797 {
1798 LOG_WARNING("target not halted");
1799 return ERROR_TARGET_NOT_HALTED;
1800 }
1801
1802 if (!debug_execution)
1803 {
1804 target_free_all_working_areas(target);
1805 }
1806
1807 /* current = 1: continue on current pc, otherwise continue at <address> */
1808 if (!current)
1809 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1810
1811 uint32_t current_pc;
1812 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1813
1814 /* the front-end may request us not to handle breakpoints */
1815 if (handle_breakpoints)
1816 {
1817 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1818 {
1819 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1820 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1821 {
1822 return retval;
1823 }
1824
1825 /* calculate PC of next instruction */
1826 uint32_t next_pc;
1827 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1828 {
1829 uint32_t current_opcode;
1830 target_read_u32(target, current_pc, &current_opcode);
1831 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1832 return retval;
1833 }
1834
1835 LOG_DEBUG("enable single-step");
1836 arm7_9->enable_single_step(target, next_pc);
1837
1838 target->debug_reason = DBG_REASON_SINGLESTEP;
1839
1840 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1841 {
1842 return retval;
1843 }
1844
1845 if (armv4_5->core_state == ARM_STATE_ARM)
1846 arm7_9->branch_resume(target);
1847 else if (armv4_5->core_state == ARM_STATE_THUMB)
1848 {
1849 arm7_9->branch_resume_thumb(target);
1850 }
1851 else
1852 {
1853 LOG_ERROR("unhandled core state");
1854 return ERROR_FAIL;
1855 }
1856
1857 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1858 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1859 err = arm7_9_execute_sys_speed(target);
1860
1861 LOG_DEBUG("disable single-step");
1862 arm7_9->disable_single_step(target);
1863
1864 if (err != ERROR_OK)
1865 {
1866 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1867 {
1868 return retval;
1869 }
1870 target->state = TARGET_UNKNOWN;
1871 return err;
1872 }
1873
1874 arm7_9_debug_entry(target);
1875 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1876
1877 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1878 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1879 {
1880 return retval;
1881 }
1882 }
1883 }
1884
1885 /* enable any pending breakpoints and watchpoints */
1886 arm7_9_enable_breakpoints(target);
1887 arm7_9_enable_watchpoints(target);
1888
1889 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1890 {
1891 return retval;
1892 }
1893
1894 if (armv4_5->core_state == ARM_STATE_ARM)
1895 {
1896 arm7_9->branch_resume(target);
1897 }
1898 else if (armv4_5->core_state == ARM_STATE_THUMB)
1899 {
1900 arm7_9->branch_resume_thumb(target);
1901 }
1902 else
1903 {
1904 LOG_ERROR("unhandled core state");
1905 return ERROR_FAIL;
1906 }
1907
1908 /* deassert DBGACK and INTDIS */
1909 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1910 /* INTDIS only when we really resume, not during debug execution */
1911 if (!debug_execution)
1912 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1913 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1914
1915 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1916 {
1917 return retval;
1918 }
1919
1920 target->debug_reason = DBG_REASON_NOTHALTED;
1921
1922 if (!debug_execution)
1923 {
1924 /* registers are now invalid */
1925 register_cache_invalidate(armv4_5->core_cache);
1926 target->state = TARGET_RUNNING;
1927 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1928 {
1929 return retval;
1930 }
1931 }
1932 else
1933 {
1934 target->state = TARGET_DEBUG_RUNNING;
1935 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1936 {
1937 return retval;
1938 }
1939 }
1940
1941 LOG_DEBUG("target resumed");
1942
1943 return ERROR_OK;
1944 }
1945
1946 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1947 {
1948 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1949 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1950 uint32_t current_pc;
1951 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1952
1953 if (next_pc != current_pc)
1954 {
1955 /* setup an inverse breakpoint on the current PC
1956 * - comparator 1 matches the current address
1957 * - rangeout from comparator 1 is connected to comparator 0 rangein
1958 * - comparator 0 matches any address, as long as rangein is low */
1959 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1960 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1961 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1962 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1963 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1964 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1965 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1966 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1967 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1968 }
1969 else
1970 {
1971 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1980 }
1981 }
1982
1983 void arm7_9_disable_eice_step(struct target *target)
1984 {
1985 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1986
1987 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1988 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1989 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1990 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1991 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1992 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1993 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1994 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1995 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1996 }
1997
1998 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
1999 {
2000 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2001 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2002 struct breakpoint *breakpoint = NULL;
2003 int err, retval;
2004
2005 if (target->state != TARGET_HALTED)
2006 {
2007 LOG_WARNING("target not halted");
2008 return ERROR_TARGET_NOT_HALTED;
2009 }
2010
2011 /* current = 1: continue on current pc, otherwise continue at <address> */
2012 if (!current)
2013 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2014
2015 uint32_t current_pc;
2016 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2017
2018 /* the front-end may request us not to handle breakpoints */
2019 if (handle_breakpoints)
2020 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2021 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2022 {
2023 return retval;
2024 }
2025
2026 target->debug_reason = DBG_REASON_SINGLESTEP;
2027
2028 /* calculate PC of next instruction */
2029 uint32_t next_pc;
2030 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2031 {
2032 uint32_t current_opcode;
2033 target_read_u32(target, current_pc, &current_opcode);
2034 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2035 return retval;
2036 }
2037
2038 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2039 {
2040 return retval;
2041 }
2042
2043 arm7_9->enable_single_step(target, next_pc);
2044
2045 if (armv4_5->core_state == ARM_STATE_ARM)
2046 {
2047 arm7_9->branch_resume(target);
2048 }
2049 else if (armv4_5->core_state == ARM_STATE_THUMB)
2050 {
2051 arm7_9->branch_resume_thumb(target);
2052 }
2053 else
2054 {
2055 LOG_ERROR("unhandled core state");
2056 return ERROR_FAIL;
2057 }
2058
2059 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2060 {
2061 return retval;
2062 }
2063
2064 err = arm7_9_execute_sys_speed(target);
2065 arm7_9->disable_single_step(target);
2066
2067 /* registers are now invalid */
2068 register_cache_invalidate(armv4_5->core_cache);
2069
2070 if (err != ERROR_OK)
2071 {
2072 target->state = TARGET_UNKNOWN;
2073 } else {
2074 arm7_9_debug_entry(target);
2075 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2076 {
2077 return retval;
2078 }
2079 LOG_DEBUG("target stepped");
2080 }
2081
2082 if (breakpoint)
2083 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2084 {
2085 return retval;
2086 }
2087
2088 return err;
2089 }
2090
2091 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2092 int num, enum arm_mode mode)
2093 {
2094 uint32_t* reg_p[16];
2095 uint32_t value;
2096 int retval;
2097 struct arm_reg *areg = r->arch_info;
2098 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2099 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2100
2101 if (!is_arm_mode(armv4_5->core_mode))
2102 return ERROR_FAIL;
2103 if ((num < 0) || (num > 16))
2104 return ERROR_INVALID_ARGUMENTS;
2105
2106 if ((mode != ARM_MODE_ANY)
2107 && (mode != armv4_5->core_mode)
2108 && (areg->mode != ARM_MODE_ANY))
2109 {
2110 uint32_t tmp_cpsr;
2111
2112 /* change processor mode (mask T bit) */
2113 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2114 tmp_cpsr |= mode;
2115 tmp_cpsr &= ~0x20;
2116 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2117 }
2118
2119 if ((num >= 0) && (num <= 15))
2120 {
2121 /* read a normal core register */
2122 reg_p[num] = &value;
2123
2124 arm7_9->read_core_regs(target, 1 << num, reg_p);
2125 }
2126 else
2127 {
2128 /* read a program status register
2129 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2130 */
2131 arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
2132 }
2133
2134 if ((retval = jtag_execute_queue()) != ERROR_OK)
2135 {
2136 return retval;
2137 }
2138
2139 r->valid = 1;
2140 r->dirty = 0;
2141 buf_set_u32(r->value, 0, 32, value);
2142
2143 if ((mode != ARM_MODE_ANY)
2144 && (mode != armv4_5->core_mode)
2145 && (areg->mode != ARM_MODE_ANY)) {
2146 /* restore processor mode (mask T bit) */
2147 arm7_9->write_xpsr_im8(target,
2148 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2149 & ~0x20, 0, 0);
2150 }
2151
2152 return ERROR_OK;
2153 }
2154
2155 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2156 int num, enum arm_mode mode, uint32_t value)
2157 {
2158 uint32_t reg[16];
2159 struct arm_reg *areg = r->arch_info;
2160 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2161 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2162
2163 if (!is_arm_mode(armv4_5->core_mode))
2164 return ERROR_FAIL;
2165 if ((num < 0) || (num > 16))
2166 return ERROR_INVALID_ARGUMENTS;
2167
2168 if ((mode != ARM_MODE_ANY)
2169 && (mode != armv4_5->core_mode)
2170 && (areg->mode != ARM_MODE_ANY)) {
2171 uint32_t tmp_cpsr;
2172
2173 /* change processor mode (mask T bit) */
2174 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2175 tmp_cpsr |= mode;
2176 tmp_cpsr &= ~0x20;
2177 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2178 }
2179
2180 if ((num >= 0) && (num <= 15))
2181 {
2182 /* write a normal core register */
2183 reg[num] = value;
2184
2185 arm7_9->write_core_regs(target, 1 << num, reg);
2186 }
2187 else
2188 {
2189 /* write a program status register
2190 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2191 */
2192 int spsr = (areg->mode != ARM_MODE_ANY);
2193
2194 /* if we're writing the CPSR, mask the T bit */
2195 if (!spsr)
2196 value &= ~0x20;
2197
2198 arm7_9->write_xpsr(target, value, spsr);
2199 }
2200
2201 r->valid = 1;
2202 r->dirty = 0;
2203
2204 if ((mode != ARM_MODE_ANY)
2205 && (mode != armv4_5->core_mode)
2206 && (areg->mode != ARM_MODE_ANY)) {
2207 /* restore processor mode (mask T bit) */
2208 arm7_9->write_xpsr_im8(target,
2209 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2210 & ~0x20, 0, 0);
2211 }
2212
2213 return jtag_execute_queue();
2214 }
2215
2216 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2217 {
2218 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2219 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2220 uint32_t reg[16];
2221 uint32_t num_accesses = 0;
2222 int thisrun_accesses;
2223 int i;
2224 uint32_t cpsr;
2225 int retval;
2226 int last_reg = 0;
2227
2228 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2229
2230 if (target->state != TARGET_HALTED)
2231 {
2232 LOG_WARNING("target not halted");
2233 return ERROR_TARGET_NOT_HALTED;
2234 }
2235
2236 /* sanitize arguments */
2237 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2238 return ERROR_INVALID_ARGUMENTS;
2239
2240 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2241 return ERROR_TARGET_UNALIGNED_ACCESS;
2242
2243 /* load the base register with the address of the first word */
2244 reg[0] = address;
2245 arm7_9->write_core_regs(target, 0x1, reg);
2246
2247 int j = 0;
2248
2249 switch (size)
2250 {
2251 case 4:
2252 while (num_accesses < count)
2253 {
2254 uint32_t reg_list;
2255 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2256 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2257
2258 if (last_reg <= thisrun_accesses)
2259 last_reg = thisrun_accesses;
2260
2261 arm7_9->load_word_regs(target, reg_list);
2262
2263 /* fast memory reads are only safe when the target is running
2264 * from a sufficiently high clock (32 kHz is usually too slow)
2265 */
2266 if (arm7_9->fast_memory_access)
2267 retval = arm7_9_execute_fast_sys_speed(target);
2268 else
2269 retval = arm7_9_execute_sys_speed(target);
2270 if (retval != ERROR_OK)
2271 return retval;
2272
2273 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2274
2275 /* advance buffer, count number of accesses */
2276 buffer += thisrun_accesses * 4;
2277 num_accesses += thisrun_accesses;
2278
2279 if ((j++%1024) == 0)
2280 {
2281 keep_alive();
2282 }
2283 }
2284 break;
2285 case 2:
2286 while (num_accesses < count)
2287 {
2288 uint32_t reg_list;
2289 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2290 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2291
2292 for (i = 1; i <= thisrun_accesses; i++)
2293 {
2294 if (i > last_reg)
2295 last_reg = i;
2296 arm7_9->load_hword_reg(target, i);
2297 /* fast memory reads are only safe when the target is running
2298 * from a sufficiently high clock (32 kHz is usually too slow)
2299 */
2300 if (arm7_9->fast_memory_access)
2301 retval = arm7_9_execute_fast_sys_speed(target);
2302 else
2303 retval = arm7_9_execute_sys_speed(target);
2304 if (retval != ERROR_OK)
2305 {
2306 return retval;
2307 }
2308
2309 }
2310
2311 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2312
2313 /* advance buffer, count number of accesses */
2314 buffer += thisrun_accesses * 2;
2315 num_accesses += thisrun_accesses;
2316
2317 if ((j++%1024) == 0)
2318 {
2319 keep_alive();
2320 }
2321 }
2322 break;
2323 case 1:
2324 while (num_accesses < count)
2325 {
2326 uint32_t reg_list;
2327 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2328 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2329
2330 for (i = 1; i <= thisrun_accesses; i++)
2331 {
2332 if (i > last_reg)
2333 last_reg = i;
2334 arm7_9->load_byte_reg(target, i);
2335 /* fast memory reads are only safe when the target is running
2336 * from a sufficiently high clock (32 kHz is usually too slow)
2337 */
2338 if (arm7_9->fast_memory_access)
2339 retval = arm7_9_execute_fast_sys_speed(target);
2340 else
2341 retval = arm7_9_execute_sys_speed(target);
2342 if (retval != ERROR_OK)
2343 {
2344 return retval;
2345 }
2346 }
2347
2348 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2349
2350 /* advance buffer, count number of accesses */
2351 buffer += thisrun_accesses * 1;
2352 num_accesses += thisrun_accesses;
2353
2354 if ((j++%1024) == 0)
2355 {
2356 keep_alive();
2357 }
2358 }
2359 break;
2360 }
2361
2362 if (!is_arm_mode(armv4_5->core_mode))
2363 return ERROR_FAIL;
2364
2365 for (i = 0; i <= last_reg; i++) {
2366 struct reg *r = arm_reg_current(armv4_5, i);
2367
2368 r->dirty = r->valid;
2369 }
2370
2371 arm7_9->read_xpsr(target, &cpsr, 0);
2372 if ((retval = jtag_execute_queue()) != ERROR_OK)
2373 {
2374 LOG_ERROR("JTAG error while reading cpsr");
2375 return ERROR_TARGET_DATA_ABORT;
2376 }
2377
2378 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2379 {
2380 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2381
2382 arm7_9->write_xpsr_im8(target,
2383 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2384 & ~0x20, 0, 0);
2385
2386 return ERROR_TARGET_DATA_ABORT;
2387 }
2388
2389 return ERROR_OK;
2390 }
2391
2392 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2393 {
2394 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2395 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2396 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2397
2398 uint32_t reg[16];
2399 uint32_t num_accesses = 0;
2400 int thisrun_accesses;
2401 int i;
2402 uint32_t cpsr;
2403 int retval;
2404 int last_reg = 0;
2405
2406 #ifdef _DEBUG_ARM7_9_
2407 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2408 #endif
2409
2410 if (target->state != TARGET_HALTED)
2411 {
2412 LOG_WARNING("target not halted");
2413 return ERROR_TARGET_NOT_HALTED;
2414 }
2415
2416 /* sanitize arguments */
2417 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2418 return ERROR_INVALID_ARGUMENTS;
2419
2420 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2421 return ERROR_TARGET_UNALIGNED_ACCESS;
2422
2423 /* load the base register with the address of the first word */
2424 reg[0] = address;
2425 arm7_9->write_core_regs(target, 0x1, reg);
2426
2427 /* Clear DBGACK, to make sure memory fetches work as expected */
2428 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2429 embeddedice_store_reg(dbg_ctrl);
2430
2431 switch (size)
2432 {
2433 case 4:
2434 while (num_accesses < count)
2435 {
2436 uint32_t reg_list;
2437 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2438 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2439
2440 for (i = 1; i <= thisrun_accesses; i++)
2441 {
2442 if (i > last_reg)
2443 last_reg = i;
2444 reg[i] = target_buffer_get_u32(target, buffer);
2445 buffer += 4;
2446 }
2447
2448 arm7_9->write_core_regs(target, reg_list, reg);
2449
2450 arm7_9->store_word_regs(target, reg_list);
2451
2452 /* fast memory writes are only safe when the target is running
2453 * from a sufficiently high clock (32 kHz is usually too slow)
2454 */
2455 if (arm7_9->fast_memory_access)
2456 retval = arm7_9_execute_fast_sys_speed(target);
2457 else
2458 retval = arm7_9_execute_sys_speed(target);
2459 if (retval != ERROR_OK)
2460 {
2461 return retval;
2462 }
2463
2464 num_accesses += thisrun_accesses;
2465 }
2466 break;
2467 case 2:
2468 while (num_accesses < count)
2469 {
2470 uint32_t reg_list;
2471 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2472 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2473
2474 for (i = 1; i <= thisrun_accesses; i++)
2475 {
2476 if (i > last_reg)
2477 last_reg = i;
2478 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2479 buffer += 2;
2480 }
2481
2482 arm7_9->write_core_regs(target, reg_list, reg);
2483
2484 for (i = 1; i <= thisrun_accesses; i++)
2485 {
2486 arm7_9->store_hword_reg(target, i);
2487
2488 /* fast memory writes are only safe when the target is running
2489 * from a sufficiently high clock (32 kHz is usually too slow)
2490 */
2491 if (arm7_9->fast_memory_access)
2492 retval = arm7_9_execute_fast_sys_speed(target);
2493 else
2494 retval = arm7_9_execute_sys_speed(target);
2495 if (retval != ERROR_OK)
2496 {
2497 return retval;
2498 }
2499 }
2500
2501 num_accesses += thisrun_accesses;
2502 }
2503 break;
2504 case 1:
2505 while (num_accesses < count)
2506 {
2507 uint32_t reg_list;
2508 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2509 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2510
2511 for (i = 1; i <= thisrun_accesses; i++)
2512 {
2513 if (i > last_reg)
2514 last_reg = i;
2515 reg[i] = *buffer++ & 0xff;
2516 }
2517
2518 arm7_9->write_core_regs(target, reg_list, reg);
2519
2520 for (i = 1; i <= thisrun_accesses; i++)
2521 {
2522 arm7_9->store_byte_reg(target, i);
2523 /* fast memory writes are only safe when the target is running
2524 * from a sufficiently high clock (32 kHz is usually too slow)
2525 */
2526 if (arm7_9->fast_memory_access)
2527 retval = arm7_9_execute_fast_sys_speed(target);
2528 else
2529 retval = arm7_9_execute_sys_speed(target);
2530 if (retval != ERROR_OK)
2531 {
2532 return retval;
2533 }
2534
2535 }
2536
2537 num_accesses += thisrun_accesses;
2538 }
2539 break;
2540 }
2541
2542 /* Re-Set DBGACK */
2543 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2544 embeddedice_store_reg(dbg_ctrl);
2545
2546 if (!is_arm_mode(armv4_5->core_mode))
2547 return ERROR_FAIL;
2548
2549 for (i = 0; i <= last_reg; i++) {
2550 struct reg *r = arm_reg_current(armv4_5, i);
2551
2552 r->dirty = r->valid;
2553 }
2554
2555 arm7_9->read_xpsr(target, &cpsr, 0);
2556 if ((retval = jtag_execute_queue()) != ERROR_OK)
2557 {
2558 LOG_ERROR("JTAG error while reading cpsr");
2559 return ERROR_TARGET_DATA_ABORT;
2560 }
2561
2562 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2563 {
2564 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2565
2566 arm7_9->write_xpsr_im8(target,
2567 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2568 & ~0x20, 0, 0);
2569
2570 return ERROR_TARGET_DATA_ABORT;
2571 }
2572
2573 return ERROR_OK;
2574 }
2575
2576 static int dcc_count;
2577 static uint8_t *dcc_buffer;
2578
2579 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2580 {
2581 int retval = ERROR_OK;
2582 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2583
2584 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2585 return retval;
2586
2587 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2588 int count = dcc_count;
2589 uint8_t *buffer = dcc_buffer;
2590 if (count > 2)
2591 {
2592 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2593 * core function repeated. */
2594 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2595 buffer += 4;
2596
2597 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2598 uint8_t reg_addr = ice_reg->addr & 0x1f;
2599 struct jtag_tap *tap;
2600 tap = ice_reg->jtag_info->tap;
2601
2602 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2603 buffer += (count-2)*4;
2604
2605 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2606 } else
2607 {
2608 int i;
2609 for (i = 0; i < count; i++)
2610 {
2611 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2612 buffer += 4;
2613 }
2614 }
2615
2616 if ((retval = target_halt(target))!= ERROR_OK)
2617 {
2618 return retval;
2619 }
2620 return target_wait_state(target, TARGET_HALTED, 500);
2621 }
2622
2623 static const uint32_t dcc_code[] =
2624 {
2625 /* r0 == input, points to memory buffer
2626 * r1 == scratch
2627 */
2628
2629 /* spin until DCC control (c0) reports data arrived */
2630 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2631 0xe3110001, /* tst r1, #1 */
2632 0x0afffffc, /* bne w */
2633
2634 /* read word from DCC (c1), write to memory */
2635 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2636 0xe4801004, /* str r1, [r0], #4 */
2637
2638 /* repeat */
2639 0xeafffff9 /* b w */
2640 };
2641
2642 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2643 {
2644 int retval;
2645 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2646 int i;
2647
2648 if (!arm7_9->dcc_downloads)
2649 return target_write_memory(target, address, 4, count, buffer);
2650
2651 /* regrab previously allocated working_area, or allocate a new one */
2652 if (!arm7_9->dcc_working_area)
2653 {
2654 uint8_t dcc_code_buf[6 * 4];
2655
2656 /* make sure we have a working area */
2657 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2658 {
2659 LOG_INFO("no working area available, falling back to memory writes");
2660 return target_write_memory(target, address, 4, count, buffer);
2661 }
2662
2663 /* copy target instructions to target endianness */
2664 for (i = 0; i < 6; i++)
2665 {
2666 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2667 }
2668
2669 /* write DCC code to working area */
2670 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2671 {
2672 return retval;
2673 }
2674 }
2675
2676 struct arm_algorithm armv4_5_info;
2677 struct reg_param reg_params[1];
2678
2679 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
2680 armv4_5_info.core_mode = ARM_MODE_SVC;
2681 armv4_5_info.core_state = ARM_STATE_ARM;
2682
2683 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2684
2685 buf_set_u32(reg_params[0].value, 0, 32, address);
2686
2687 dcc_count = count;
2688 dcc_buffer = buffer;
2689 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2690 arm7_9->dcc_working_area->address,
2691 arm7_9->dcc_working_area->address + 6*4,
2692 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2693
2694 if (retval == ERROR_OK)
2695 {
2696 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2697 if (endaddress != (address + count*4))
2698 {
2699 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2700 retval = ERROR_FAIL;
2701 }
2702 }
2703
2704 destroy_reg_param(&reg_params[0]);
2705
2706 return retval;
2707 }
2708
2709 /**
2710 * Perform per-target setup that requires JTAG access.
2711 */
2712 int arm7_9_examine(struct target *target)
2713 {
2714 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2715 int retval;
2716
2717 if (!target_was_examined(target)) {
2718 struct reg_cache *t, **cache_p;
2719
2720 t = embeddedice_build_reg_cache(target, arm7_9);
2721 if (t == NULL)
2722 return ERROR_FAIL;
2723
2724 cache_p = register_get_last_cache_p(&target->reg_cache);
2725 (*cache_p) = t;
2726 arm7_9->eice_cache = (*cache_p);
2727
2728 if (arm7_9->armv4_5_common.etm)
2729 (*cache_p)->next = etm_build_reg_cache(target,
2730 &arm7_9->jtag_info,
2731 arm7_9->armv4_5_common.etm);
2732
2733 target_set_examined(target);
2734 }
2735
2736 retval = embeddedice_setup(target);
2737 if (retval == ERROR_OK)
2738 retval = arm7_9_setup(target);
2739 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2740 retval = etm_setup(target);
2741 return retval;
2742 }
2743
2744
2745 int arm7_9_check_reset(struct target *target)
2746 {
2747 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2748
2749 if (get_target_reset_nag() && !arm7_9->dcc_downloads)
2750 {
2751 LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
2752 }
2753
2754 return ERROR_OK;
2755 }
2756
2757 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2758 {
2759 struct target *target = get_current_target(CMD_CTX);
2760 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2761
2762 if (!is_arm7_9(arm7_9))
2763 {
2764 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2765 return ERROR_TARGET_INVALID;
2766 }
2767
2768 if (CMD_ARGC > 0)
2769 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2770
2771 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2772
2773 return ERROR_OK;
2774 }
2775
2776 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2777 {
2778 struct target *target = get_current_target(CMD_CTX);
2779 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2780
2781 if (!is_arm7_9(arm7_9))
2782 {
2783 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2784 return ERROR_TARGET_INVALID;
2785 }
2786
2787 if (CMD_ARGC > 0)
2788 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2789
2790 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2791
2792 return ERROR_OK;
2793 }
2794
2795 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2796 {
2797 struct target *target = get_current_target(CMD_CTX);
2798 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2799
2800 if (!is_arm7_9(arm7_9))
2801 {
2802 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2803 return ERROR_TARGET_INVALID;
2804 }
2805
2806 if (CMD_ARGC > 0)
2807 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2808
2809 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2810
2811 return ERROR_OK;
2812 }
2813
2814 COMMAND_HANDLER(handle_arm7_9_semihosting_command)
2815 {
2816 struct target *target = get_current_target(CMD_CTX);
2817 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2818
2819 if (!is_arm7_9(arm7_9))
2820 {
2821 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2822 return ERROR_TARGET_INVALID;
2823 }
2824
2825 if (CMD_ARGC > 0)
2826 {
2827 int semihosting;
2828
2829 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
2830
2831 if (!target_was_examined(target))
2832 {
2833 LOG_ERROR("Target not examined yet");
2834 return ERROR_FAIL;
2835 }
2836
2837 if (arm7_9->has_vector_catch) {
2838 struct reg *vector_catch = &arm7_9->eice_cache
2839 ->reg_list[EICE_VEC_CATCH];
2840
2841 if (!vector_catch->valid)
2842 embeddedice_read_reg(vector_catch);
2843 buf_set_u32(vector_catch->value, 2, 1, semihosting);
2844 embeddedice_store_reg(vector_catch);
2845 } else {
2846 /* TODO: allow optional high vectors and/or BKPT_HARD */
2847 if (semihosting)
2848 breakpoint_add(target, 8, 4, BKPT_SOFT);
2849 else
2850 breakpoint_remove(target, 8);
2851 }
2852
2853 /* FIXME never let that "catch" be dropped! */
2854 arm7_9->armv4_5_common.is_semihosting = semihosting;
2855
2856 }
2857
2858 command_print(CMD_CTX, "semihosting is %s",
2859 arm7_9->armv4_5_common.is_semihosting
2860 ? "enabled" : "disabled");
2861
2862 return ERROR_OK;
2863 }
2864
2865 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2866 {
2867 int retval = ERROR_OK;
2868 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2869
2870 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2871
2872 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2873 return retval;
2874
2875 /* caller must have allocated via calloc(), so everything's zeroed */
2876
2877 arm7_9->wp_available_max = 2;
2878
2879 arm7_9->fast_memory_access = false;
2880 arm7_9->dcc_downloads = false;
2881
2882 armv4_5->arch_info = arm7_9;
2883 armv4_5->read_core_reg = arm7_9_read_core_reg;
2884 armv4_5->write_core_reg = arm7_9_write_core_reg;
2885 armv4_5->full_context = arm7_9_full_context;
2886
2887 retval = arm_init_arch_info(target, armv4_5);
2888 if (retval != ERROR_OK)
2889 return retval;
2890
2891 return target_register_timer_callback(arm7_9_handle_target_request,
2892 1, 1, target);
2893 }
2894
2895 static const struct command_registration arm7_9_any_command_handlers[] = {
2896 {
2897 "dbgrq",
2898 .handler = handle_arm7_9_dbgrq_command,
2899 .mode = COMMAND_ANY,
2900 .usage = "['enable'|'disable']",
2901 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2902 "for target halt requests",
2903 },
2904 {
2905 "fast_memory_access",
2906 .handler = handle_arm7_9_fast_memory_access_command,
2907 .mode = COMMAND_ANY,
2908 .usage = "['enable'|'disable']",
2909 .help = "use fast memory accesses instead of slower "
2910 "but potentially safer accesses",
2911 },
2912 {
2913 "dcc_downloads",
2914 .handler = handle_arm7_9_dcc_downloads_command,
2915 .mode = COMMAND_ANY,
2916 .usage = "['enable'|'disable']",
2917 .help = "use DCC downloads for larger memory writes",
2918 },
2919 {
2920 "semihosting",
2921 .handler = handle_arm7_9_semihosting_command,
2922 .mode = COMMAND_EXEC,
2923 .usage = "['enable'|'disable']",
2924 .help = "activate support for semihosting operations",
2925 },
2926 COMMAND_REGISTRATION_DONE
2927 };
2928 const struct command_registration arm7_9_command_handlers[] = {
2929 {
2930 .chain = arm_command_handlers,
2931 },
2932 {
2933 .chain = etm_command_handlers,
2934 },
2935 {
2936 .name = "arm7_9",
2937 .mode = COMMAND_ANY,
2938 .help = "arm7/9 specific commands",
2939 .chain = arm7_9_any_command_handlers,
2940 },
2941 COMMAND_REGISTRATION_DONE
2942 };
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