1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
47 * procedure interfaces. Modal programming interfaces are very error prone.
48 * Procedures should be either queued, or synchronous. Otherwise input
49 * and output constraints are context-sensitive, and it's hard to know
50 * what a block of code will do just by reading it.
54 * Relevant specifications from ARM include:
56 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
57 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
59 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
60 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 #include "arm_adi_v5.h"
68 #include <helper/time_support.h>
72 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
73 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
74 * result checking until swjdp_end_transaction()
75 * This must be done before using or deallocating any return variables.
76 * swjdp->trans_mode == TRANS_MODE_ATOMIC
77 * All reads and writes to the AHB bus are checked for valid completion, and return values
78 * are immediatley available.
82 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
85 uint32_t tar_block_size(uint32_t address)
86 Return the largest block starting at address that does not cross a tar block size alignment boundary
88 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
90 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
93 /***************************************************************************
95 * DPACC and APACC scanchain access through JTAG-DP *
97 ***************************************************************************/
100 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
101 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
102 * discusses operations which access these registers.
104 * Note that only one scan is performed. If RnW is set, a separate scan
105 * will be needed to collect the data which was read; the "invalue" collects
106 * the posted result of a preceding operation, not the current one.
108 * @param swjdp the DAP
109 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
110 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
111 * SELECT register has more addressing bits.
112 * @param RnW false iff outvalue will be written to the DP or AP
113 * @param outvalue points to a 32-bit (little-endian) integer
114 * @param invalue NULL, or points to a 32-bit (little-endian) integer
115 * @param ack points to where the three bit JTAG_ACK_* code will be stored
117 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
118 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
119 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
121 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
122 struct scan_field fields
[2];
123 uint8_t out_addr_buf
;
125 jtag_set_end_state(TAP_IDLE
);
126 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
128 /* Add specified number of tck clocks before accessing memory bus */
130 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
131 * they provide more time for the (MEM) AP to complete the read ...
132 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
134 if ((instr
== JTAG_DP_APACC
)
135 && ((reg_addr
== AP_REG_DRW
)
136 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
137 && (swjdp
->memaccess_tck
!= 0))
138 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
140 /* Scan out a read or write operation using some DP or AP register.
141 * For APACC access with any sticky error flag set, this is discarded.
143 fields
[0].tap
= jtag_info
->tap
;
144 fields
[0].num_bits
= 3;
145 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
146 fields
[0].out_value
= &out_addr_buf
;
147 fields
[0].in_value
= ack
;
149 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
150 * complete; data we write is discarded, data we read is unpredictable.
151 * When overrun detect is active, STICKYORUN is set.
154 fields
[1].tap
= jtag_info
->tap
;
155 fields
[1].num_bits
= 32;
156 fields
[1].out_value
= outvalue
;
157 fields
[1].in_value
= invalue
;
159 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
164 /* Scan out and in from host ordered uint32_t variables */
165 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
166 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
167 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
169 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
170 struct scan_field fields
[2];
171 uint8_t out_value_buf
[4];
172 uint8_t out_addr_buf
;
174 jtag_set_end_state(TAP_IDLE
);
175 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
177 /* Add specified number of tck clocks before accessing memory bus */
179 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
180 * they provide more time for the (MEM) AP to complete the read ...
182 if ((instr
== JTAG_DP_APACC
)
183 && ((reg_addr
== AP_REG_DRW
)
184 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
185 && (swjdp
->memaccess_tck
!= 0))
186 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
188 fields
[0].tap
= jtag_info
->tap
;
189 fields
[0].num_bits
= 3;
190 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
191 fields
[0].out_value
= &out_addr_buf
;
192 fields
[0].in_value
= ack
;
194 fields
[1].tap
= jtag_info
->tap
;
195 fields
[1].num_bits
= 32;
196 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
197 fields
[1].out_value
= out_value_buf
;
198 fields
[1].in_value
= NULL
;
202 fields
[1].in_value
= (uint8_t *)invalue
;
203 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
205 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
) invalue
);
209 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
215 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
216 static int scan_inout_check(struct swjdp_common
*swjdp
,
217 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
218 uint8_t *outvalue
, uint8_t *invalue
)
220 adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
222 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
223 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
,
224 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
226 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
227 * ack = OK/FAULT and the check CTRL_STAT
229 if ((instr
== JTAG_DP_APACC
)
230 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
231 return jtagdp_transaction_endcheck(swjdp
);
236 static int scan_inout_check_u32(struct swjdp_common
*swjdp
,
237 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
238 uint32_t outvalue
, uint32_t *invalue
)
240 /* Issue the read or write */
241 adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
243 /* For reads, collect posted value; RDBUFF has no other effect.
244 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
246 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
247 adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
248 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
250 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
251 * ack = OK/FAULT and then check CTRL_STAT
253 if ((instr
== JTAG_DP_APACC
)
254 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
255 return jtagdp_transaction_endcheck(swjdp
);
260 int jtagdp_transaction_endcheck(struct swjdp_common
*swjdp
)
265 /* too expensive to call keep_alive() here */
268 /* Danger!!!! BROKEN!!!! */
269 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
270 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
271 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
272 R956 introduced the check on return value here and now Michael Schwingen reports
273 that this code no longer works....
275 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
277 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
279 LOG_ERROR("BUG: Why does this fail the first time????");
281 /* Why??? second time it works??? */
284 /* Post CTRL/STAT read; discard any previous posted read value
285 * but collect its ACK status.
287 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
288 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
289 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
292 swjdp
->ack
= swjdp
->ack
& 0x7;
294 /* common code path avoids calling timeval_ms() */
295 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
297 long long then
= timeval_ms();
299 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
301 if (swjdp
->ack
== JTAG_ACK_WAIT
)
303 if ((timeval_ms()-then
) > 1000)
305 /* NOTE: this would be a good spot
306 * to use JTAG_DP_ABORT.
308 LOG_WARNING("Timeout (1000ms) waiting "
310 "in JTAG-DP transaction");
311 return ERROR_JTAG_DEVICE_ERROR
;
316 LOG_WARNING("Invalid ACK %#x "
317 "in JTAG-DP transaction",
319 return ERROR_JTAG_DEVICE_ERROR
;
322 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
323 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
324 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
326 swjdp
->ack
= swjdp
->ack
& 0x7;
330 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
332 /* Check for STICKYERR and STICKYORUN */
333 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
335 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
336 /* Check power to debug regions */
337 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
338 ahbap_debugport_init(swjdp
);
341 uint32_t mem_ap_csw
, mem_ap_tar
;
343 /* Maybe print information about last intended
344 * MEM-AP access; but not if autoincrementing.
345 * *Real* CSW and TAR values are always shown.
347 if (swjdp
->ap_tar_value
!= (uint32_t) -1)
348 LOG_DEBUG("MEM-AP Cached values: "
350 ", ap_csw 0x%" PRIx32
351 ", ap_tar 0x%" PRIx32
,
352 swjdp
->ap_bank_value
,
354 swjdp
->ap_tar_value
);
356 if (ctrlstat
& SSTICKYORUN
)
357 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
358 "memaccess, or reduce jtag speed");
360 if (ctrlstat
& SSTICKYERR
)
361 LOG_ERROR("JTAG-DP STICKY ERROR");
363 /* Clear Sticky Error Bits */
364 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
365 DP_CTRL_STAT
, DPAP_WRITE
,
366 swjdp
->dp_ctrl_stat
| SSTICKYORUN
368 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
369 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
370 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
373 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
375 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
376 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
377 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
379 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
380 PRIx32
, mem_ap_csw
, mem_ap_tar
);
383 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
385 return ERROR_JTAG_DEVICE_ERROR
;
391 /***************************************************************************
393 * DP and MEM-AP register access through APACC and DPACC *
395 ***************************************************************************/
397 static int dap_dp_write_reg(struct swjdp_common
*swjdp
,
398 uint32_t value
, uint8_t reg_addr
)
400 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
401 reg_addr
, DPAP_WRITE
, value
, NULL
);
404 static int dap_dp_read_reg(struct swjdp_common
*swjdp
,
405 uint32_t *value
, uint8_t reg_addr
)
407 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
408 reg_addr
, DPAP_READ
, 0, value
);
412 * Select one of the APs connected to the specified DAP. The
413 * selection is implicitly used with future AP transactions.
414 * This is a NOP if the specified AP is already selected.
416 * @param swjdp The DAP
417 * @param apsel Number of the AP to (implicitly) use with further
418 * transactions. This normally identifies a MEM-AP.
420 void dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
422 uint32_t select
= (apsel
<< 24) & 0xFF000000;
424 if (select
!= swjdp
->apsel
)
426 swjdp
->apsel
= select
;
427 /* Switching AP invalidates cached values.
428 * Values MUST BE UPDATED BEFORE AP ACCESS.
430 swjdp
->ap_bank_value
= -1;
431 swjdp
->ap_csw_value
= -1;
432 swjdp
->ap_tar_value
= -1;
436 /** Select the AP register bank matching bits 7:4 of ap_reg. */
437 static int dap_ap_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
439 uint32_t select
= (ap_reg
& 0x000000F0);
441 if (select
!= swjdp
->ap_bank_value
)
443 swjdp
->ap_bank_value
= select
;
444 select
|= swjdp
->apsel
;
445 return dap_dp_write_reg(swjdp
, select
, DP_SELECT
);
450 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
451 uint32_t reg_addr
, uint8_t *out_value_buf
)
455 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
456 if (retval
!= ERROR_OK
)
459 return scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
460 DPAP_WRITE
, out_value_buf
, NULL
);
464 * Write an AP register value.
465 * This is synchronous iff the mode is set to ATOMIC, in which
466 * case any queued transactions are flushed.
468 * @param swjdp The DAP whose currently selected AP will be written.
469 * @param reg_addr Eight bit AP register address.
470 * @param value Word to be written at reg_addr
472 * @return In synchronous mode: ERROR_OK for success, and the register holds
473 * the specified value; else a fault code. In asynchronous mode, a status
474 * code reflecting whether the transaction was properly queued.
476 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
,
477 uint32_t reg_addr
, uint32_t value
)
479 uint8_t out_value_buf
[4];
481 buf_set_u32(out_value_buf
, 0, 32, value
);
482 return dap_ap_write_reg(swjdp
,
483 reg_addr
, out_value_buf
);
487 * Read an AP register value.
488 * This is synchronous iff the mode is set to ATOMIC, in which
489 * case any queued transactions are flushed.
491 * @param swjdp The DAP whose currently selected AP will be read.
492 * @param reg_addr Eight bit AP register address.
493 * @param value Points to where the 32-bit (little-endian) word will be stored.
495 * @return In synchronous mode: ERROR_OK for success, and *value holds
496 * the specified value; else a fault code. In asynchronous mode, a status
497 * code reflecting whether the transaction was properly queued.
499 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
,
500 uint32_t reg_addr
, uint32_t *value
)
504 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
505 if (retval
!= ERROR_OK
)
508 return scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
509 DPAP_READ
, 0, value
);
513 * Set up transfer parameters for the currently selected MEM-AP.
514 * This is synchronous iff the mode is set to ATOMIC, in which
515 * case any queued transactions are flushed.
517 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
518 * initiate data reads or writes using memory or peripheral addresses.
519 * If the CSW is configured for it, the TAR may be automatically
520 * incremented after each transfer.
522 * @todo Rename to reflect it being specifically a MEM-AP function.
524 * @param swjdp The DAP connected to the MEM-AP.
525 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
526 * matches the cached value, the register is not changed.
527 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
528 * matches the cached address, the register is not changed.
530 * @return In synchronous mode: ERROR_OK for success, and the AP is set
531 * up as requested else a fault code. In asynchronous mode, a status
532 * code reflecting whether the transaction was properly queued.
534 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
538 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
539 if (csw
!= swjdp
->ap_csw_value
)
541 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
542 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
543 if (retval
!= ERROR_OK
)
545 swjdp
->ap_csw_value
= csw
;
547 if (tar
!= swjdp
->ap_tar_value
)
549 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
550 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
551 if (retval
!= ERROR_OK
)
553 swjdp
->ap_tar_value
= tar
;
555 /* Disable TAR cache when autoincrementing */
556 if (csw
& CSW_ADDRINC_MASK
)
557 swjdp
->ap_tar_value
= -1;
562 * Asynchronous (queued) read of a word from memory or a system register.
564 * @param swjdp The DAP connected to the MEM-AP performing the read.
565 * @param address Address of the 32-bit word to read; it must be
566 * readable by the currently selected MEM-AP.
567 * @param value points to where the word will be stored when the
568 * transaction queue is flushed (assuming no errors).
570 * @return ERROR_OK for success. Otherwise a fault code.
572 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
,
577 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
579 /* Use banked addressing (REG_BDx) to avoid some link traffic
580 * (updating TAR) when reading several consecutive addresses.
582 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
583 address
& 0xFFFFFFF0);
584 if (retval
!= ERROR_OK
)
587 return dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
591 * Synchronous read of a word from memory or a system register.
592 * As a side effect, this flushes any queued transactions.
594 * @param swjdp The DAP connected to the MEM-AP performing the read.
595 * @param address Address of the 32-bit word to read; it must be
596 * readable by the currently selected MEM-AP.
597 * @param value points to where the result will be stored.
599 * @return ERROR_OK for success; *value holds the result.
600 * Otherwise a fault code.
602 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
607 retval
= mem_ap_read_u32(swjdp
, address
, value
);
608 if (retval
!= ERROR_OK
)
611 return jtagdp_transaction_endcheck(swjdp
);
615 * Asynchronous (queued) write of a word to memory or a system register.
617 * @param swjdp The DAP connected to the MEM-AP.
618 * @param address Address to be written; it must be writable by
619 * the currently selected MEM-AP.
620 * @param value Word that will be written to the address when transaction
621 * queue is flushed (assuming no errors).
623 * @return ERROR_OK for success. Otherwise a fault code.
625 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
,
630 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
632 /* Use banked addressing (REG_BDx) to avoid some link traffic
633 * (updating TAR) when writing several consecutive addresses.
635 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
636 address
& 0xFFFFFFF0);
637 if (retval
!= ERROR_OK
)
640 return dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC),
645 * Synchronous write of a word to memory or a system register.
646 * As a side effect, this flushes any queued transactions.
648 * @param swjdp The DAP connected to the MEM-AP.
649 * @param address Address to be written; it must be writable by
650 * the currently selected MEM-AP.
651 * @param value Word that will be written.
653 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
655 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
658 int retval
= mem_ap_write_u32(swjdp
, address
, value
);
660 if (retval
!= ERROR_OK
)
663 return jtagdp_transaction_endcheck(swjdp
);
666 /*****************************************************************************
668 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
670 * Write a buffer in target order (little endian) *
672 *****************************************************************************/
673 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
675 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
676 uint32_t adr
= address
;
677 uint8_t* pBuffer
= buffer
;
679 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
684 /* if we have an unaligned access - reorder data */
687 for (writecount
= 0; writecount
< count
; writecount
++)
691 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
693 for (i
= 0; i
< 4; i
++)
695 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
699 pBuffer
+= sizeof(uint32_t);
705 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
706 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
707 if (wcount
< blocksize
)
710 /* handle unaligned data at 4k boundary */
714 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
716 for (writecount
= 0; writecount
< blocksize
; writecount
++)
718 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
721 if (jtagdp_transaction_endcheck(swjdp
) == ERROR_OK
)
723 wcount
= wcount
- blocksize
;
724 address
= address
+ 4 * blocksize
;
725 buffer
= buffer
+ 4 * blocksize
;
734 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
735 return ERROR_JTAG_DEVICE_ERROR
;
742 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
743 uint8_t *buffer
, int count
, uint32_t address
)
745 int retval
= ERROR_OK
;
746 int wcount
, blocksize
, writecount
, i
;
748 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
756 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
757 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
759 if (wcount
< blocksize
)
762 /* handle unaligned data at 4k boundary */
766 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
767 writecount
= blocksize
;
771 nbytes
= MIN((writecount
<< 1), 4);
775 if (mem_ap_write_buf_u16(swjdp
, buffer
,
776 nbytes
, address
) != ERROR_OK
)
778 LOG_WARNING("Block write error address "
779 "0x%" PRIx32
", count 0x%x",
781 return ERROR_JTAG_DEVICE_ERROR
;
784 address
+= nbytes
>> 1;
789 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
791 for (i
= 0; i
< nbytes
; i
++)
793 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
798 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
799 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
800 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
802 LOG_WARNING("Block write error address "
803 "0x%" PRIx32
", count 0x%x",
805 return ERROR_JTAG_DEVICE_ERROR
;
809 buffer
+= nbytes
>> 1;
810 writecount
-= nbytes
>> 1;
812 } while (writecount
);
819 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
821 int retval
= ERROR_OK
;
824 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
826 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
830 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
832 memcpy(&svalue
, buffer
, sizeof(uint16_t));
833 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
834 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
835 retval
= jtagdp_transaction_endcheck(swjdp
);
844 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
845 uint8_t *buffer
, int count
, uint32_t address
)
847 int retval
= ERROR_OK
;
848 int wcount
, blocksize
, writecount
, i
;
850 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
858 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
859 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
861 if (wcount
< blocksize
)
864 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
865 writecount
= blocksize
;
869 nbytes
= MIN(writecount
, 4);
873 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
875 LOG_WARNING("Block write error address "
876 "0x%" PRIx32
", count 0x%x",
878 return ERROR_JTAG_DEVICE_ERROR
;
886 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
888 for (i
= 0; i
< nbytes
; i
++)
890 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
895 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
896 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
897 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
899 LOG_WARNING("Block write error address "
900 "0x%" PRIx32
", count 0x%x",
902 return ERROR_JTAG_DEVICE_ERROR
;
907 writecount
-= nbytes
;
909 } while (writecount
);
916 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
918 int retval
= ERROR_OK
;
921 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
923 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
927 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
928 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
929 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
930 retval
= jtagdp_transaction_endcheck(swjdp
);
939 /*********************************************************************************
941 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
943 * Read block fast in target order (little endian) into a buffer *
945 **********************************************************************************/
946 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
948 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
949 uint32_t adr
= address
;
950 uint8_t* pBuffer
= buffer
;
952 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
959 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
960 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
961 if (wcount
< blocksize
)
964 /* handle unaligned data at 4k boundary */
968 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
970 /* Scan out first read */
971 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
972 DPAP_READ
, 0, NULL
, NULL
);
973 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
975 /* Scan out next read; scan in posted value for the
976 * previous one. Assumes read is acked "OK/FAULT",
977 * and CTRL_STAT says that meant "OK".
979 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
980 DPAP_READ
, 0, buffer
+ 4 * readcount
,
984 /* Scan in last posted value; RDBUFF has no other effect,
985 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
987 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
988 DPAP_READ
, 0, buffer
+ 4 * readcount
,
990 if (jtagdp_transaction_endcheck(swjdp
) == ERROR_OK
)
992 wcount
= wcount
- blocksize
;
993 address
+= 4 * blocksize
;
994 buffer
+= 4 * blocksize
;
1003 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1004 return ERROR_JTAG_DEVICE_ERROR
;
1008 /* if we have an unaligned access - reorder data */
1011 for (readcount
= 0; readcount
< count
; readcount
++)
1015 memcpy(&data
, pBuffer
, sizeof(uint32_t));
1017 for (i
= 0; i
< 4; i
++)
1019 *((uint8_t*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
1029 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
1030 uint8_t *buffer
, int count
, uint32_t address
)
1033 int retval
= ERROR_OK
;
1034 int wcount
, blocksize
, readcount
, i
;
1036 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1038 wcount
= count
>> 1;
1044 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1045 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1046 if (wcount
< blocksize
)
1049 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
1051 /* handle unaligned data at 4k boundary */
1054 readcount
= blocksize
;
1058 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1059 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
1061 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1062 return ERROR_JTAG_DEVICE_ERROR
;
1065 nbytes
= MIN((readcount
<< 1), 4);
1067 for (i
= 0; i
< nbytes
; i
++)
1069 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1074 readcount
-= (nbytes
>> 1);
1075 } while (readcount
);
1076 wcount
-= blocksize
;
1082 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
1084 uint32_t invalue
, i
;
1085 int retval
= ERROR_OK
;
1088 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
1090 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1094 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
1095 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1096 retval
= jtagdp_transaction_endcheck(swjdp
);
1099 for (i
= 0; i
< 2; i
++)
1101 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1108 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
1109 memcpy(buffer
, &svalue
, sizeof(uint16_t));
1119 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1120 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1122 * The solution is to arrange for a large out/in scan in this loop and
1123 * and convert data afterwards.
1125 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
1126 uint8_t *buffer
, int count
, uint32_t address
)
1129 int retval
= ERROR_OK
;
1130 int wcount
, blocksize
, readcount
, i
;
1132 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1140 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1141 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1143 if (wcount
< blocksize
)
1146 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
1147 readcount
= blocksize
;
1151 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1152 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
1154 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1155 return ERROR_JTAG_DEVICE_ERROR
;
1158 nbytes
= MIN(readcount
, 4);
1160 for (i
= 0; i
< nbytes
; i
++)
1162 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1167 readcount
-= nbytes
;
1168 } while (readcount
);
1169 wcount
-= blocksize
;
1175 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
1178 int retval
= ERROR_OK
;
1181 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1183 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1187 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1188 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1189 retval
= jtagdp_transaction_endcheck(swjdp
);
1190 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1200 * Initialize a DAP. This sets up the power domains, prepares the DP
1201 * for further use, and arranges to use AP #0 for all AP operations
1202 * until dap_ap-select() changes that policy.
1204 * @param swjdp The DAP being initialized.
1206 * @todo Rename this. We also need an initialization scheme which account
1207 * for SWD transports not just JTAG; that will need to address differences
1208 * in layering. (JTAG is useful without any debug target; but not SWD.)
1209 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1211 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1213 uint32_t idreg
, romaddr
, dummy
;
1220 /* Default MEM-AP setup.
1222 * REVISIT AP #0 may be an inappropriate default for this.
1223 * Should we probe, or take a hint from the caller?
1224 * Presumably we can ignore the possibility of multiple APs.
1227 dap_ap_select(swjdp
, 0);
1229 /* DP initialization */
1230 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
1231 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1232 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
1233 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1235 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1237 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1238 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1239 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1242 /* Check that we have debug power domains activated */
1243 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1245 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1246 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1247 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1252 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1254 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1255 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1256 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1261 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1262 /* With debug power on we can activate OVERRUN checking */
1263 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1264 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1265 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1268 * REVISIT this isn't actually *initializing* anything in an AP,
1269 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1270 * Should it? If the ROM address is valid, is this the right
1271 * place to scan the table and do any topology detection?
1273 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1274 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1276 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1277 ", Debug ROM Address 0x%" PRIx32
,
1278 swjdp
->apsel
, idreg
, romaddr
);
1283 /* CID interpretation -- see ARM IHI 0029B section 3
1284 * and ARM IHI 0031A table 13-3.
1286 static const char *class_description
[16] ={
1287 "Reserved", "ROM table", "Reserved", "Reserved",
1288 "Reserved", "Reserved", "Reserved", "Reserved",
1289 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1290 "Reserved", "OptimoDE DESS",
1291 "Generic IP component", "PrimeCell or System component"
1295 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1297 return cid3
== 0xb1 && cid2
== 0x05
1298 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1301 int dap_info_command(struct command_context
*cmd_ctx
,
1302 struct swjdp_common
*swjdp
, int apsel
)
1305 uint32_t dbgbase
, apid
;
1306 int romtable_present
= 0;
1310 /* AP address is in bits 31:24 of DP_SELECT */
1312 return ERROR_INVALID_ARGUMENTS
;
1314 apselold
= swjdp
->apsel
;
1315 dap_ap_select(swjdp
, apsel
);
1316 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1317 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1318 jtagdp_transaction_endcheck(swjdp
);
1319 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1320 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1321 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1327 command_print(cmd_ctx
, "\tType is JTAG-AP");
1330 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1333 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1336 command_print(cmd_ctx
, "\tUnknown AP type");
1340 /* NOTE: a MEM-AP may have a single CoreSight component that's
1341 * not a ROM table ... or have no such components at all.
1344 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1349 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1352 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1353 if (romtable_present
)
1355 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1356 uint16_t entry_offset
;
1358 /* bit 16 of apid indicates a memory access port */
1360 command_print(cmd_ctx
, "\tValid ROM table present");
1362 command_print(cmd_ctx
, "\tROM table in legacy format");
1364 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1365 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1366 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1367 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1368 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1369 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1370 jtagdp_transaction_endcheck(swjdp
);
1371 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1372 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1373 ", CID2 0x%2.2" PRIx32
1374 ", CID1 0x%2.2" PRIx32
1375 ", CID0 0x%2.2" PRIx32
,
1376 cid3
, cid2
, cid1
, cid0
);
1378 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1380 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1381 "Dedicated debug bus.");
1383 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1387 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1388 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1391 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1392 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1393 uint32_t component_start
, component_base
;
1397 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1398 + (int)(romentry
& 0xFFFFF000));
1399 mem_ap_read_atomic_u32(swjdp
,
1400 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1401 mem_ap_read_atomic_u32(swjdp
,
1402 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1403 mem_ap_read_atomic_u32(swjdp
,
1404 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1405 mem_ap_read_atomic_u32(swjdp
,
1406 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1407 mem_ap_read_atomic_u32(swjdp
,
1408 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1409 mem_ap_read_atomic_u32(swjdp
,
1410 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1411 mem_ap_read_atomic_u32(swjdp
,
1412 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1413 mem_ap_read_atomic_u32(swjdp
,
1414 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1415 mem_ap_read_atomic_u32(swjdp
,
1416 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1417 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1419 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1420 ", start address 0x%" PRIx32
,
1421 component_base
, component_start
);
1422 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1423 (int) (c_cid1
>> 4) & 0xf,
1424 /* See ARM IHI 0029B Table 3-3 */
1425 class_description
[(c_cid1
>> 4) & 0xf]);
1427 /* CoreSight component? */
1428 if (((c_cid1
>> 4) & 0x0f) == 9) {
1431 char *major
= "Reserved", *subtype
= "Reserved";
1433 mem_ap_read_atomic_u32(swjdp
,
1434 (component_base
& 0xfffff000) | 0xfcc,
1436 minor
= (devtype
>> 4) & 0x0f;
1437 switch (devtype
& 0x0f) {
1439 major
= "Miscellaneous";
1445 subtype
= "Validation component";
1450 major
= "Trace Sink";
1464 major
= "Trace Link";
1470 subtype
= "Funnel, router";
1476 subtype
= "FIFO, buffer";
1481 major
= "Trace Source";
1487 subtype
= "Processor";
1493 subtype
= "Engine/Coprocessor";
1501 major
= "Debug Control";
1507 subtype
= "Trigger Matrix";
1510 subtype
= "Debug Auth";
1515 major
= "Debug Logic";
1521 subtype
= "Processor";
1527 subtype
= "Engine/Coprocessor";
1532 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1533 (unsigned) (devtype
& 0xff),
1535 /* REVISIT also show 0xfc8 DevId */
1538 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1539 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1540 ", CID2 0x%2.2" PRIx32
1541 ", CID1 0x%2.2" PRIx32
1542 ", CID0 0x%2.2" PRIx32
,
1543 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1544 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1545 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1547 (int) c_pid3
, (int) c_pid2
,
1548 (int) c_pid1
, (int) c_pid0
);
1550 /* Part number interpretations are from Cortex
1551 * core specs, the CoreSight components TRM
1552 * (ARM DDI 0314H), and ETM specs; also from
1553 * chip observation (e.g. TI SDTI).
1555 part_num
= c_pid0
& 0xff;
1556 part_num
|= (c_pid1
& 0x0f) << 8;
1559 type
= "Cortex-M3 NVIC";
1560 full
= "(Interrupt Controller)";
1563 type
= "Cortex-M3 ITM";
1564 full
= "(Instrumentation Trace Module)";
1567 type
= "Cortex-M3 DWT";
1568 full
= "(Data Watchpoint and Trace)";
1571 type
= "Cortex-M3 FBP";
1572 full
= "(Flash Patch and Breakpoint)";
1575 type
= "CoreSight ETM11";
1576 full
= "(Embedded Trace)";
1578 // case 0x113: what?
1579 case 0x120: /* from OMAP3 memmap */
1581 full
= "(System Debug Trace Interface)";
1583 case 0x343: /* from OMAP3 memmap */
1588 type
= "Cortex-M3 ETM";
1589 full
= "(Embedded Trace)";
1592 type
= "Coresight CTI";
1593 full
= "(Cross Trigger)";
1596 type
= "Coresight ETB";
1597 full
= "(Trace Buffer)";
1600 type
= "Coresight CSTF";
1601 full
= "(Trace Funnel)";
1604 type
= "CoreSight ETM9";
1605 full
= "(Embedded Trace)";
1608 type
= "Coresight TPIU";
1609 full
= "(Trace Port Interface Unit)";
1612 type
= "Cortex-A8 ETM";
1613 full
= "(Embedded Trace)";
1616 type
= "Cortex-A8 CTI";
1617 full
= "(Cross Trigger)";
1620 type
= "Cortex-M3 TPIU";
1621 full
= "(Trace Port Interface Unit)";
1624 type
= "Cortex-A8 Debug";
1625 full
= "(Debug Unit)";
1628 type
= "-*- unrecognized -*-";
1632 command_print(cmd_ctx
, "\t\tPart is %s %s",
1638 command_print(cmd_ctx
, "\t\tComponent not present");
1640 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1643 } while (romentry
> 0);
1647 command_print(cmd_ctx
, "\tNo ROM table present");
1649 dap_ap_select(swjdp
, apselold
);
1654 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1656 uint32_t apsel
, apselsave
, baseaddr
;
1659 apselsave
= swjdp
->apsel
;
1662 apsel
= swjdp
->apsel
;
1665 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1666 /* AP address is in bits 31:24 of DP_SELECT */
1668 return ERROR_INVALID_ARGUMENTS
;
1671 return ERROR_COMMAND_SYNTAX_ERROR
;
1674 if (apselsave
!= apsel
)
1675 dap_ap_select(swjdp
, apsel
);
1677 /* NOTE: assumes we're talking to a MEM-AP, which
1678 * has a base address. There are other kinds of AP,
1679 * though they're not common for now. This should
1680 * use the ID register to verify it's a MEM-AP.
1682 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1683 retval
= jtagdp_transaction_endcheck(swjdp
);
1684 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1686 if (apselsave
!= apsel
)
1687 dap_ap_select(swjdp
, apselsave
);
1692 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1694 uint32_t memaccess_tck
;
1698 memaccess_tck
= swjdp
->memaccess_tck
;
1701 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1704 return ERROR_COMMAND_SYNTAX_ERROR
;
1706 swjdp
->memaccess_tck
= memaccess_tck
;
1708 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1709 swjdp
->memaccess_tck
);
1714 DAP_COMMAND_HANDLER(dap_apsel_command
)
1716 uint32_t apsel
, apid
;
1724 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1725 /* AP address is in bits 31:24 of DP_SELECT */
1727 return ERROR_INVALID_ARGUMENTS
;
1730 return ERROR_COMMAND_SYNTAX_ERROR
;
1733 dap_ap_select(swjdp
, apsel
);
1734 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1735 retval
= jtagdp_transaction_endcheck(swjdp
);
1736 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1742 DAP_COMMAND_HANDLER(dap_apid_command
)
1744 uint32_t apsel
, apselsave
, apid
;
1747 apselsave
= swjdp
->apsel
;
1750 apsel
= swjdp
->apsel
;
1753 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1754 /* AP address is in bits 31:24 of DP_SELECT */
1756 return ERROR_INVALID_ARGUMENTS
;
1759 return ERROR_COMMAND_SYNTAX_ERROR
;
1762 if (apselsave
!= apsel
)
1763 dap_ap_select(swjdp
, apsel
);
1765 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1766 retval
= jtagdp_transaction_endcheck(swjdp
);
1767 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1768 if (apselsave
!= apsel
)
1769 dap_ap_select(swjdp
, apselsave
);