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ARM: ADIv5 export cleanup
[openocd/ellerodev.git] / src / target / arm_adi_v5.c
blob19154ce6aa47ded5bab6fe26bc5103f4548acc8b
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 /**
28 * @file
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
34 *
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
43 */
44
45 /*
46 * Relevant specifications from ARM include:
47 *
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
50 *
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
53 */
54
55 #ifdef HAVE_CONFIG_H
56 #include "config.h"
57 #endif
58
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
61
62 /*
63 * Transaction Mode:
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
71 */
72
73
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
75
76 /*
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
79 */
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
81 {
82 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
83 }
84
85 /***************************************************************************
86 * *
87 * DPACC and APACC scanchain access through JTAG-DP *
88 * *
89 ***************************************************************************/
90
91 /* Scan out and in from target ordered uint8_t buffers */
92 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
93 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
94 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
95 {
96 struct arm_jtag *jtag_info = swjdp->jtag_info;
97 struct scan_field fields[2];
98 uint8_t out_addr_buf;
99
100 jtag_set_end_state(TAP_IDLE);
101 arm_jtag_set_instr(jtag_info, instr, NULL);
102
103 /* Add specified number of tck clocks before accessing memory bus */
104 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
105 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
106
107 fields[0].tap = jtag_info->tap;
108 fields[0].num_bits = 3;
109 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
110 fields[0].out_value = &out_addr_buf;
111 fields[0].in_value = ack;
112
113 fields[1].tap = jtag_info->tap;
114 fields[1].num_bits = 32;
115 fields[1].out_value = outvalue;
116 fields[1].in_value = invalue;
117
118 jtag_add_dr_scan(2, fields, jtag_get_end_state());
119
120 return ERROR_OK;
121 }
122
123 /* Scan out and in from host ordered uint32_t variables */
124 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
125 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
126 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
127 {
128 struct arm_jtag *jtag_info = swjdp->jtag_info;
129 struct scan_field fields[2];
130 uint8_t out_value_buf[4];
131 uint8_t out_addr_buf;
132
133 jtag_set_end_state(TAP_IDLE);
134 arm_jtag_set_instr(jtag_info, instr, NULL);
135
136 /* Add specified number of tck clocks before accessing memory bus */
137 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
138 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
139
140 fields[0].tap = jtag_info->tap;
141 fields[0].num_bits = 3;
142 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
143 fields[0].out_value = &out_addr_buf;
144 fields[0].in_value = ack;
145
146 fields[1].tap = jtag_info->tap;
147 fields[1].num_bits = 32;
148 buf_set_u32(out_value_buf, 0, 32, outvalue);
149 fields[1].out_value = out_value_buf;
150 fields[1].in_value = NULL;
151
152 if (invalue)
153 {
154 fields[1].in_value = (uint8_t *)invalue;
155 jtag_add_dr_scan(2, fields, jtag_get_end_state());
156
157 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
158 } else
159 {
160
161 jtag_add_dr_scan(2, fields, jtag_get_end_state());
162 }
163
164 return ERROR_OK;
165 }
166
167 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
168 static int scan_inout_check(struct swjdp_common *swjdp,
169 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
170 uint8_t *outvalue, uint8_t *invalue)
171 {
172 adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
173
174 if ((RnW == DPAP_READ) && (invalue != NULL))
175 {
176 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
177 }
178
179 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
180 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
181 {
182 return swjdp_transaction_endcheck(swjdp);
183 }
184
185 return ERROR_OK;
186 }
187
188 static int scan_inout_check_u32(struct swjdp_common *swjdp,
189 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
190 uint32_t outvalue, uint32_t *invalue)
191 {
192 adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
193
194 if ((RnW == DPAP_READ) && (invalue != NULL))
195 {
196 adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
197 }
198
199 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
200 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
201 {
202 return swjdp_transaction_endcheck(swjdp);
203 }
204
205 return ERROR_OK;
206 }
207
208 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
209 {
210 int retval;
211 uint32_t ctrlstat;
212
213 /* too expensive to call keep_alive() here */
214
215 #if 0
216 /* Danger!!!! BROKEN!!!! */
217 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
218 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
219 R956 introduced the check on return value here and now Michael Schwingen reports
220 that this code no longer works....
221
222 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
223 */
224 if ((retval = jtag_execute_queue()) != ERROR_OK)
225 {
226 LOG_ERROR("BUG: Why does this fail the first time????");
227 }
228 /* Why??? second time it works??? */
229 #endif
230
231 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
232 if ((retval = jtag_execute_queue()) != ERROR_OK)
233 return retval;
234
235 swjdp->ack = swjdp->ack & 0x7;
236
237 if (swjdp->ack != 2)
238 {
239 long long then = timeval_ms();
240 while (swjdp->ack != 2)
241 {
242 if (swjdp->ack == 1)
243 {
244 if ((timeval_ms()-then) > 1000)
245 {
246 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
247 return ERROR_JTAG_DEVICE_ERROR;
248 }
249 }
250 else
251 {
252 LOG_WARNING("Invalid ACK in SWJDP transaction");
253 return ERROR_JTAG_DEVICE_ERROR;
254 }
255
256 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
257 if ((retval = jtag_execute_queue()) != ERROR_OK)
258 return retval;
259 swjdp->ack = swjdp->ack & 0x7;
260 }
261 } else
262 {
263 /* common code path avoids fn to timeval_ms() */
264 }
265
266 /* Check for STICKYERR and STICKYORUN */
267 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
268 {
269 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
270 /* Check power to debug regions */
271 if ((ctrlstat & 0xf0000000) != 0xf0000000)
272 {
273 ahbap_debugport_init(swjdp);
274 }
275 else
276 {
277 uint32_t mem_ap_csw, mem_ap_tar;
278
279 /* Print information about last AHBAP access */
280 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
281 if (ctrlstat & SSTICKYORUN)
282 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
283
284 if (ctrlstat & SSTICKYERR)
285 LOG_ERROR("SWJ-DP STICKY ERROR");
286
287 /* Clear Sticky Error Bits */
288 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
289 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
290 if ((retval = jtag_execute_queue()) != ERROR_OK)
291 return retval;
292
293 LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
294
295 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
296 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
297 if ((retval = jtag_execute_queue()) != ERROR_OK)
298 return retval;
299 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
300
301 }
302 if ((retval = jtag_execute_queue()) != ERROR_OK)
303 return retval;
304 return ERROR_JTAG_DEVICE_ERROR;
305 }
306
307 return ERROR_OK;
308 }
309
310 /***************************************************************************
311 * *
312 * DP and MEM-AP register access through APACC and DPACC *
313 * *
314 ***************************************************************************/
315
316 static int dap_dp_write_reg(struct swjdp_common *swjdp,
317 uint32_t value, uint8_t reg_addr)
318 {
319 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
320 }
321
322 static int dap_dp_read_reg(struct swjdp_common *swjdp,
323 uint32_t *value, uint8_t reg_addr)
324 {
325 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
326 }
327
328 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
329 {
330 uint32_t select;
331 select = (apsel << 24) & 0xFF000000;
332
333 if (select != swjdp->apsel)
334 {
335 swjdp->apsel = select;
336 /* Switching AP invalidates cached values */
337 swjdp->dp_select_value = -1;
338 swjdp->ap_csw_value = -1;
339 swjdp->ap_tar_value = -1;
340 }
341
342 return ERROR_OK;
343 }
344
345 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
346 {
347 uint32_t select;
348 select = (ap_reg & 0x000000F0);
349
350 if (select != swjdp->dp_select_value)
351 {
352 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
353 swjdp->dp_select_value = select;
354 }
355
356 return ERROR_OK;
357 }
358
359 static int dap_ap_write_reg(struct swjdp_common *swjdp,
360 uint32_t reg_addr, uint8_t *out_value_buf)
361 {
362 dap_dp_bankselect(swjdp, reg_addr);
363 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
364
365 return ERROR_OK;
366 }
367
368 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
369 {
370 uint8_t out_value_buf[4];
371
372 buf_set_u32(out_value_buf, 0, 32, value);
373 dap_dp_bankselect(swjdp, reg_addr);
374 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
375
376 return ERROR_OK;
377 }
378
379 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
380 {
381 dap_dp_bankselect(swjdp, reg_addr);
382 scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
383
384 return ERROR_OK;
385 }
386
387 /***************************************************************************
388 * *
389 * AHB-AP access to memory and system registers on AHB bus *
390 * *
391 ***************************************************************************/
392
393 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
394 {
395 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
396 if (csw != swjdp->ap_csw_value)
397 {
398 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
399 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
400 swjdp->ap_csw_value = csw;
401 }
402 if (tar != swjdp->ap_tar_value)
403 {
404 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
405 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
406 swjdp->ap_tar_value = tar;
407 }
408 if (csw & CSW_ADDRINC_MASK)
409 {
410 /* Do not cache TAR value when autoincrementing */
411 swjdp->ap_tar_value = -1;
412 }
413 return ERROR_OK;
414 }
415
416 /*****************************************************************************
417 * *
418 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
419 * *
420 * Read a uint32_t value from memory or system register *
421 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
422 * but with less overhead *
423 *****************************************************************************/
424 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
425 {
426 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
427
428 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
429 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
430
431 return ERROR_OK;
432 }
433
434 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
435 {
436 mem_ap_read_u32(swjdp, address, value);
437
438 return swjdp_transaction_endcheck(swjdp);
439 }
440
441 /*****************************************************************************
442 * *
443 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
444 * *
445 * Write a uint32_t value to memory or memory mapped register *
446 * *
447 *****************************************************************************/
448 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
449 {
450 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
451
452 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
453 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
454
455 return ERROR_OK;
456 }
457
458 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
459 {
460 mem_ap_write_u32(swjdp, address, value);
461
462 return swjdp_transaction_endcheck(swjdp);
463 }
464
465 /*****************************************************************************
466 * *
467 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
468 * *
469 * Write a buffer in target order (little endian) *
470 * *
471 *****************************************************************************/
472 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
473 {
474 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
475 uint32_t adr = address;
476 uint8_t* pBuffer = buffer;
477
478 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
479
480 count >>= 2;
481 wcount = count;
482
483 /* if we have an unaligned access - reorder data */
484 if (adr & 0x3u)
485 {
486 for (writecount = 0; writecount < count; writecount++)
487 {
488 int i;
489 uint32_t outvalue;
490 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
491
492 for (i = 0; i < 4; i++)
493 {
494 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
495 outvalue >>= 8;
496 adr++;
497 }
498 pBuffer += sizeof(uint32_t);
499 }
500 }
501
502 while (wcount > 0)
503 {
504 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
505 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
506 if (wcount < blocksize)
507 blocksize = wcount;
508
509 /* handle unaligned data at 4k boundary */
510 if (blocksize == 0)
511 blocksize = 1;
512
513 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
514
515 for (writecount = 0; writecount < blocksize; writecount++)
516 {
517 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
518 }
519
520 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
521 {
522 wcount = wcount - blocksize;
523 address = address + 4 * blocksize;
524 buffer = buffer + 4 * blocksize;
525 }
526 else
527 {
528 errorcount++;
529 }
530
531 if (errorcount > 1)
532 {
533 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
534 return ERROR_JTAG_DEVICE_ERROR;
535 }
536 }
537
538 return retval;
539 }
540
541 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
542 uint8_t *buffer, int count, uint32_t address)
543 {
544 int retval = ERROR_OK;
545 int wcount, blocksize, writecount, i;
546
547 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
548
549 wcount = count >> 1;
550
551 while (wcount > 0)
552 {
553 int nbytes;
554
555 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
556 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
557
558 if (wcount < blocksize)
559 blocksize = wcount;
560
561 /* handle unaligned data at 4k boundary */
562 if (blocksize == 0)
563 blocksize = 1;
564
565 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
566 writecount = blocksize;
567
568 do
569 {
570 nbytes = MIN((writecount << 1), 4);
571
572 if (nbytes < 4)
573 {
574 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
575 {
576 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
577 return ERROR_JTAG_DEVICE_ERROR;
578 }
579
580 address += nbytes >> 1;
581 }
582 else
583 {
584 uint32_t outvalue;
585 memcpy(&outvalue, buffer, sizeof(uint32_t));
586
587 for (i = 0; i < nbytes; i++)
588 {
589 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
590 outvalue >>= 8;
591 address++;
592 }
593
594 memcpy(&outvalue, buffer, sizeof(uint32_t));
595 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
596 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
597 {
598 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
599 return ERROR_JTAG_DEVICE_ERROR;
600 }
601 }
602
603 buffer += nbytes >> 1;
604 writecount -= nbytes >> 1;
605
606 } while (writecount);
607 wcount -= blocksize;
608 }
609
610 return retval;
611 }
612
613 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
614 {
615 int retval = ERROR_OK;
616
617 if (count >= 4)
618 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
619
620 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
621
622 while (count > 0)
623 {
624 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
625 uint16_t svalue;
626 memcpy(&svalue, buffer, sizeof(uint16_t));
627 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
628 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
629 retval = swjdp_transaction_endcheck(swjdp);
630 count -= 2;
631 address += 2;
632 buffer += 2;
633 }
634
635 return retval;
636 }
637
638 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
639 uint8_t *buffer, int count, uint32_t address)
640 {
641 int retval = ERROR_OK;
642 int wcount, blocksize, writecount, i;
643
644 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
645
646 wcount = count;
647
648 while (wcount > 0)
649 {
650 int nbytes;
651
652 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
653 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
654
655 if (wcount < blocksize)
656 blocksize = wcount;
657
658 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
659 writecount = blocksize;
660
661 do
662 {
663 nbytes = MIN(writecount, 4);
664
665 if (nbytes < 4)
666 {
667 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
668 {
669 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
670 return ERROR_JTAG_DEVICE_ERROR;
671 }
672
673 address += nbytes;
674 }
675 else
676 {
677 uint32_t outvalue;
678 memcpy(&outvalue, buffer, sizeof(uint32_t));
679
680 for (i = 0; i < nbytes; i++)
681 {
682 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
683 outvalue >>= 8;
684 address++;
685 }
686
687 memcpy(&outvalue, buffer, sizeof(uint32_t));
688 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
689 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
690 {
691 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
692 return ERROR_JTAG_DEVICE_ERROR;
693 }
694 }
695
696 buffer += nbytes;
697 writecount -= nbytes;
698
699 } while (writecount);
700 wcount -= blocksize;
701 }
702
703 return retval;
704 }
705
706 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
707 {
708 int retval = ERROR_OK;
709
710 if (count >= 4)
711 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
712
713 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
714
715 while (count > 0)
716 {
717 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
718 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
719 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
720 retval = swjdp_transaction_endcheck(swjdp);
721 count--;
722 address++;
723 buffer++;
724 }
725
726 return retval;
727 }
728
729 /*********************************************************************************
730 * *
731 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
732 * *
733 * Read block fast in target order (little endian) into a buffer *
734 * *
735 **********************************************************************************/
736 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
737 {
738 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
739 uint32_t adr = address;
740 uint8_t* pBuffer = buffer;
741
742 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
743
744 count >>= 2;
745 wcount = count;
746
747 while (wcount > 0)
748 {
749 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
750 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
751 if (wcount < blocksize)
752 blocksize = wcount;
753
754 /* handle unaligned data at 4k boundary */
755 if (blocksize == 0)
756 blocksize = 1;
757
758 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
759
760 /* Scan out first read */
761 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
762 for (readcount = 0; readcount < blocksize - 1; readcount++)
763 {
764 /* Scan out read instruction and scan in previous value */
765 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
766 }
767
768 /* Scan in last value */
769 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
770 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
771 {
772 wcount = wcount - blocksize;
773 address += 4 * blocksize;
774 buffer += 4 * blocksize;
775 }
776 else
777 {
778 errorcount++;
779 }
780
781 if (errorcount > 1)
782 {
783 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
784 return ERROR_JTAG_DEVICE_ERROR;
785 }
786 }
787
788 /* if we have an unaligned access - reorder data */
789 if (adr & 0x3u)
790 {
791 for (readcount = 0; readcount < count; readcount++)
792 {
793 int i;
794 uint32_t data;
795 memcpy(&data, pBuffer, sizeof(uint32_t));
796
797 for (i = 0; i < 4; i++)
798 {
799 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
800 pBuffer++;
801 adr++;
802 }
803 }
804 }
805
806 return retval;
807 }
808
809 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
810 uint8_t *buffer, int count, uint32_t address)
811 {
812 uint32_t invalue;
813 int retval = ERROR_OK;
814 int wcount, blocksize, readcount, i;
815
816 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
817
818 wcount = count >> 1;
819
820 while (wcount > 0)
821 {
822 int nbytes;
823
824 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
825 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
826 if (wcount < blocksize)
827 blocksize = wcount;
828
829 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
830
831 /* handle unaligned data at 4k boundary */
832 if (blocksize == 0)
833 blocksize = 1;
834 readcount = blocksize;
835
836 do
837 {
838 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
839 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
840 {
841 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
842 return ERROR_JTAG_DEVICE_ERROR;
843 }
844
845 nbytes = MIN((readcount << 1), 4);
846
847 for (i = 0; i < nbytes; i++)
848 {
849 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
850 buffer++;
851 address++;
852 }
853
854 readcount -= (nbytes >> 1);
855 } while (readcount);
856 wcount -= blocksize;
857 }
858
859 return retval;
860 }
861
862 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
863 {
864 uint32_t invalue, i;
865 int retval = ERROR_OK;
866
867 if (count >= 4)
868 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
869
870 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
871
872 while (count > 0)
873 {
874 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
875 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
876 retval = swjdp_transaction_endcheck(swjdp);
877 if (address & 0x1)
878 {
879 for (i = 0; i < 2; i++)
880 {
881 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
882 buffer++;
883 address++;
884 }
885 }
886 else
887 {
888 uint16_t svalue = (invalue >> 8 * (address & 0x3));
889 memcpy(buffer, &svalue, sizeof(uint16_t));
890 address += 2;
891 buffer += 2;
892 }
893 count -= 2;
894 }
895
896 return retval;
897 }
898
899 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
900 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
901 *
902 * The solution is to arrange for a large out/in scan in this loop and
903 * and convert data afterwards.
904 */
905 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
906 uint8_t *buffer, int count, uint32_t address)
907 {
908 uint32_t invalue;
909 int retval = ERROR_OK;
910 int wcount, blocksize, readcount, i;
911
912 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
913
914 wcount = count;
915
916 while (wcount > 0)
917 {
918 int nbytes;
919
920 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
921 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
922
923 if (wcount < blocksize)
924 blocksize = wcount;
925
926 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
927 readcount = blocksize;
928
929 do
930 {
931 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
932 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
933 {
934 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
935 return ERROR_JTAG_DEVICE_ERROR;
936 }
937
938 nbytes = MIN(readcount, 4);
939
940 for (i = 0; i < nbytes; i++)
941 {
942 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
943 buffer++;
944 address++;
945 }
946
947 readcount -= nbytes;
948 } while (readcount);
949 wcount -= blocksize;
950 }
951
952 return retval;
953 }
954
955 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
956 {
957 uint32_t invalue;
958 int retval = ERROR_OK;
959
960 if (count >= 4)
961 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
962
963 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
964
965 while (count > 0)
966 {
967 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
968 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
969 retval = swjdp_transaction_endcheck(swjdp);
970 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
971 count--;
972 address++;
973 buffer++;
974 }
975
976 return retval;
977 }
978
979 /**
980 * Initialize a DAP.
981 *
982 * @todo Rename this. We also need an initialization scheme which account
983 * for SWD transports not just JTAG; that will need to address differences
984 * in layering. (JTAG is useful without any debug target; but not SWD.)
985 */
986 int ahbap_debugport_init(struct swjdp_common *swjdp)
987 {
988 uint32_t idreg, romaddr, dummy;
989 uint32_t ctrlstat;
990 int cnt = 0;
991 int retval;
992
993 LOG_DEBUG(" ");
994
995 /* Default MEM-AP setup.
996 *
997 * REVISIT AP #0 may be an inappropriate default for this.
998 * Should we probe, or receve a hint from the caller?
999 * Presumably we can ignore the possibility of multiple APs.
1000 */
1001 swjdp->apsel = 0;
1002 swjdp->ap_csw_value = -1;
1003 swjdp->ap_tar_value = -1;
1004
1005 /* DP initialization */
1006 swjdp->trans_mode = TRANS_MODE_ATOMIC;
1007 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1008 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1009 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1010
1011 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1012
1013 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1014 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1015 if ((retval = jtag_execute_queue()) != ERROR_OK)
1016 return retval;
1017
1018 /* Check that we have debug power domains activated */
1019 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1020 {
1021 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1022 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1023 if ((retval = jtag_execute_queue()) != ERROR_OK)
1024 return retval;
1025 alive_sleep(10);
1026 }
1027
1028 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1029 {
1030 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1031 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1032 if ((retval = jtag_execute_queue()) != ERROR_OK)
1033 return retval;
1034 alive_sleep(10);
1035 }
1036
1037 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1038 /* With debug power on we can activate OVERRUN checking */
1039 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1040 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1041 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1042
1043 /*
1044 * REVISIT this isn't actually *initializing* anything in an AP,
1045 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1046 * Should it? If the ROM address is valid, is this the right
1047 * place to scan the table and do any topology detection?
1048 */
1049 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1050 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1051
1052 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1053
1054 return ERROR_OK;
1055 }
1056
1057 /* CID interpretation -- see ARM IHI 0029B section 3
1058 * and ARM IHI 0031A table 13-3.
1059 */
1060 static const char *class_description[16] ={
1061 "Reserved", "ROM table", "Reserved", "Reserved",
1062 "Reserved", "Reserved", "Reserved", "Reserved",
1063 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1064 "Reserved", "OptimoDE DESS",
1065 "Generic IP component", "PrimeCell or System component"
1066 };
1067
1068 static bool
1069 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1070 {
1071 return cid3 == 0xb1 && cid2 == 0x05
1072 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1073 }
1074
1075 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1076 {
1077
1078 uint32_t dbgbase,apid;
1079 int romtable_present = 0;
1080 uint8_t mem_ap;
1081 uint32_t apselold;
1082
1083 apselold = swjdp->apsel;
1084 dap_ap_select(swjdp, apsel);
1085 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1086 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1087 swjdp_transaction_endcheck(swjdp);
1088 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1089 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1090 command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
1091 if (apid)
1092 {
1093 switch (apid&0x0F)
1094 {
1095 case 0:
1096 command_print(cmd_ctx, "\tType is jtag-ap");
1097 break;
1098 case 1:
1099 command_print(cmd_ctx, "\tType is mem-ap AHB");
1100 break;
1101 case 2:
1102 command_print(cmd_ctx, "\tType is mem-ap APB");
1103 break;
1104 default:
1105 command_print(cmd_ctx, "\tUnknown AP-type");
1106 break;
1107 }
1108 command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase);
1109 }
1110 else
1111 {
1112 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1113 }
1114
1115 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1116 if (romtable_present)
1117 {
1118 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1119 uint16_t entry_offset;
1120
1121 /* bit 16 of apid indicates a memory access port */
1122 if (dbgbase & 0x02)
1123 command_print(cmd_ctx, "\tValid ROM table present");
1124 else
1125 command_print(cmd_ctx, "\tROM table in legacy format");
1126
1127 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1128 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1129 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1130 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1131 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1132 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1133 swjdp_transaction_endcheck(swjdp);
1134 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1135 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1136 ", CID2 0x%2.2" PRIx32
1137 ", CID1 0x%2.2" PRIx32
1138 ", CID0 0x%2.2" PRIx32,
1139 cid3, cid2, cid1, cid0);
1140 if (memtype & 0x01)
1141 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1142 else
1143 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1144 "Dedicated debug bus.");
1145
1146 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1147 entry_offset = 0;
1148 do
1149 {
1150 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1151 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1152 if (romentry&0x01)
1153 {
1154 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1155 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1156 uint32_t component_start, component_base;
1157 unsigned part_num;
1158 char *type, *full;
1159
1160 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1161 + (int)(romentry & 0xFFFFF000));
1162 mem_ap_read_atomic_u32(swjdp,
1163 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1164 mem_ap_read_atomic_u32(swjdp,
1165 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1166 mem_ap_read_atomic_u32(swjdp,
1167 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1168 mem_ap_read_atomic_u32(swjdp,
1169 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1170 mem_ap_read_atomic_u32(swjdp,
1171 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1172 mem_ap_read_atomic_u32(swjdp,
1173 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1174 mem_ap_read_atomic_u32(swjdp,
1175 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1176 mem_ap_read_atomic_u32(swjdp,
1177 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1178 mem_ap_read_atomic_u32(swjdp,
1179 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1180 component_start = component_base - 0x1000*(c_pid4 >> 4);
1181
1182 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1183 ", start address 0x%" PRIx32,
1184 component_base, component_start);
1185 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1186 (int) (c_cid1 >> 4) & 0xf,
1187 /* See ARM IHI 0029B Table 3-3 */
1188 class_description[(c_cid1 >> 4) & 0xf]);
1189
1190 /* CoreSight component? */
1191 if (((c_cid1 >> 4) & 0x0f) == 9) {
1192 uint32_t devtype;
1193 unsigned minor;
1194 char *major = "Reserved", *subtype = "Reserved";
1195
1196 mem_ap_read_atomic_u32(swjdp,
1197 (component_base & 0xfffff000) | 0xfcc,
1198 &devtype);
1199 minor = (devtype >> 4) & 0x0f;
1200 switch (devtype & 0x0f) {
1201 case 0:
1202 major = "Miscellaneous";
1203 switch (minor) {
1204 case 0:
1205 subtype = "other";
1206 break;
1207 case 4:
1208 subtype = "Validation component";
1209 break;
1210 }
1211 break;
1212 case 1:
1213 major = "Trace Sink";
1214 switch (minor) {
1215 case 0:
1216 subtype = "other";
1217 break;
1218 case 1:
1219 subtype = "Port";
1220 break;
1221 case 2:
1222 subtype = "Buffer";
1223 break;
1224 }
1225 break;
1226 case 2:
1227 major = "Trace Link";
1228 switch (minor) {
1229 case 0:
1230 subtype = "other";
1231 break;
1232 case 1:
1233 subtype = "Funnel, router";
1234 break;
1235 case 2:
1236 subtype = "Filter";
1237 break;
1238 case 3:
1239 subtype = "FIFO, buffer";
1240 break;
1241 }
1242 break;
1243 case 3:
1244 major = "Trace Source";
1245 switch (minor) {
1246 case 0:
1247 subtype = "other";
1248 break;
1249 case 1:
1250 subtype = "Processor";
1251 break;
1252 case 2:
1253 subtype = "DSP";
1254 break;
1255 case 3:
1256 subtype = "Engine/Coprocessor";
1257 break;
1258 case 4:
1259 subtype = "Bus";
1260 break;
1261 }
1262 break;
1263 case 4:
1264 major = "Debug Control";
1265 switch (minor) {
1266 case 0:
1267 subtype = "other";
1268 break;
1269 case 1:
1270 subtype = "Trigger Matrix";
1271 break;
1272 case 2:
1273 subtype = "Debug Auth";
1274 break;
1275 }
1276 break;
1277 case 5:
1278 major = "Debug Logic";
1279 switch (minor) {
1280 case 0:
1281 subtype = "other";
1282 break;
1283 case 1:
1284 subtype = "Processor";
1285 break;
1286 case 2:
1287 subtype = "DSP";
1288 break;
1289 case 3:
1290 subtype = "Engine/Coprocessor";
1291 break;
1292 }
1293 break;
1294 }
1295 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1296 (unsigned) (devtype & 0xff),
1297 major, subtype);
1298 /* REVISIT also show 0xfc8 DevId */
1299 }
1300
1301 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1302 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1303 ", CID2 0x%2.2" PRIx32
1304 ", CID1 0x%2.2" PRIx32
1305 ", CID0 0x%2.2" PRIx32,
1306 c_cid3, c_cid2, c_cid1, c_cid0);
1307 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1308 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1309 (int) c_pid4,
1310 (int) c_pid3, (int) c_pid2,
1311 (int) c_pid1, (int) c_pid0);
1312
1313 /* Part number interpretations are from Cortex
1314 * core specs, the CoreSight components TRM
1315 * (ARM DDI 0314H), and ETM specs; also from
1316 * chip observation (e.g. TI SDTI).
1317 */
1318 part_num = c_pid0 & 0xff;
1319 part_num |= (c_pid1 & 0x0f) << 8;
1320 switch (part_num) {
1321 case 0x000:
1322 type = "Cortex-M3 NVIC";
1323 full = "(Interrupt Controller)";
1324 break;
1325 case 0x001:
1326 type = "Cortex-M3 ITM";
1327 full = "(Instrumentation Trace Module)";
1328 break;
1329 case 0x002:
1330 type = "Cortex-M3 DWT";
1331 full = "(Data Watchpoint and Trace)";
1332 break;
1333 case 0x003:
1334 type = "Cortex-M3 FBP";
1335 full = "(Flash Patch and Breakpoint)";
1336 break;
1337 case 0x00d:
1338 type = "CoreSight ETM11";
1339 full = "(Embedded Trace)";
1340 break;
1341 // case 0x113: what?
1342 case 0x120: /* from OMAP3 memmap */
1343 type = "TI SDTI";
1344 full = "(System Debug Trace Interface)";
1345 break;
1346 case 0x343: /* from OMAP3 memmap */
1347 type = "TI DAPCTL";
1348 full = "";
1349 break;
1350 case 0x4e0:
1351 type = "Cortex-M3 ETM";
1352 full = "(Embedded Trace)";
1353 break;
1354 case 0x906:
1355 type = "Coresight CTI";
1356 full = "(Cross Trigger)";
1357 break;
1358 case 0x907:
1359 type = "Coresight ETB";
1360 full = "(Trace Buffer)";
1361 break;
1362 case 0x908:
1363 type = "Coresight CSTF";
1364 full = "(Trace Funnel)";
1365 break;
1366 case 0x910:
1367 type = "CoreSight ETM9";
1368 full = "(Embedded Trace)";
1369 break;
1370 case 0x912:
1371 type = "Coresight TPIU";
1372 full = "(Trace Port Interface Unit)";
1373 break;
1374 case 0x921:
1375 type = "Cortex-A8 ETM";
1376 full = "(Embedded Trace)";
1377 break;
1378 case 0x922:
1379 type = "Cortex-A8 CTI";
1380 full = "(Cross Trigger)";
1381 break;
1382 case 0x923:
1383 type = "Cortex-M3 TPIU";
1384 full = "(Trace Port Interface Unit)";
1385 break;
1386 case 0xc08:
1387 type = "Cortex-A8 Debug";
1388 full = "(Debug Unit)";
1389 break;
1390 default:
1391 type = "-*- unrecognized -*-";
1392 full = "";
1393 break;
1394 }
1395 command_print(cmd_ctx, "\t\tPart is %s %s",
1396 type, full);
1397 }
1398 else
1399 {
1400 if (romentry)
1401 command_print(cmd_ctx, "\t\tComponent not present");
1402 else
1403 command_print(cmd_ctx, "\t\tEnd of ROM table");
1404 }
1405 entry_offset += 4;
1406 } while (romentry > 0);
1407 }
1408 else
1409 {
1410 command_print(cmd_ctx, "\tNo ROM table present");
1411 }
1412 dap_ap_select(swjdp, apselold);
1413
1414 return ERROR_OK;
1415 }
1416
1417 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1418 {
1419 uint32_t apsel, apselsave, baseaddr;
1420 int retval;
1421
1422 apselsave = swjdp->apsel;
1423 switch (CMD_ARGC) {
1424 case 0:
1425 apsel = swjdp->apsel;
1426 break;
1427 case 1:
1428 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1429 break;
1430 default:
1431 return ERROR_COMMAND_SYNTAX_ERROR;
1432 }
1433
1434 if (apselsave != apsel)
1435 dap_ap_select(swjdp, apsel);
1436
1437 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1438 retval = swjdp_transaction_endcheck(swjdp);
1439 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1440
1441 if (apselsave != apsel)
1442 dap_ap_select(swjdp, apselsave);
1443
1444 return retval;
1445 }
1446
1447 DAP_COMMAND_HANDLER(dap_memaccess_command)
1448 {
1449 uint32_t memaccess_tck;
1450
1451 switch (CMD_ARGC) {
1452 case 0:
1453 memaccess_tck = swjdp->memaccess_tck;
1454 break;
1455 case 1:
1456 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1457 break;
1458 default:
1459 return ERROR_COMMAND_SYNTAX_ERROR;
1460 }
1461 swjdp->memaccess_tck = memaccess_tck;
1462
1463 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1464 swjdp->memaccess_tck);
1465
1466 return ERROR_OK;
1467 }
1468
1469 DAP_COMMAND_HANDLER(dap_apsel_command)
1470 {
1471 uint32_t apsel, apid;
1472 int retval;
1473
1474 switch (CMD_ARGC) {
1475 case 0:
1476 apsel = 0;
1477 break;
1478 case 1:
1479 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1480 break;
1481 default:
1482 return ERROR_COMMAND_SYNTAX_ERROR;
1483 }
1484
1485 dap_ap_select(swjdp, apsel);
1486 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1487 retval = swjdp_transaction_endcheck(swjdp);
1488 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1489 apsel, apid);
1490
1491 return retval;
1492 }
1493
1494 DAP_COMMAND_HANDLER(dap_apid_command)
1495 {
1496 uint32_t apsel, apselsave, apid;
1497 int retval;
1498
1499 apselsave = swjdp->apsel;
1500 switch (CMD_ARGC) {
1501 case 0:
1502 apsel = swjdp->apsel;
1503 break;
1504 case 1:
1505 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1506 break;
1507 default:
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1509 }
1510
1511 if (apselsave != apsel)
1512 dap_ap_select(swjdp, apsel);
1513
1514 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1515 retval = swjdp_transaction_endcheck(swjdp);
1516 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1517 if (apselsave != apsel)
1518 dap_ap_select(swjdp, apselsave);
1519
1520 return retval;
1521 }
Luca's development patches