src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <jtag/interface.h>
  25 #include "bitbang.h"
  26
  27 #define TDO_BIT         1
  28 #define TDI_BIT         2
  29 #define TCK_BIT         4
  30 #define TMS_BIT         8
  31 #define TRST_BIT        16
  32 #define SRST_BIT        32
  33 #define VCC_BIT         64
  34
  35 #include <sys/mman.h>
  36
  37 static uint8_t output_value = 0x0;
  38 static int dev_mem_fd;
  39 static void *gpio_controller;
  40 static volatile uint8_t *gpio_data_register;
  41 static volatile uint8_t *gpio_data_direction_register;
  42
  43 /* low level command set
  44  */
  45 static int ep93xx_read(void);
  46 static void ep93xx_write(int tck, int tms, int tdi);
  47 static void ep93xx_reset(int trst, int srst);
  48
  49 static int ep93xx_speed(int speed);
  50 static int ep93xx_register_commands(struct command_context *cmd_ctx);
  51 static int ep93xx_init(void);
  52 static int ep93xx_quit(void);
  53
  54 struct timespec ep93xx_zzzz;
  55
  56 struct jtag_interface ep93xx_interface =
  57 {
  58         .name = "ep93xx",
  59
  60         .execute_queue = bitbang_execute_queue,
  61
  62         .speed = ep93xx_speed,
  63         .register_commands = ep93xx_register_commands,
  64         .init = ep93xx_init,
  65         .quit = ep93xx_quit,
  66 };
  67
  68 static struct bitbang_interface ep93xx_bitbang =
  69 {
  70         .read = ep93xx_read,
  71         .write = ep93xx_write,
  72         .reset = ep93xx_reset,
  73         .blink = 0,
  74 };
  75
  76 static int ep93xx_read(void)
  77 {
  78         return !!(*gpio_data_register & TDO_BIT);
  79 }
  80
  81 static void ep93xx_write(int tck, int tms, int tdi)
  82 {
  83         if (tck)
  84                 output_value |= TCK_BIT;
  85         else
  86                 output_value &= ~TCK_BIT;
  87
  88         if (tms)
  89                 output_value |= TMS_BIT;
  90         else
  91                 output_value &= ~TMS_BIT;
  92
  93         if (tdi)
  94                 output_value |= TDI_BIT;
  95         else
  96                 output_value &= ~TDI_BIT;
  97
  98         *gpio_data_register = output_value;
  99         nanosleep(&ep93xx_zzzz, NULL);
 100 }
 101
 102 /* (1) assert or (0) deassert reset lines */
 103 static void ep93xx_reset(int trst, int srst)
 104 {
 105         if (trst == 0)
 106                 output_value |= TRST_BIT;
 107         else if (trst == 1)
 108                 output_value &= ~TRST_BIT;
 109
 110         if (srst == 0)
 111                 output_value |= SRST_BIT;
 112         else if (srst == 1)
 113                 output_value &= ~SRST_BIT;
 114
 115         *gpio_data_register = output_value;
 116         nanosleep(&ep93xx_zzzz, NULL);
 117 }
 118
 119 static int ep93xx_speed(int speed)
 120 {
 121
 122         return ERROR_OK;
 123 }
 124
 125 static int ep93xx_register_commands(struct command_context *cmd_ctx)
 126 {
 127
 128         return ERROR_OK;
 129 }
 130
 131 static int set_gonk_mode(void)
 132 {
 133         void *syscon;
 134         uint32_t devicecfg;
 135
 136         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 137                         MAP_SHARED, dev_mem_fd, 0x80930000);
 138         if (syscon == MAP_FAILED) {
 139                 perror("mmap");
 140                 return ERROR_JTAG_INIT_FAILED;
 141         }
 142
 143         devicecfg = *((volatile int *)(syscon + 0x80));
 144         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 145         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 146
 147         munmap(syscon, 4096);
 148
 149         return ERROR_OK;
 150 }
 151
 152 static int ep93xx_init(void)
 153 {
 154         int ret;
 155
 156         bitbang_interface = &ep93xx_bitbang;
 157
 158         ep93xx_zzzz.tv_sec = 0;
 159         ep93xx_zzzz.tv_nsec = 10000000;
 160
 161         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 162         if (dev_mem_fd < 0) {
 163                 perror("open");
 164                 return ERROR_JTAG_INIT_FAILED;
 165         }
 166
 167         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 168                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 169         if (gpio_controller == MAP_FAILED) {
 170                 perror("mmap");
 171                 close(dev_mem_fd);
 172                 return ERROR_JTAG_INIT_FAILED;
 173         }
 174
 175         ret = set_gonk_mode();
 176         if (ret != ERROR_OK) {
 177                 munmap(gpio_controller, 4096);
 178                 close(dev_mem_fd);
 179                 return ret;
 180         }
 181
 182 #if 0
 183         /* Use GPIO port A.  */
 184         gpio_data_register = gpio_controller + 0x00;
 185         gpio_data_direction_register = gpio_controller + 0x10;
 186
 187
 188         /* Use GPIO port B.  */
 189         gpio_data_register = gpio_controller + 0x04;
 190         gpio_data_direction_register = gpio_controller + 0x14;
 191
 192         /* Use GPIO port C.  */
 193         gpio_data_register = gpio_controller + 0x08;
 194         gpio_data_direction_register = gpio_controller + 0x18;
 195
 196         /* Use GPIO port D.  */
 197         gpio_data_register = gpio_controller + 0x0c;
 198         gpio_data_direction_register = gpio_controller + 0x1c;
 199 #endif
 200
 201         /* Use GPIO port C.  */
 202         gpio_data_register = gpio_controller + 0x08;
 203         gpio_data_direction_register = gpio_controller + 0x18;
 204
 205         LOG_INFO("gpio_data_register      = %p\n", gpio_data_register);
 206         LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
 207         /*
 208          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 209          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 210          * TMS/TRST/SRST high.
 211          */
 212         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 213         *gpio_data_register = output_value;
 214         nanosleep(&ep93xx_zzzz, NULL);
 215
 216         /*
 217          * Configure the direction register.  1 = output, 0 = input.
 218          */
 219         *gpio_data_direction_register =
 220                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 221
 222         nanosleep(&ep93xx_zzzz, NULL);
 223         return ERROR_OK;
 224 }
 225
 226 static int ep93xx_quit(void)
 227 {
 228
 229         return ERROR_OK;
 230 }