src/flash/nand/mx3.c

   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 /*
  24  * Freescale iMX3* OpenOCD NAND Flash controller support.
  25  *
  26  * Many thanks to Ben Dooks for writing s3c24xx driver.
  27  */
  28
  29 /*
  30 driver tested with STMicro NAND512W3A @imx31
  31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
  32 get_next_halfword_from_sram_buffer() not tested
  33 */
  34 #ifdef HAVE_CONFIG_H
  35 #include "config.h"
  36 #endif
  37
  38 #include "imp.h"
  39 #include "mx3.h"
  40 #include <target/target.h>
  41
  42 static const char target_not_halted_err_msg[] =
  43         "target must be halted to use mx3 NAND flash controller";
  44 static const char data_block_size_err_msg[] =
  45         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  46 static const char sram_buffer_bounds_err_msg[] =
  47         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  48 static const char get_status_register_err_msg[] = "can't get NAND status";
  49 static uint32_t in_sram_address;
  50 static unsigned char sign_of_sequental_byte_read;
  51
  52 static int test_iomux_settings (struct target * target, uint32_t value,
  53                                 uint32_t mask, const char *text);
  54 static int initialize_nf_controller (struct nand_device *nand);
  55 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
  56 static int get_next_halfword_from_sram_buffer (struct target * target,
  57                                                uint16_t * value);
  58 static int poll_for_complete_op (struct target * target, const char *text);
  59 static int validate_target_state (struct nand_device *nand);
  60 static int do_data_output (struct nand_device *nand);
  61
  62 static int imx31_command (struct nand_device *nand, uint8_t command);
  63 static int imx31_address (struct nand_device *nand, uint8_t address);
  64
  65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
  66 {
  67         struct mx3_nf_controller *mx3_nf_info;
  68         mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
  69         if (mx3_nf_info == NULL)
  70         {
  71             LOG_ERROR ("no memory for nand controller");
  72             return ERROR_FAIL;
  73         }
  74
  75         nand->controller_priv = mx3_nf_info;
  76
  77         if (CMD_ARGC < 3)
  78         {
  79             LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
  80             return ERROR_FAIL;
  81         }
  82         /*
  83         * check hwecc requirements
  84         */
  85         {
  86         int hwecc_needed;
  87         hwecc_needed = strcmp (CMD_ARGV[2], "hwecc");
  88         if (hwecc_needed == 0)
  89             {
  90                 mx3_nf_info->flags.hw_ecc_enabled = 1;
  91             }
  92         else
  93             {
  94                 mx3_nf_info->flags.hw_ecc_enabled = 0;
  95             }
  96         }
  97
  98         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
  99         mx3_nf_info->fin = MX3_NF_FIN_NONE;
 100         mx3_nf_info->flags.target_little_endian =
 101         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 102         /*
 103         * testing host endianness
 104         */
 105         {
 106         int x = 1;
 107         if (*(char *) &x == 1)
 108             {
 109                 mx3_nf_info->flags.host_little_endian = 1;
 110             }
 111         else
 112             {
 113                 mx3_nf_info->flags.host_little_endian = 0;
 114             }
 115         }
 116         return ERROR_OK;
 117 }
 118
 119 static int imx31_init (struct nand_device *nand)
 120 {
 121         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 122         struct target *target = nand->target;
 123
 124         {
 125         /*
 126          * validate target state
 127          */
 128         int validate_target_result;
 129         validate_target_result = validate_target_state(nand);
 130         if (validate_target_result != ERROR_OK)
 131             {
 132                 return validate_target_result;
 133             }
 134         }
 135
 136         {
 137         uint16_t buffsize_register_content;
 138         target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
 139         mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 140         }
 141
 142         {
 143         uint32_t pcsr_register_content;
 144         target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
 145         if (!nand->bus_width)
 146             {
 147                 nand->bus_width =
 148                     (pcsr_register_content & 0x80000000) ? 16 : 8;
 149             }
 150         else
 151             {
 152                 pcsr_register_content |=
 153                     ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
 154                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 155             }
 156
 157         if (!nand->page_size)
 158             {
 159                 nand->page_size =
 160                     (pcsr_register_content & 0x40000000) ? 2048 : 512;
 161             }
 162         else
 163             {
 164                 pcsr_register_content |=
 165                     ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
 166                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 167             }
 168         if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
 169             {
 170                 LOG_ERROR
 171                     ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
 172             }
 173         }
 174
 175         {
 176         uint32_t cgr_register_content;
 177         target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
 178         if (!(cgr_register_content & 0x00000300))
 179             {
 180                 LOG_ERROR ("clock gating to EMI disabled");
 181                 return ERROR_FAIL;
 182             }
 183         }
 184
 185         {
 186         uint32_t gpr_register_content;
 187         target_read_u32 (target, MX3_GPR, &gpr_register_content);
 188         if (gpr_register_content & 0x00000060)
 189             {
 190                 LOG_ERROR ("pins mode overrided by GPR");
 191                 return ERROR_FAIL;
 192             }
 193         }
 194
 195         {
 196         /*
 197          * testing IOMUX settings; must be in "functional-mode output and
 198          * functional-mode input" mode
 199          */
 200         int test_iomux;
 201         test_iomux = ERROR_OK;
 202         test_iomux |=
 203             test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
 204         test_iomux |=
 205             test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
 206         test_iomux |=
 207             test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
 208         if (nand->bus_width == 16)
 209             {
 210                 test_iomux |=
 211                     test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
 212                                          "d8,d9,d10");
 213                 test_iomux |=
 214                     test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
 215                                          "d11,d12,d13,d14");
 216                 test_iomux |=
 217                     test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
 218             }
 219         test_iomux |=
 220             test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
 221                                  "nfwp,nfce,nfrb");
 222         test_iomux |=
 223             test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
 224                                  "nfwe,nfre,nfale,nfcle");
 225         if (test_iomux != ERROR_OK)
 226             {
 227                 return ERROR_FAIL;
 228             }
 229         }
 230
 231         initialize_nf_controller (nand);
 232
 233         {
 234         int retval;
 235         uint16_t nand_status_content;
 236         retval = ERROR_OK;
 237         retval |= imx31_command (nand, NAND_CMD_STATUS);
 238         retval |= imx31_address (nand, 0x00);
 239         retval |= do_data_output (nand);
 240         if (retval != ERROR_OK)
 241             {
 242                 LOG_ERROR (get_status_register_err_msg);
 243                 return ERROR_FAIL;
 244             }
 245         target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 246         if (!(nand_status_content & 0x0080))
 247             {
 248                 /*
 249                  * is host-big-endian correctly ??
 250                  */
 251                 LOG_INFO ("NAND read-only");
 252                 mx3_nf_info->flags.nand_readonly = 1;
 253             }
 254         else
 255             {
 256                 mx3_nf_info->flags.nand_readonly = 0;
 257             }
 258         }
 259         return ERROR_OK;
 260 }
 261
 262 static int imx31_read_data (struct nand_device *nand, void *data)
 263 {
 264         struct target *target = nand->target;
 265         {
 266         /*
 267          * validate target state
 268          */
 269         int validate_target_result;
 270         validate_target_result = validate_target_state (nand);
 271         if (validate_target_result != ERROR_OK)
 272             {
 273                 return validate_target_result;
 274             }
 275         }
 276
 277         {
 278         /*
 279          * get data from nand chip
 280          */
 281         int try_data_output_from_nand_chip;
 282         try_data_output_from_nand_chip = do_data_output (nand);
 283         if (try_data_output_from_nand_chip != ERROR_OK)
 284             {
 285                 return try_data_output_from_nand_chip;
 286             }
 287         }
 288
 289         if (nand->bus_width == 16)
 290         {
 291             get_next_halfword_from_sram_buffer (target, data);
 292         }
 293         else
 294         {
 295             get_next_byte_from_sram_buffer (target, data);
 296         }
 297
 298         return ERROR_OK;
 299 }
 300
 301 static int imx31_write_data (struct nand_device *nand, uint16_t data)
 302 {
 303         LOG_ERROR ("write_data() not implemented");
 304         return ERROR_NAND_OPERATION_FAILED;
 305 }
 306
 307 static int imx31_reset (struct nand_device *nand)
 308 {
 309         /*
 310         * validate target state
 311         */
 312         int validate_target_result;
 313         validate_target_result = validate_target_state (nand);
 314         if (validate_target_result != ERROR_OK)
 315         {
 316             return validate_target_result;
 317         }
 318         initialize_nf_controller (nand);
 319         return ERROR_OK;
 320 }
 321
 322 static int imx31_command (struct nand_device *nand, uint8_t command)
 323 {
 324         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 325         struct target *target = nand->target;
 326         {
 327         /*
 328          * validate target state
 329          */
 330         int validate_target_result;
 331         validate_target_result = validate_target_state (nand);
 332         if (validate_target_result != ERROR_OK)
 333             {
 334                 return validate_target_result;
 335             }
 336         }
 337
 338         switch (command)
 339         {
 340             case NAND_CMD_READOOB:
 341                 command = NAND_CMD_READ0;
 342                 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
 343                                                          * data_read() and
 344                                                          * read_block_data() to
 345                                                          * spare area in SRAM
 346                                                          * buffer */
 347                 break;
 348             case NAND_CMD_READ1:
 349                 command = NAND_CMD_READ0;
 350                 /*
 351                  * offset == one half of page size
 352                  */
 353                 in_sram_address =
 354                     MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 355             default:
 356                 in_sram_address = MX3_NF_MAIN_BUFFER0;
 357         }
 358
 359         target_write_u16 (target, MX3_NF_FCMD, command);
 360         /*
 361         * start command input operation (set MX3_NF_BIT_OP_DONE==0)
 362         */
 363         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
 364         {
 365         int poll_result;
 366         poll_result = poll_for_complete_op (target, "command");
 367         if (poll_result != ERROR_OK)
 368             {
 369                 return poll_result;
 370             }
 371         }
 372         /*
 373         * reset cursor to begin of the buffer
 374         */
 375         sign_of_sequental_byte_read = 0;
 376         switch (command)
 377         {
 378             case NAND_CMD_READID:
 379                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
 380                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 381                 break;
 382             case NAND_CMD_STATUS:
 383                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
 384                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 385                 break;
 386             case NAND_CMD_READ0:
 387                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 388                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 389                 break;
 390             default:
 391                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 392         }
 393         return ERROR_OK;
 394 }
 395
 396 static int imx31_address (struct nand_device *nand, uint8_t address)
 397 {
 398         struct target *target = nand->target;
 399         {
 400         /*
 401          * validate target state
 402          */
 403         int validate_target_result;
 404         validate_target_result = validate_target_state (nand);
 405         if (validate_target_result != ERROR_OK)
 406             {
 407                 return validate_target_result;
 408             }
 409         }
 410
 411         target_write_u16 (target, MX3_NF_FADDR, address);
 412         /*
 413         * start address input operation (set MX3_NF_BIT_OP_DONE==0)
 414         */
 415         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
 416         {
 417         int poll_result;
 418         poll_result = poll_for_complete_op (target, "address");
 419         if (poll_result != ERROR_OK)
 420             {
 421                 return poll_result;
 422             }
 423         }
 424         return ERROR_OK;
 425 }
 426
 427 static int imx31_nand_ready (struct nand_device *nand, int tout)
 428 {
 429         uint16_t poll_complete_status;
 430         struct target *target = nand->target;
 431
 432         {
 433         /*
 434          * validate target state
 435          */
 436         int validate_target_result;
 437         validate_target_result = validate_target_state (nand);
 438         if (validate_target_result != ERROR_OK)
 439             {
 440                 return validate_target_result;
 441             }
 442         }
 443
 444         do
 445         {
 446             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 447             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 448                 {
 449                     return tout;
 450                 }
 451             alive_sleep (1);
 452         }
 453         while (tout-- > 0);
 454         return tout;
 455 }
 456
 457 static int imx31_write_page (struct nand_device *nand, uint32_t page,
 458                              uint8_t * data, uint32_t data_size, uint8_t * oob,
 459                              uint32_t oob_size)
 460 {
 461         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 462         struct target *target = nand->target;
 463
 464         if (data_size % 2)
 465         {
 466             LOG_ERROR (data_block_size_err_msg, data_size);
 467             return ERROR_NAND_OPERATION_FAILED;
 468         }
 469         if (oob_size % 2)
 470         {
 471             LOG_ERROR (data_block_size_err_msg, oob_size);
 472             return ERROR_NAND_OPERATION_FAILED;
 473         }
 474         if (!data)
 475         {
 476             LOG_ERROR ("nothing to program");
 477             return ERROR_NAND_OPERATION_FAILED;
 478         }
 479         {
 480         /*
 481          * validate target state
 482          */
 483         int retval;
 484         retval = validate_target_state (nand);
 485         if (retval != ERROR_OK)
 486             {
 487                 return retval;
 488             }
 489         }
 490         {
 491         int retval = ERROR_OK;
 492         retval |= imx31_command(nand, NAND_CMD_SEQIN);
 493         retval |= imx31_address(nand, 0x00);
 494         retval |= imx31_address(nand, page & 0xff);
 495         retval |= imx31_address(nand, (page >> 8) & 0xff);
 496         if (nand->address_cycles >= 4)
 497             {
 498                 retval |= imx31_address (nand, (page >> 16) & 0xff);
 499                 if (nand->address_cycles >= 5)
 500                     {
 501                         retval |= imx31_address (nand, (page >> 24) & 0xff);
 502                     }
 503             }
 504         target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
 505         if (oob)
 506             {
 507                 if (mx3_nf_info->flags.hw_ecc_enabled)
 508                     {
 509                         /*
 510                          * part of spare block will be overrided by hardware
 511                          * ECC generator
 512                          */
 513                         LOG_DEBUG
 514                             ("part of spare block will be overrided by hardware ECC generator");
 515                     }
 516                 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 517                                      oob);
 518             }
 519         /*
 520          * start data input operation (set MX3_NF_BIT_OP_DONE==0)
 521          */
 522         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
 523         {
 524             int poll_result;
 525             poll_result = poll_for_complete_op (target, "data input");
 526             if (poll_result != ERROR_OK)
 527                 {
 528                     return poll_result;
 529                 }
 530         }
 531         retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
 532         if (retval != ERROR_OK)
 533             {
 534                 return retval;
 535             }
 536
 537         /*
 538          * check status register
 539          */
 540         {
 541             uint16_t nand_status_content;
 542             retval = ERROR_OK;
 543             retval |= imx31_command(nand, NAND_CMD_STATUS);
 544             retval |= imx31_address(nand, 0x00);
 545             retval |= do_data_output(nand);
 546             if (retval != ERROR_OK)
 547                 {
 548                     LOG_ERROR (get_status_register_err_msg);
 549                     return retval;
 550                 }
 551             target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 552             if (nand_status_content & 0x0001)
 553                 {
 554                     /*
 555                      * is host-big-endian correctly ??
 556                      */
 557                     return ERROR_NAND_OPERATION_FAILED;
 558                 }
 559         }
 560         }
 561         return ERROR_OK;
 562 }
 563
 564 static int imx31_read_page (struct nand_device *nand, uint32_t page,
 565                             uint8_t * data, uint32_t data_size, uint8_t * oob,
 566                             uint32_t oob_size)
 567 {
 568         struct target *target = nand->target;
 569
 570         if (data_size % 2)
 571         {
 572             LOG_ERROR (data_block_size_err_msg, data_size);
 573             return ERROR_NAND_OPERATION_FAILED;
 574         }
 575         if (oob_size % 2)
 576         {
 577             LOG_ERROR (data_block_size_err_msg, oob_size);
 578             return ERROR_NAND_OPERATION_FAILED;
 579         }
 580
 581         {
 582         /*
 583          * validate target state
 584          */
 585         int retval;
 586         retval = validate_target_state(nand);
 587         if (retval != ERROR_OK)
 588             {
 589                 return retval;
 590             }
 591         }
 592         {
 593         int retval = ERROR_OK;
 594         retval |= imx31_command(nand, NAND_CMD_READ0);
 595         retval |= imx31_address(nand, 0x00);
 596         retval |= imx31_address(nand, page & 0xff);
 597         retval |= imx31_address(nand, (page >> 8) & 0xff);
 598         if (nand->address_cycles >= 4)
 599             {
 600                 retval |= imx31_address(nand, (page >> 16) & 0xff);
 601                 if (nand->address_cycles >= 5)
 602                     {
 603                         retval |= imx31_address(nand, (page >> 24) & 0xff);
 604                         retval |= imx31_command(nand, NAND_CMD_READSTART);
 605                     }
 606             }
 607         retval |= do_data_output (nand);
 608         if (retval != ERROR_OK)
 609             {
 610                 return retval;
 611             }
 612
 613         if (data)
 614             {
 615                 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
 616                                     data);
 617             }
 618         if (oob)
 619             {
 620                 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 621                                     oob);
 622             }
 623         }
 624         return ERROR_OK;
 625 }
 626
 627 static int test_iomux_settings (struct target * target, uint32_t address,
 628                                 uint32_t mask, const char *text)
 629 {
 630         uint32_t register_content;
 631         target_read_u32 (target, address, &register_content);
 632         if ((register_content & mask) != (0x12121212 & mask))
 633         {
 634             LOG_ERROR ("IOMUX for {%s} is bad", text);
 635             return ERROR_FAIL;
 636         }
 637         return ERROR_OK;
 638 }
 639
 640 static int initialize_nf_controller (struct nand_device *nand)
 641 {
 642         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 643         struct target *target = nand->target;
 644         /*
 645         * resets NAND flash controller in zero time ? I dont know.
 646         */
 647         target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 648         {
 649         uint16_t work_mode;
 650         work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
 651         if (target->endianness == TARGET_BIG_ENDIAN)
 652             {
 653                 work_mode |= MX3_NF_BIT_BE_EN;
 654             }
 655         if (mx3_nf_info->flags.hw_ecc_enabled)
 656             {
 657                 work_mode |= MX3_NF_BIT_ECC_EN;
 658             }
 659         target_write_u16 (target, MX3_NF_CFG1, work_mode);
 660         }
 661         /*
 662         * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 663         */
 664         target_write_u16 (target, MX3_NF_BUFCFG, 2);
 665         {
 666         uint16_t temp;
 667         target_read_u16 (target, MX3_NF_FWP, &temp);
 668         if ((temp & 0x0007) == 1)
 669             {
 670                 LOG_ERROR ("NAND flash is tight-locked, reset needed");
 671                 return ERROR_FAIL;
 672             }
 673
 674         }
 675         /*
 676         * unlock NAND flash for write
 677         */
 678         target_write_u16 (target, MX3_NF_FWP, 4);
 679         target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
 680         target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
 681         /*
 682         * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
 683         */
 684         target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
 685         /*
 686         * address of SRAM buffer
 687         */
 688         in_sram_address = MX3_NF_MAIN_BUFFER0;
 689         sign_of_sequental_byte_read = 0;
 690         return ERROR_OK;
 691 }
 692
 693 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
 694 {
 695         static uint8_t even_byte = 0;
 696         /*
 697         * host-big_endian ??
 698         */
 699         if (sign_of_sequental_byte_read == 0)
 700         {
 701             even_byte = 0;
 702         }
 703         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 704         {
 705             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 706             *value = 0;
 707             sign_of_sequental_byte_read = 0;
 708             even_byte = 0;
 709             return ERROR_NAND_OPERATION_FAILED;
 710         }
 711         else
 712         {
 713             uint16_t temp;
 714             target_read_u16 (target, in_sram_address, &temp);
 715             if (even_byte)
 716                 {
 717                     *value = temp >> 8;
 718                     even_byte = 0;
 719                     in_sram_address += 2;
 720                 }
 721             else
 722                 {
 723                     *value = temp & 0xff;
 724                     even_byte = 1;
 725                 }
 726         }
 727         sign_of_sequental_byte_read = 1;
 728         return ERROR_OK;
 729 }
 730
 731 static int get_next_halfword_from_sram_buffer (struct target * target,
 732                                                uint16_t * value)
 733 {
 734         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 735         {
 736             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 737             *value = 0;
 738             return ERROR_NAND_OPERATION_FAILED;
 739         }
 740         else
 741         {
 742             target_read_u16 (target, in_sram_address, value);
 743             in_sram_address += 2;
 744         }
 745         return ERROR_OK;
 746 }
 747
 748 static int poll_for_complete_op (struct target * target, const char *text)
 749 {
 750         uint16_t poll_complete_status;
 751         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
 752         {
 753             usleep (25);
 754             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 755             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 756                 {
 757                     break;
 758                 }
 759         }
 760         if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
 761         {
 762             LOG_ERROR ("%s sending timeout", text);
 763             return ERROR_NAND_OPERATION_FAILED;
 764         }
 765         return ERROR_OK;
 766 }
 767
 768 static int validate_target_state (struct nand_device *nand)
 769 {
 770         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 771         struct target *target = nand->target;
 772
 773         if (target->state != TARGET_HALTED)
 774         {
 775             LOG_ERROR (target_not_halted_err_msg);
 776             return ERROR_NAND_OPERATION_FAILED;
 777         }
 778
 779         if (mx3_nf_info->flags.target_little_endian !=
 780         (target->endianness == TARGET_LITTLE_ENDIAN))
 781         {
 782             /*
 783              * endianness changed after NAND controller probed
 784              */
 785             return ERROR_NAND_OPERATION_FAILED;
 786         }
 787         return ERROR_OK;
 788 }
 789
 790 static int do_data_output (struct nand_device *nand)
 791 {
 792         struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 793         struct target *target = nand->target;
 794         switch (mx3_nf_info->fin)
 795         {
 796             case MX3_NF_FIN_DATAOUT:
 797                 /*
 798                  * start data output operation (set MX3_NF_BIT_OP_DONE==0)
 799                  */
 800                 target_write_u16 (target, MX3_NF_CFG2,
 801                                   MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
 802                                                            optype));
 803                 {
 804                     int poll_result;
 805                     poll_result = poll_for_complete_op (target, "data output");
 806                     if (poll_result != ERROR_OK)
 807                         {
 808                             return poll_result;
 809                         }
 810                 }
 811                 mx3_nf_info->fin = MX3_NF_FIN_NONE;
 812                 /*
 813                  * ECC stuff
 814                  */
 815                 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
 816                     && mx3_nf_info->flags.hw_ecc_enabled)
 817                     {
 818                         uint16_t ecc_status;
 819                         target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 820                         switch (ecc_status & 0x000c)
 821                             {
 822                                 case 1 << 2:
 823                                     LOG_DEBUG
 824                                         ("main area readed with 1 (correctable) error");
 825                                     break;
 826                                 case 2 << 2:
 827                                     LOG_DEBUG
 828                                         ("main area readed with more than 1 (incorrectable) error");
 829                                     return ERROR_NAND_OPERATION_FAILED;
 830                                     break;
 831                             }
 832                         switch (ecc_status & 0x0003)
 833                             {
 834                                 case 1:
 835                                     LOG_DEBUG
 836                                         ("spare area readed with 1 (correctable) error");
 837                                     break;
 838                                 case 2:
 839                                     LOG_DEBUG
 840                                         ("main area readed with more than 1 (incorrectable) error");
 841                                     return ERROR_NAND_OPERATION_FAILED;
 842                                     break;
 843                             }
 844                     }
 845                 break;
 846             case MX3_NF_FIN_NONE:
 847                 break;
 848         }
 849         return ERROR_OK;
 850 }
 851
 852 struct nand_flash_controller imx31_nand_flash_controller = {
 853                 .name = "imx31",
 854                 .nand_device_command = &imx31_nand_device_command,
 855                 .init = &imx31_init,
 856                 .reset = &imx31_reset,
 857                 .command = &imx31_command,
 858                 .address = &imx31_address,
 859                 .write_data = &imx31_write_data,
 860                 .read_data = &imx31_read_data,
 861                 .write_page = &imx31_write_page,
 862                 .read_page = &imx31_read_page,
 863                 .nand_ready = &imx31_nand_ready,
 864         };