src/target/arm11.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   Copyright (C) 2009 David Brownell                                     *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "etm.h"
  32 #include "breakpoints.h"
  33 #include "arm11_dbgtap.h"
  34 #include "arm_simulator.h"
  35 #include <helper/time_support.h>
  36 #include "target_type.h"
  37 #include "algorithm.h"
  38 #include "register.h"
  39 #include "arm_opcodes.h"
  40
  41
  42 #if 0
  43 #define _DEBUG_INSTRUCTION_EXECUTION_
  44 #endif
  45
  46
  47 /* FIXME none of these flags should be global to all ARM11 cores!
  48  * Most of them shouldn't exist at all, once the code works...
  49  */
  50 static bool arm11_config_memwrite_burst = true;
  51 static bool arm11_config_memwrite_error_fatal = true;
  52 static uint32_t arm11_vcr = 0;
  53 static bool arm11_config_step_irq_enable = false;
  54 static bool arm11_config_hardware_step = false;
  55
  56 static int arm11_step(struct target *target, int current,
  57                 uint32_t address, int handle_breakpoints);
  58
  59
  60 /** Check and if necessary take control of the system
  61  *
  62  * \param arm11         Target state variable.
  63  */
  64 static int arm11_check_init(struct arm11_common *arm11)
  65 {
  66         CHECK_RETVAL(arm11_read_DSCR(arm11));
  67
  68         if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
  69         {
  70                 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
  71                 LOG_DEBUG("Bringing target into debug mode");
  72
  73                 arm11->dscr |= DSCR_HALT_DBG_MODE;
  74                 arm11_write_DSCR(arm11, arm11->dscr);
  75
  76                 /* add further reset initialization here */
  77
  78                 arm11->simulate_reset_on_next_halt = true;
  79
  80                 if (arm11->dscr & DSCR_CORE_HALTED)
  81                 {
  82                         /** \todo TODO: this needs further scrutiny because
  83                           * arm11_debug_entry() never gets called.  (WHY NOT?)
  84                           * As a result we don't read the actual register states from
  85                           * the target.
  86                           */
  87
  88                         arm11->arm.target->state = TARGET_HALTED;
  89                         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
  90                 }
  91                 else
  92                 {
  93                         arm11->arm.target->state = TARGET_RUNNING;
  94                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
  95                 }
  96
  97                 arm11_sc7_clear_vbw(arm11);
  98         }
  99
 100         return ERROR_OK;
 101 }
 102
 103 /**
 104  * Save processor state.  This is called after a HALT instruction
 105  * succeeds, and on other occasions the processor enters debug mode
 106  * (breakpoint, watchpoint, etc).  Caller has updated arm11->dscr.
 107  */
 108 static int arm11_debug_entry(struct arm11_common *arm11)
 109 {
 110         int retval;
 111
 112         arm11->arm.target->state = TARGET_HALTED;
 113         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
 114
 115         /* REVISIT entire cache should already be invalid !!! */
 116         register_cache_invalidate(arm11->arm.core_cache);
 117
 118         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 119
 120         /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
 121         arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
 122         if (arm11->is_wdtr_saved)
 123         {
 124                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 125
 126                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 127
 128                 struct scan_field       chain5_fields[3];
 129
 130                 arm11_setup_field(arm11, 32, NULL,
 131                                 &arm11->saved_wdtr, chain5_fields + 0);
 132                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 133                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 134
 135                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 136
 137         }
 138
 139         /* DSCR: set the Execute ARM instruction enable bit.
 140          *
 141          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 142          * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
 143          * for executing instructions via ITR.
 144          */
 145         arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
 146
 147
 148         /* From the spec:
 149            Before executing any instruction in debug state you have to drain the write buffer.
 150            This ensures that no imprecise Data Aborts can return at a later point:*/
 151
 152         /** \todo TODO: Test drain write buffer. */
 153
 154 #if 0
 155         while (1)
 156         {
 157                 /* MRC p14,0,R0,c5,c10,0 */
 158                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 159
 160                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 161                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 162
 163                 uint32_t dscr = arm11_read_DSCR(arm11);
 164
 165                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 166
 167                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 168                 {
 169                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 170
 171                         dscr = arm11_read_DSCR(arm11);
 172
 173                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 174
 175                         break;
 176                 }
 177         }
 178 #endif
 179
 180         /* Save registers.
 181          *
 182          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 183          * CPSR and PC after the rDTR stuff.  We do it all at once.
 184          */
 185         retval = arm_dpm_read_current_registers(&arm11->dpm);
 186         if (retval != ERROR_OK)
 187                 LOG_ERROR("DPM REG READ -- fail %d", retval);
 188
 189         retval = arm11_run_instr_data_prepare(arm11);
 190         if (retval != ERROR_OK)
 191                 return retval;
 192
 193         /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
 194         arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
 195         if (arm11->is_rdtr_saved)
 196         {
 197                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 198                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 199                                 0xEE100E15, &arm11->saved_rdtr);
 200                 if (retval != ERROR_OK)
 201                         return retval;
 202         }
 203
 204         /* REVISIT Now that we've saved core state, there's may also
 205          * be MMU and cache state to care about ...
 206          */
 207
 208         if (arm11->simulate_reset_on_next_halt)
 209         {
 210                 arm11->simulate_reset_on_next_halt = false;
 211
 212                 LOG_DEBUG("Reset c1 Control Register");
 213
 214                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 215
 216                 /* MCR p15,0,R0,c1,c0,0 */
 217                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 218                 if (retval != ERROR_OK)
 219                         return retval;
 220
 221         }
 222
 223         if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
 224                 uint32_t wfar;
 225
 226                 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
 227                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 228                                 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
 229                                 &wfar);
 230                 if (retval != ERROR_OK)
 231                         return retval;
 232                 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
 233         }
 234
 235
 236         retval = arm11_run_instr_data_finish(arm11);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return ERROR_OK;
 241 }
 242
 243 /**
 244  * Restore processor state.  This is called in preparation for
 245  * the RESTART function.
 246  */
 247 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 248 {
 249         int retval;
 250
 251         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 252
 253         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 254          * except R0/PC/CPSR right now.  Instead, we do them all
 255          * at once, just a bit later on.
 256          */
 257
 258         /* REVISIT once we start caring about MMU and cache state,
 259          * address it here ...
 260          */
 261
 262         /* spec says clear wDTR and rDTR; we assume they are clear as
 263            otherwise our programming would be sloppy */
 264         {
 265                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 266
 267                 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
 268                 {
 269                         /*
 270                         The wDTR/rDTR two registers that are used to send/receive data to/from
 271                         the core in tandem with corresponding instruction codes that are
 272                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 273                         registers hold data that was written by one side (CPU or JTAG) and not
 274                         read out by the other side.
 275                         */
 276                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
 277                                         (unsigned) arm11->dscr);
 278                         return ERROR_FAIL;
 279                 }
 280         }
 281
 282         /* maybe restore original wDTR */
 283         if (arm11->is_wdtr_saved)
 284         {
 285                 retval = arm11_run_instr_data_prepare(arm11);
 286                 if (retval != ERROR_OK)
 287                         return retval;
 288
 289                 /* MCR p14,0,R0,c0,c5,0 */
 290                 retval = arm11_run_instr_data_to_core_via_r0(arm11,
 291                                 0xee000e15, arm11->saved_wdtr);
 292                 if (retval != ERROR_OK)
 293                         return retval;
 294
 295                 retval = arm11_run_instr_data_finish(arm11);
 296                 if (retval != ERROR_OK)
 297                         return retval;
 298         }
 299
 300         /* restore CPSR, PC, and R0 ... after flushing any modified
 301          * registers.
 302          */
 303         retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 304
 305         retval = arm11_bpwp_flush(arm11);
 306
 307         register_cache_invalidate(arm11->arm.core_cache);
 308
 309         /* restore DSCR */
 310         arm11_write_DSCR(arm11, arm11->dscr);
 311
 312         /* maybe restore rDTR */
 313         if (arm11->is_rdtr_saved)
 314         {
 315                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 316
 317                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 318
 319                 struct scan_field       chain5_fields[3];
 320
 321                 uint8_t                 Ready           = 0;    /* ignored */
 322                 uint8_t                 Valid           = 0;    /* ignored */
 323
 324                 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
 325                                 NULL, chain5_fields + 0);
 326                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 327                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 328
 329                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 330         }
 331
 332         /* now processor is ready to RESTART */
 333
 334         return ERROR_OK;
 335 }
 336
 337 /* poll current target status */
 338 static int arm11_poll(struct target *target)
 339 {
 340         int retval;
 341         struct arm11_common *arm11 = target_to_arm11(target);
 342
 343         CHECK_RETVAL(arm11_check_init(arm11));
 344
 345         if (arm11->dscr & DSCR_CORE_HALTED)
 346         {
 347                 if (target->state != TARGET_HALTED)
 348                 {
 349                         enum target_state old_state = target->state;
 350
 351                         LOG_DEBUG("enter TARGET_HALTED");
 352                         retval = arm11_debug_entry(arm11);
 353                         if (retval != ERROR_OK)
 354                                 return retval;
 355
 356                         target_call_event_callbacks(target,
 357                                 (old_state == TARGET_DEBUG_RUNNING)
 358                                         ? TARGET_EVENT_DEBUG_HALTED
 359                                         : TARGET_EVENT_HALTED);
 360                 }
 361         }
 362         else
 363         {
 364                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 365                 {
 366                         LOG_DEBUG("enter TARGET_RUNNING");
 367                         target->state                   = TARGET_RUNNING;
 368                         target->debug_reason    = DBG_REASON_NOTHALTED;
 369                 }
 370         }
 371
 372         return ERROR_OK;
 373 }
 374 /* architecture specific status reply */
 375 static int arm11_arch_state(struct target *target)
 376 {
 377         struct arm11_common *arm11 = target_to_arm11(target);
 378         int retval;
 379
 380         retval = arm_arch_state(target);
 381
 382         /* REVISIT also display ARM11-specific MMU and cache status ... */
 383
 384         if (target->debug_reason == DBG_REASON_WATCHPOINT)
 385                 LOG_USER("Watchpoint triggered at PC %#08x",
 386                                 (unsigned) arm11->dpm.wp_pc);
 387
 388         return retval;
 389 }
 390
 391 /* target request support */
 392 static int arm11_target_request_data(struct target *target,
 393                 uint32_t size, uint8_t *buffer)
 394 {
 395         LOG_WARNING("Not implemented: %s", __func__);
 396
 397         return ERROR_FAIL;
 398 }
 399
 400 /* target execution control */
 401 static int arm11_halt(struct target *target)
 402 {
 403         struct arm11_common *arm11 = target_to_arm11(target);
 404
 405         LOG_DEBUG("target->state: %s",
 406                 target_state_name(target));
 407
 408         if (target->state == TARGET_UNKNOWN)
 409         {
 410                 arm11->simulate_reset_on_next_halt = true;
 411         }
 412
 413         if (target->state == TARGET_HALTED)
 414         {
 415                 LOG_DEBUG("target was already halted");
 416                 return ERROR_OK;
 417         }
 418
 419         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 420
 421         CHECK_RETVAL(jtag_execute_queue());
 422
 423         int i = 0;
 424
 425         while (1)
 426         {
 427                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 428
 429                 if (arm11->dscr & DSCR_CORE_HALTED)
 430                         break;
 431
 432
 433                 long long then = 0;
 434                 if (i == 1000)
 435                 {
 436                         then = timeval_ms();
 437                 }
 438                 if (i >= 1000)
 439                 {
 440                         if ((timeval_ms()-then) > 1000)
 441                         {
 442                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 443                                 return ERROR_FAIL;
 444                         }
 445                 }
 446                 i++;
 447         }
 448
 449         enum target_state old_state     = target->state;
 450
 451         arm11_debug_entry(arm11);
 452
 453         CHECK_RETVAL(
 454                 target_call_event_callbacks(target,
 455                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 456
 457         return ERROR_OK;
 458 }
 459
 460 static uint32_t
 461 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 462 {
 463         void *value = arm11->arm.core_cache->reg_list[15].value;
 464
 465         if (!current)
 466                 buf_set_u32(value, 0, 32, address);
 467         else
 468                 address = buf_get_u32(value, 0, 32);
 469
 470         return address;
 471 }
 472
 473 static int arm11_resume(struct target *target, int current,
 474                 uint32_t address, int handle_breakpoints, int debug_execution)
 475 {
 476         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 477         //      current, address, handle_breakpoints, debug_execution);
 478
 479         struct arm11_common *arm11 = target_to_arm11(target);
 480
 481         LOG_DEBUG("target->state: %s",
 482                 target_state_name(target));
 483
 484
 485         if (target->state != TARGET_HALTED)
 486         {
 487                 LOG_ERROR("Target not halted");
 488                 return ERROR_TARGET_NOT_HALTED;
 489         }
 490
 491         address = arm11_nextpc(arm11, current, address);
 492
 493         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 494
 495         /* clear breakpoints/watchpoints and VCR*/
 496         arm11_sc7_clear_vbw(arm11);
 497
 498         if (!debug_execution)
 499                 target_free_all_working_areas(target);
 500
 501         /* Should we skip over breakpoints matching the PC? */
 502         if (handle_breakpoints) {
 503                 struct breakpoint *bp;
 504
 505                 for (bp = target->breakpoints; bp; bp = bp->next)
 506                 {
 507                         if (bp->address == address)
 508                         {
 509                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 510                                 arm11_step(target, 1, 0, 0);
 511                                 break;
 512                         }
 513                 }
 514         }
 515
 516         /* activate all breakpoints */
 517         if (true) {
 518                 struct breakpoint *bp;
 519                 unsigned brp_num = 0;
 520
 521                 for (bp = target->breakpoints; bp; bp = bp->next)
 522                 {
 523                         struct arm11_sc7_action brp[2];
 524
 525                         brp[0].write    = 1;
 526                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 527                         brp[0].value    = bp->address;
 528                         brp[1].write    = 1;
 529                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 530                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 531
 532                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 533
 534                         LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 535                                         bp->address);
 536
 537                         brp_num++;
 538                 }
 539
 540                 if (arm11_vcr)
 541                         arm11_sc7_set_vcr(arm11, arm11_vcr);
 542         }
 543
 544         /* activate all watchpoints and breakpoints */
 545         arm11_leave_debug_state(arm11, true);
 546
 547         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 548
 549         CHECK_RETVAL(jtag_execute_queue());
 550
 551         int i = 0;
 552         while (1)
 553         {
 554                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 555
 556                 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 557
 558                 if (arm11->dscr & DSCR_CORE_RESTARTED)
 559                         break;
 560
 561
 562                 long long then = 0;
 563                 if (i == 1000)
 564                 {
 565                         then = timeval_ms();
 566                 }
 567                 if (i >= 1000)
 568                 {
 569                         if ((timeval_ms()-then) > 1000)
 570                         {
 571                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 572                                 return ERROR_FAIL;
 573                         }
 574                 }
 575                 i++;
 576         }
 577
 578         target->debug_reason = DBG_REASON_NOTHALTED;
 579         if (!debug_execution)
 580                 target->state = TARGET_RUNNING;
 581         else
 582                 target->state = TARGET_DEBUG_RUNNING;
 583         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 584
 585         return ERROR_OK;
 586 }
 587
 588 static int arm11_step(struct target *target, int current,
 589                 uint32_t address, int handle_breakpoints)
 590 {
 591         LOG_DEBUG("target->state: %s",
 592                 target_state_name(target));
 593
 594         if (target->state != TARGET_HALTED)
 595         {
 596                 LOG_WARNING("target was not halted");
 597                 return ERROR_TARGET_NOT_HALTED;
 598         }
 599
 600         struct arm11_common *arm11 = target_to_arm11(target);
 601
 602         address = arm11_nextpc(arm11, current, address);
 603
 604         LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
 605
 606
 607         /** \todo TODO: Thumb not supported here */
 608
 609         uint32_t        next_instruction;
 610
 611         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 612
 613         /* skip over BKPT */
 614         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 615         {
 616                 address = arm11_nextpc(arm11, 0, address + 4);
 617                 LOG_DEBUG("Skipping BKPT");
 618         }
 619         /* skip over Wait for interrupt / Standby */
 620         /* mcr  15, 0, r?, cr7, cr0, {4} */
 621         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 622         {
 623                 address = arm11_nextpc(arm11, 0, address + 4);
 624                 LOG_DEBUG("Skipping WFI");
 625         }
 626         /* ignore B to self */
 627         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 628         {
 629                 LOG_DEBUG("Not stepping jump to self");
 630         }
 631         else
 632         {
 633                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 634                 * with this. */
 635
 636                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 637                 * the VCR might be something worth looking into. */
 638
 639
 640                 /* Set up breakpoint for stepping */
 641
 642                 struct arm11_sc7_action brp[2];
 643
 644                 brp[0].write    = 1;
 645                 brp[0].address  = ARM11_SC7_BVR0;
 646                 brp[1].write    = 1;
 647                 brp[1].address  = ARM11_SC7_BCR0;
 648
 649                 if (arm11_config_hardware_step)
 650                 {
 651                         /* Hardware single stepping ("instruction address
 652                          * mismatch") is used if enabled.  It's not quite
 653                          * exactly "run one instruction"; "branch to here"
 654                          * loops won't break, neither will some other cases,
 655                          * but it's probably the best default.
 656                          *
 657                          * Hardware single stepping isn't supported on v6
 658                          * debug modules.  ARM1176 and v7 can support it...
 659                          *
 660                          * FIXME Thumb stepping likely needs to use 0x03
 661                          * or 0xc0 byte masks, not 0x0f.
 662                          */
 663                          brp[0].value   = address;
 664                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 665                                         | (0 << 14) | (0 << 16) | (0 << 20)
 666                                         | (2 << 21);
 667                 } else
 668                 {
 669                         /* Sets a breakpoint on the next PC, as calculated
 670                          * by instruction set simulation.
 671                          *
 672                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 673                          * support from the simulator.
 674                          */
 675                         uint32_t next_pc;
 676                         int retval;
 677
 678                         retval = arm_simulate_step(target, &next_pc);
 679                         if (retval != ERROR_OK)
 680                                 return retval;
 681
 682                         brp[0].value    = next_pc;
 683                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 684                                         | (0 << 14) | (0 << 16) | (0 << 20)
 685                                         | (0 << 21);
 686                 }
 687
 688                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 689
 690                 /* resume */
 691
 692
 693                 if (arm11_config_step_irq_enable)
 694                         /* this disable should be redundant ... */
 695                         arm11->dscr &= ~DSCR_INT_DIS;
 696                 else
 697                         arm11->dscr |= DSCR_INT_DIS;
 698
 699
 700                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 701
 702                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 703
 704                 CHECK_RETVAL(jtag_execute_queue());
 705
 706                 /* wait for halt */
 707                 int i = 0;
 708
 709                 while (1)
 710                 {
 711                         const uint32_t mask = DSCR_CORE_RESTARTED
 712                                         | DSCR_CORE_HALTED;
 713
 714                         CHECK_RETVAL(arm11_read_DSCR(arm11));
 715                         LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
 716
 717                         if ((arm11->dscr & mask) == mask)
 718                                 break;
 719
 720                         long long then = 0;
 721                         if (i == 1000)
 722                         {
 723                                 then = timeval_ms();
 724                         }
 725                         if (i >= 1000)
 726                         {
 727                                 if ((timeval_ms()-then) > 1000)
 728                                 {
 729                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 730                                         return ERROR_FAIL;
 731                                 }
 732                         }
 733                         i++;
 734                 }
 735
 736                 /* clear breakpoint */
 737                 arm11_sc7_clear_vbw(arm11);
 738
 739                 /* save state */
 740                 CHECK_RETVAL(arm11_debug_entry(arm11));
 741
 742                 /* restore default state */
 743                 arm11->dscr &= ~DSCR_INT_DIS;
 744
 745         }
 746
 747         target->debug_reason = DBG_REASON_SINGLESTEP;
 748
 749         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 750
 751         return ERROR_OK;
 752 }
 753
 754 static int arm11_assert_reset(struct target *target)
 755 {
 756         struct arm11_common *arm11 = target_to_arm11(target);
 757
 758         /* optionally catch reset vector */
 759         if (target->reset_halt && !(arm11_vcr & 1))
 760                 arm11_sc7_set_vcr(arm11, arm11_vcr | 1);
 761
 762         /* Issue some kind of warm reset. */
 763         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 764                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 765         } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
 766                 /* REVISIT handle "pulls" cases, if there's
 767                  * hardware that needs them to work.
 768                  */
 769                 jtag_add_reset(0, 1);
 770         } else {
 771                 LOG_ERROR("%s: how to reset?", target_name(target));
 772                 return ERROR_FAIL;
 773         }
 774
 775         /* registers are now invalid */
 776         register_cache_invalidate(arm11->arm.core_cache);
 777
 778         target->state = TARGET_RESET;
 779
 780         return ERROR_OK;
 781 }
 782
 783 /*
 784  * - There is another bug in the arm11 core.  (iMX31 specific again?)
 785  *   When you generate an access to external logic (for example DDR
 786  *   controller via AHB bus) and that block is not configured (perhaps
 787  *   it is still held in reset), that transaction will never complete.
 788  *   This will hang arm11 core but it will also hang JTAG controller.
 789  *   Nothing short of srst assertion will bring it out of this.
 790  */
 791
 792 static int arm11_deassert_reset(struct target *target)
 793 {
 794         struct arm11_common *arm11 = target_to_arm11(target);
 795         int retval;
 796
 797         /* be certain SRST is off */
 798         jtag_add_reset(0, 0);
 799
 800         /* WORKAROUND i.MX31 problems:  SRST goofs the TAP, and resets
 801          * at least DSCR.  OMAP24xx doesn't show that problem, though
 802          * SRST-only reset seems to be problematic for other reasons.
 803          * (Secure boot sequences being one likelihood!)
 804          */
 805         jtag_add_tlr();
 806
 807         retval = arm11_poll(target);
 808
 809         if (target->reset_halt) {
 810                 if (target->state != TARGET_HALTED) {
 811                         LOG_WARNING("%s: ran after reset and before halt ...",
 812                                         target_name(target));
 813                         if ((retval = target_halt(target)) != ERROR_OK)
 814                                 return retval;
 815                 }
 816         }
 817
 818         /* maybe restore vector catch config */
 819         if (target->reset_halt && !(arm11_vcr & 1))
 820                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 821
 822         return ERROR_OK;
 823 }
 824
 825 static int arm11_soft_reset_halt(struct target *target)
 826 {
 827         LOG_WARNING("Not implemented: %s", __func__);
 828
 829         return ERROR_FAIL;
 830 }
 831
 832 /* target memory access
 833  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 834  * count: number of items of <size>
 835  *
 836  * arm11_config_memrw_no_increment - in the future we may want to be able
 837  * to read/write a range of data to a "port". a "port" is an action on
 838  * read memory address for some peripheral.
 839  */
 840 static int arm11_read_memory_inner(struct target *target,
 841                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 842                 bool arm11_config_memrw_no_increment)
 843 {
 844         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 845         int retval;
 846
 847         if (target->state != TARGET_HALTED)
 848         {
 849                 LOG_WARNING("target was not halted");
 850                 return ERROR_TARGET_NOT_HALTED;
 851         }
 852
 853         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 854
 855         struct arm11_common *arm11 = target_to_arm11(target);
 856
 857         retval = arm11_run_instr_data_prepare(arm11);
 858         if (retval != ERROR_OK)
 859                 return retval;
 860
 861         /* MRC p14,0,r0,c0,c5,0 */
 862         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 863         if (retval != ERROR_OK)
 864                 return retval;
 865
 866         switch (size)
 867         {
 868         case 1:
 869                 arm11->arm.core_cache->reg_list[1].dirty = true;
 870
 871                 for (size_t i = 0; i < count; i++)
 872                 {
 873                         /* ldrb    r1, [r0], #1 */
 874                         /* ldrb    r1, [r0] */
 875                         arm11_run_instr_no_data1(arm11,
 876                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 877
 878                         uint32_t res;
 879                         /* MCR p14,0,R1,c0,c5,0 */
 880                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 881
 882                         *buffer++ = res;
 883                 }
 884
 885                 break;
 886
 887         case 2:
 888                 {
 889                         arm11->arm.core_cache->reg_list[1].dirty = true;
 890
 891                         for (size_t i = 0; i < count; i++)
 892                         {
 893                                 /* ldrh    r1, [r0], #2 */
 894                                 arm11_run_instr_no_data1(arm11,
 895                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 896
 897                                 uint32_t res;
 898
 899                                 /* MCR p14,0,R1,c0,c5,0 */
 900                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 901
 902                                 uint16_t svalue = res;
 903                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 904                         }
 905
 906                         break;
 907                 }
 908
 909         case 4:
 910                 {
 911                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 912                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 913                 uint32_t *words = (uint32_t *)buffer;
 914
 915                 /* LDC p14,c5,[R0],#4 */
 916                 /* LDC p14,c5,[R0] */
 917                 arm11_run_instr_data_from_core(arm11, instr, words, count);
 918                 break;
 919                 }
 920         }
 921
 922         return arm11_run_instr_data_finish(arm11);
 923 }
 924
 925 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 926 {
 927         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 928 }
 929
 930 /*
 931 * no_increment - in the future we may want to be able
 932 * to read/write a range of data to a "port". a "port" is an action on
 933 * read memory address for some peripheral.
 934 */
 935 static int arm11_write_memory_inner(struct target *target,
 936                 uint32_t address, uint32_t size,
 937                 uint32_t count, uint8_t *buffer,
 938                 bool no_increment)
 939 {
 940         int retval;
 941
 942         if (target->state != TARGET_HALTED)
 943         {
 944                 LOG_WARNING("target was not halted");
 945                 return ERROR_TARGET_NOT_HALTED;
 946         }
 947
 948         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 949
 950         struct arm11_common *arm11 = target_to_arm11(target);
 951
 952         retval = arm11_run_instr_data_prepare(arm11);
 953         if (retval != ERROR_OK)
 954                 return retval;
 955
 956         /* load r0 with buffer address */
 957         /* MRC p14,0,r0,c0,c5,0 */
 958         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961
 962         /* burst writes are not used for single words as those may well be
 963          * reset init script writes.
 964          *
 965          * The other advantage is that as burst writes are default, we'll
 966          * now exercise both burst and non-burst code paths with the
 967          * default settings, increasing code coverage.
 968          */
 969         bool burst = arm11_config_memwrite_burst && (count > 1);
 970
 971         switch (size)
 972         {
 973         case 1:
 974                 {
 975                         arm11->arm.core_cache->reg_list[1].dirty = true;
 976
 977                         for (size_t i = 0; i < count; i++)
 978                         {
 979                                 /* load r1 from DCC with byte data */
 980                                 /* MRC p14,0,r1,c0,c5,0 */
 981                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
 982                                 if (retval != ERROR_OK)
 983                                         return retval;
 984
 985                                 /* write r1 to memory */
 986                                 /* strb    r1, [r0], #1 */
 987                                 /* strb    r1, [r0] */
 988                                 retval = arm11_run_instr_no_data1(arm11,
 989                                         !no_increment
 990                                                 ? 0xe4c01001
 991                                                 : 0xe5c01000);
 992                                 if (retval != ERROR_OK)
 993                                         return retval;
 994                         }
 995
 996                         break;
 997                 }
 998
 999         case 2:
1000                 {
1001                         arm11->arm.core_cache->reg_list[1].dirty = true;
1002
1003                         for (size_t i = 0; i < count; i++)
1004                         {
1005                                 uint16_t value;
1006                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1007
1008                                 /* load r1 from DCC with halfword data */
1009                                 /* MRC p14,0,r1,c0,c5,0 */
1010                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1011                                 if (retval != ERROR_OK)
1012                                         return retval;
1013
1014                                 /* write r1 to memory */
1015                                 /* strh    r1, [r0], #2 */
1016                                 /* strh    r1, [r0] */
1017                                 retval = arm11_run_instr_no_data1(arm11,
1018                                         !no_increment
1019                                                 ? 0xe0c010b2
1020                                                 : 0xe1c010b0);
1021                                 if (retval != ERROR_OK)
1022                                         return retval;
1023                         }
1024
1025                         break;
1026                 }
1027
1028         case 4: {
1029                 /* stream word data through DCC directly to memory */
1030                 /* increment:           STC p14,c5,[R0],#4 */
1031                 /* no increment:        STC p14,c5,[R0]*/
1032                 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1033
1034                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1035                 uint32_t *words = (uint32_t*)buffer;
1036
1037                 /* "burst" here just means trusting each instruction executes
1038                  * fully before we run the next one:  per-word roundtrips, to
1039                  * check the Ready flag, are not used.
1040                  */
1041                 if (!burst)
1042                         retval = arm11_run_instr_data_to_core(arm11,
1043                                         instr, words, count);
1044                 else
1045                         retval = arm11_run_instr_data_to_core_noack(arm11,
1046                                         instr, words, count);
1047                 if (retval != ERROR_OK)
1048                         return retval;
1049
1050                 break;
1051         }
1052         }
1053
1054         /* r0 verification */
1055         if (!no_increment)
1056         {
1057                 uint32_t r0;
1058
1059                 /* MCR p14,0,R0,c0,c5,0 */
1060                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1061                 if (retval != ERROR_OK)
1062                         return retval;
1063
1064                 if (address + size * count != r0)
1065                 {
1066                         LOG_ERROR("Data transfer failed. Expected end "
1067                                         "address 0x%08x, got 0x%08x",
1068                                         (unsigned) (address + size * count),
1069                                         (unsigned) r0);
1070
1071                         if (burst)
1072                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1073
1074                         if (arm11_config_memwrite_error_fatal)
1075                                 return ERROR_FAIL;
1076                 }
1077         }
1078
1079         return arm11_run_instr_data_finish(arm11);
1080 }
1081
1082 static int arm11_write_memory(struct target *target,
1083                 uint32_t address, uint32_t size,
1084                 uint32_t count, uint8_t *buffer)
1085 {
1086         /* pointer increment matters only for multi-unit writes ...
1087          * not e.g. to a "reset the chip" controller.
1088          */
1089         return arm11_write_memory_inner(target, address, size,
1090                         count, buffer, count == 1);
1091 }
1092
1093 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1094 static int arm11_bulk_write_memory(struct target *target,
1095                 uint32_t address, uint32_t count, uint8_t *buffer)
1096 {
1097         if (target->state != TARGET_HALTED)
1098         {
1099                 LOG_WARNING("target was not halted");
1100                 return ERROR_TARGET_NOT_HALTED;
1101         }
1102
1103         return arm11_write_memory(target, address, 4, count, buffer);
1104 }
1105
1106 /* target break-/watchpoint control
1107 * rw: 0 = write, 1 = read, 2 = access
1108 */
1109 static int arm11_add_breakpoint(struct target *target,
1110                 struct breakpoint *breakpoint)
1111 {
1112         struct arm11_common *arm11 = target_to_arm11(target);
1113
1114 #if 0
1115         if (breakpoint->type == BKPT_SOFT)
1116         {
1117                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1118                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1119         }
1120 #endif
1121
1122         if (!arm11->free_brps)
1123         {
1124                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1125                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126         }
1127
1128         if (breakpoint->length != 4)
1129         {
1130                 LOG_DEBUG("only breakpoints of four bytes length supported");
1131                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1132         }
1133
1134         arm11->free_brps--;
1135
1136         return ERROR_OK;
1137 }
1138
1139 static int arm11_remove_breakpoint(struct target *target,
1140                 struct breakpoint *breakpoint)
1141 {
1142         struct arm11_common *arm11 = target_to_arm11(target);
1143
1144         arm11->free_brps++;
1145
1146         return ERROR_OK;
1147 }
1148
1149 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1150 {
1151         struct arm11_common *arm11;
1152
1153         if (target->tap == NULL)
1154                 return ERROR_FAIL;
1155
1156         if (target->tap->ir_length != 5)
1157         {
1158                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1159                 return ERROR_COMMAND_SYNTAX_ERROR;
1160         }
1161
1162         arm11 = calloc(1, sizeof *arm11);
1163         if (!arm11)
1164                 return ERROR_FAIL;
1165
1166         arm_init_arch_info(target, &arm11->arm);
1167
1168         arm11->jtag_info.tap = target->tap;
1169         arm11->jtag_info.scann_size = 5;
1170         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1171         arm11->jtag_info.cur_scan_chain = ~0;   /* invalid/unknown */
1172         arm11->jtag_info.intest_instr = ARM11_INTEST;
1173
1174         return ERROR_OK;
1175 }
1176
1177 static int arm11_init_target(struct command_context *cmd_ctx,
1178                 struct target *target)
1179 {
1180         /* Initialize anything we can set up without talking to the target */
1181         return ERROR_OK;
1182 }
1183
1184 /* talk to the target and set things up */
1185 static int arm11_examine(struct target *target)
1186 {
1187         int retval;
1188         char *type;
1189         struct arm11_common *arm11 = target_to_arm11(target);
1190         uint32_t didr, device_id;
1191         uint8_t implementor;
1192
1193         /* FIXME split into do-first-time and do-every-time logic ... */
1194
1195         /* check IDCODE */
1196
1197         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1198
1199         struct scan_field               idcode_field;
1200
1201         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1202
1203         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1204
1205         /* check DIDR */
1206
1207         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1208
1209         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1210
1211         struct scan_field               chain0_fields[2];
1212
1213         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1214         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1215
1216         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1217
1218         CHECK_RETVAL(jtag_execute_queue());
1219
1220         /* assume the manufacturer id is ok; check the part # */
1221         switch ((device_id >> 12) & 0xFFFF)
1222         {
1223         case 0x7B36:
1224                 type = "ARM1136";
1225                 break;
1226         case 0x7B37:
1227                 type = "ARM11 MPCore";
1228                 break;
1229         case 0x7B56:
1230                 type = "ARM1156";
1231                 break;
1232         case 0x7B76:
1233                 arm11->arm.core_type = ARM_MODE_MON;
1234                 type = "ARM1176";
1235                 break;
1236         default:
1237                 LOG_ERROR("unexpected ARM11 ID code");
1238                 return ERROR_FAIL;
1239         }
1240         LOG_INFO("found %s", type);
1241
1242         /* unlikely this could ever fail, but ... */
1243         switch ((didr >> 16) & 0x0F) {
1244         case ARM11_DEBUG_V6:
1245         case ARM11_DEBUG_V61:           /* supports security extensions */
1246                 break;
1247         default:
1248                 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1249                 return ERROR_FAIL;
1250         }
1251
1252         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1253
1254         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1255         arm11->free_brps = arm11->brp;
1256
1257         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1258                         device_id, implementor, didr);
1259
1260         /* as a side-effect this reads DSCR and thus
1261          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1262          * as suggested by the spec.
1263          */
1264
1265         retval = arm11_check_init(arm11);
1266         if (retval != ERROR_OK)
1267                 return retval;
1268
1269         /* Build register cache "late", after target_init(), since we
1270          * want to know if this core supports Secure Monitor mode.
1271          */
1272         if (!target_was_examined(target))
1273                 retval = arm11_dpm_init(arm11, didr);
1274
1275         /* ETM on ARM11 still uses original scanchain 6 access mode */
1276         if (arm11->arm.etm && !target_was_examined(target)) {
1277                 *register_get_last_cache_p(&target->reg_cache) =
1278                         etm_build_reg_cache(target, &arm11->jtag_info,
1279                                         arm11->arm.etm);
1280                 retval = etm_setup(target);
1281         }
1282
1283         target_set_examined(target);
1284
1285         return ERROR_OK;
1286 }
1287
1288
1289 /* FIXME all these BOOL_WRAPPER things should be modifying
1290  * per-instance state, not shared state; ditto the vector
1291  * catch register support.  Scan chains with multiple cores
1292  * should be able to say "work with this core like this,
1293  * that core like that".  Example, ARM11 MPCore ...
1294  */
1295
1296 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1297                 COMMAND_HANDLER(arm11_handle_bool_##name) \
1298                 { \
1299                         return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1300                                         &arm11_config_##name, print_name); \
1301                 }
1302
1303 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1304 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1305 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1306 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1307
1308 COMMAND_HANDLER(arm11_handle_vcr)
1309 {
1310         switch (CMD_ARGC) {
1311         case 0:
1312                 break;
1313         case 1:
1314                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1315                 break;
1316         default:
1317                 return ERROR_COMMAND_SYNTAX_ERROR;
1318         }
1319
1320         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1321         return ERROR_OK;
1322 }
1323
1324 static const struct command_registration arm11_mw_command_handlers[] = {
1325         {
1326                 .name = "burst",
1327                 .handler = arm11_handle_bool_memwrite_burst,
1328                 .mode = COMMAND_ANY,
1329                 .help = "Display or modify flag controlling potentially "
1330                         "risky fast burst mode (default: enabled)",
1331                 .usage = "['enable'|'disable']",
1332         },
1333         {
1334                 .name = "error_fatal",
1335                 .handler = arm11_handle_bool_memwrite_error_fatal,
1336                 .mode = COMMAND_ANY,
1337                 .help = "Display or modify flag controlling transfer "
1338                         "termination on transfer errors"
1339                         " (default: enabled)",
1340                 .usage = "['enable'|'disable']",
1341         },
1342         COMMAND_REGISTRATION_DONE
1343 };
1344 static const struct command_registration arm11_any_command_handlers[] = {
1345         {
1346                 /* "hardware_step" is only here to check if the default
1347                  * simulate + breakpoint implementation is broken.
1348                  * TEMPORARY! NOT DOCUMENTED! */
1349                 .name = "hardware_step",
1350                 .handler = arm11_handle_bool_hardware_step,
1351                 .mode = COMMAND_ANY,
1352                 .help = "DEBUG ONLY - Hardware single stepping"
1353                         " (default: disabled)",
1354                 .usage = "['enable'|'disable']",
1355         },
1356         {
1357                 .name = "memwrite",
1358                 .mode = COMMAND_ANY,
1359                 .help = "memwrite command group",
1360                 .chain = arm11_mw_command_handlers,
1361         },
1362         {
1363                 .name = "step_irq_enable",
1364                 .handler = arm11_handle_bool_step_irq_enable,
1365                 .mode = COMMAND_ANY,
1366                 .help = "Display or modify flag controlling interrupt "
1367                         "enable while stepping (default: disabled)",
1368                 .usage = "['enable'|'disable']",
1369         },
1370         {
1371                 .name = "vcr",
1372                 .handler = arm11_handle_vcr,
1373                 .mode = COMMAND_ANY,
1374                 .help = "Display or modify Vector Catch Register",
1375                 .usage = "[value]",
1376         },
1377         COMMAND_REGISTRATION_DONE
1378 };
1379 static const struct command_registration arm11_command_handlers[] = {
1380         {
1381                 .chain = arm_command_handlers,
1382         },
1383         {
1384                 .chain = etm_command_handlers,
1385         },
1386         {
1387                 .name = "arm11",
1388                 .mode = COMMAND_ANY,
1389                 .help = "ARM11 command group",
1390                 .chain = arm11_any_command_handlers,
1391         },
1392         COMMAND_REGISTRATION_DONE
1393 };
1394
1395 /** Holds methods for ARM11xx targets. */
1396 struct target_type arm11_target = {
1397         .name =                 "arm11",
1398
1399         .poll =                 arm11_poll,
1400         .arch_state =           arm11_arch_state,
1401
1402         .target_request_data =  arm11_target_request_data,
1403
1404         .halt =                 arm11_halt,
1405         .resume =               arm11_resume,
1406         .step =                 arm11_step,
1407
1408         .assert_reset =         arm11_assert_reset,
1409         .deassert_reset =       arm11_deassert_reset,
1410         .soft_reset_halt =      arm11_soft_reset_halt,
1411
1412         .get_gdb_reg_list =     arm_get_gdb_reg_list,
1413
1414         .read_memory =          arm11_read_memory,
1415         .write_memory =         arm11_write_memory,
1416
1417         .bulk_write_memory =    arm11_bulk_write_memory,
1418
1419         .checksum_memory =      arm_checksum_memory,
1420         .blank_check_memory =   arm_blank_check_memory,
1421
1422         .add_breakpoint =       arm11_add_breakpoint,
1423         .remove_breakpoint =    arm11_remove_breakpoint,
1424
1425         .run_algorithm =        armv4_5_run_algorithm,
1426
1427         .commands =             arm11_command_handlers,
1428         .target_create =        arm11_target_create,
1429         .init_target =          arm11_init_target,
1430         .examine =              arm11_examine,
1431 };