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ARM: keep a handle to the PC
[openocd/ellerodev.git] / src / target / cortex_m3.c
bloba3b3d425a9b2dabb2e7ea85f7aee7908a2db47a2
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
58 static void cortex_m3_enable_watchpoints(struct target *target);
59 static int cortex_m3_store_core_reg_u32(struct target *target,
60 enum armv7m_regtype type, uint32_t num, uint32_t value);
61
62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
63 uint32_t *value, int regnum)
64 {
65 int retval;
66 uint32_t dcrdr;
67
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
70
71 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
72
73 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
74
75 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
76 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
77 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
78
79 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
80 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
81 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
82
83 retval = jtagdp_transaction_endcheck(swjdp);
84
85 /* restore DCB_DCRDR - this needs to be in a seperate
86 * transaction otherwise the emulated DCC channel breaks */
87 if (retval == ERROR_OK)
88 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
89
90 return retval;
91 }
92
93 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
94 uint32_t value, int regnum)
95 {
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101
102 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
103
104 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
105
106 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
107 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
108 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
109
110 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
111 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
112 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
113
114 retval = jtagdp_transaction_endcheck(swjdp);
115
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
120
121 return retval;
122 }
123
124 static int cortex_m3_write_debug_halt_mask(struct target *target,
125 uint32_t mask_on, uint32_t mask_off)
126 {
127 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
128 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
129
130 /* mask off status bits */
131 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
132 /* create new register mask */
133 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
134
135 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
136 }
137
138 static int cortex_m3_clear_halt(struct target *target)
139 {
140 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
141 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
142
143 /* clear step if any */
144 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
145
146 /* Read Debug Fault Status Register */
147 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
148
149 /* Clear Debug Fault Status */
150 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
151 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
152
153 return ERROR_OK;
154 }
155
156 static int cortex_m3_single_step_core(struct target *target)
157 {
158 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
159 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
160 uint32_t dhcsr_save;
161
162 /* backup dhcsr reg */
163 dhcsr_save = cortex_m3->dcb_dhcsr;
164
165 /* Mask interrupts before clearing halt, if done already. This avoids
166 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
167 * HALT can put the core into an unknown state.
168 */
169 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
170 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
171 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
172 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
173 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
174 LOG_DEBUG(" ");
175
176 /* restore dhcsr reg */
177 cortex_m3->dcb_dhcsr = dhcsr_save;
178 cortex_m3_clear_halt(target);
179
180 return ERROR_OK;
181 }
182
183 static int cortex_m3_endreset_event(struct target *target)
184 {
185 int i;
186 uint32_t dcb_demcr;
187 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
188 struct armv7m_common *armv7m = &cortex_m3->armv7m;
189 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
190 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
191 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
192
193 /* REVISIT The four debug monitor bits are currently ignored... */
194 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
195 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
196
197 /* this register is used for emulated dcc channel */
198 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
199
200 /* Enable debug requests */
201 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
202 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
203 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
204
205 /* clear any interrupt masking */
206 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
207
208 /* Enable features controlled by ITM and DWT blocks, and catch only
209 * the vectors we were told to pay attention to.
210 *
211 * Target firmware is responsible for all fault handling policy
212 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
213 * or manual updates to the NVIC SHCSR and CCR registers.
214 */
215 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
216
217 /* Paranoia: evidently some (early?) chips don't preserve all the
218 * debug state (including FBP, DWT, etc) across reset...
219 */
220
221 /* Enable FPB */
222 target_write_u32(target, FP_CTRL, 3);
223 cortex_m3->fpb_enabled = 1;
224
225 /* Restore FPB registers */
226 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
227 {
228 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
229 }
230
231 /* Restore DWT registers */
232 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
233 {
234 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
235 dwt_list[i].comp);
236 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
237 dwt_list[i].mask);
238 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
239 dwt_list[i].function);
240 }
241 jtagdp_transaction_endcheck(swjdp);
242
243 register_cache_invalidate(cortex_m3->armv7m.core_cache);
244
245 /* make sure we have latest dhcsr flags */
246 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
247
248 return ERROR_OK;
249 }
250
251 static int cortex_m3_examine_debug_reason(struct target *target)
252 {
253 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
254
255 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
256 /* only check the debug reason if we don't know it already */
257
258 if ((target->debug_reason != DBG_REASON_DBGRQ)
259 && (target->debug_reason != DBG_REASON_SINGLESTEP))
260 {
261 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
262 {
263 target->debug_reason = DBG_REASON_BREAKPOINT;
264 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
265 target->debug_reason = DBG_REASON_WPTANDBKPT;
266 }
267 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
268 target->debug_reason = DBG_REASON_WATCHPOINT;
269 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
270 target->debug_reason = DBG_REASON_BREAKPOINT;
271 else /* EXTERNAL, HALTED */
272 target->debug_reason = DBG_REASON_UNDEFINED;
273 }
274
275 return ERROR_OK;
276 }
277
278 static int cortex_m3_examine_exception_reason(struct target *target)
279 {
280 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
281 struct armv7m_common *armv7m = target_to_armv7m(target);
282 struct swjdp_common *swjdp = &armv7m->swjdp_info;
283
284 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
285 switch (armv7m->exception_number)
286 {
287 case 2: /* NMI */
288 break;
289 case 3: /* Hard Fault */
290 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
291 if (except_sr & 0x40000000)
292 {
293 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
294 }
295 break;
296 case 4: /* Memory Management */
297 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
298 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
299 break;
300 case 5: /* Bus Fault */
301 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
302 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
303 break;
304 case 6: /* Usage Fault */
305 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
306 break;
307 case 11: /* SVCall */
308 break;
309 case 12: /* Debug Monitor */
310 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
311 break;
312 case 14: /* PendSV */
313 break;
314 case 15: /* SysTick */
315 break;
316 default:
317 except_sr = 0;
318 break;
319 }
320 jtagdp_transaction_endcheck(swjdp);
321 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
322 shcsr, except_sr, cfsr, except_ar);
323 return ERROR_OK;
324 }
325
326 /* PSP is used in some thread modes */
327 static const int armv7m_psp_reg_map[17] = {
328 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
329 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
330 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
331 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
332 ARMV7M_xPSR,
333 };
334
335 /* MSP is used in handler and some thread modes */
336 static const int armv7m_msp_reg_map[17] = {
337 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
338 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
339 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
340 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
341 ARMV7M_xPSR,
342 };
343
344 static int cortex_m3_debug_entry(struct target *target)
345 {
346 int i;
347 uint32_t xPSR;
348 int retval;
349 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
350 struct armv7m_common *armv7m = &cortex_m3->armv7m;
351 struct arm *arm = &armv7m->arm;
352 struct swjdp_common *swjdp = &armv7m->swjdp_info;
353 struct reg *r;
354
355 LOG_DEBUG(" ");
356
357 cortex_m3_clear_halt(target);
358 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
359
360 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
361 return retval;
362
363 /* Examine target state and mode */
364 /* First load register acessible through core debug port*/
365 int num_regs = armv7m->core_cache->num_regs;
366
367 for (i = 0; i < num_regs; i++)
368 {
369 if (!armv7m->core_cache->reg_list[i].valid)
370 armv7m->read_core_reg(target, i);
371 }
372
373 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
374 xPSR = buf_get_u32(r->value, 0, 32);
375
376 #ifdef ARMV7_GDB_HACKS
377 /* FIXME this breaks on scan chains with more than one Cortex-M3.
378 * Instead, each CM3 should have its own dummy value...
379 */
380 /* copy real xpsr reg for gdb, setting thumb bit */
381 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
382 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
383 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
384 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
385 #endif
386
387 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
388 if (xPSR & 0xf00)
389 {
390 r->dirty = r->valid;
391 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
392 }
393
394 /* Are we in an exception handler */
395 if (xPSR & 0x1FF)
396 {
397 armv7m->core_mode = ARMV7M_MODE_HANDLER;
398 armv7m->exception_number = (xPSR & 0x1FF);
399
400 arm->core_mode = ARM_MODE_HANDLER;
401 arm->map = armv7m_msp_reg_map;
402 }
403 else
404 {
405 unsigned control = buf_get_u32(armv7m->core_cache
406 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
407
408 /* is this thread privileged? */
409 armv7m->core_mode = control & 1;
410 arm->core_mode = armv7m->core_mode
411 ? ARM_MODE_USER_THREAD
412 : ARM_MODE_THREAD;
413
414 /* which stack is it using? */
415 if (control & 2)
416 arm->map = armv7m_psp_reg_map;
417 else
418 arm->map = armv7m_msp_reg_map;
419
420 armv7m->exception_number = 0;
421 }
422
423 if (armv7m->exception_number)
424 {
425 cortex_m3_examine_exception_reason(target);
426 }
427
428 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
429 armv7m_mode_strings[armv7m->core_mode],
430 *(uint32_t*)(arm->pc->value),
431 target_state_name(target));
432
433 if (armv7m->post_debug_entry)
434 armv7m->post_debug_entry(target);
435
436 return ERROR_OK;
437 }
438
439 static int cortex_m3_poll(struct target *target)
440 {
441 int retval;
442 enum target_state prev_target_state = target->state;
443 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
444 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
445
446 /* Read from Debug Halting Control and Status Register */
447 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
448 if (retval != ERROR_OK)
449 {
450 target->state = TARGET_UNKNOWN;
451 return retval;
452 }
453
454 /* Recover from lockup. See ARMv7-M architecture spec,
455 * section B1.5.15 "Unrecoverable exception cases".
456 *
457 * REVISIT Is there a better way to report and handle this?
458 */
459 if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
460 LOG_WARNING("%s -- clearing lockup after double fault",
461 target_name(target));
462 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
463 target->debug_reason = DBG_REASON_DBGRQ;
464
465 /* refresh status bits */
466 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
467 }
468
469 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
470 {
471 /* check if still in reset */
472 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
473
474 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
475 {
476 target->state = TARGET_RESET;
477 return ERROR_OK;
478 }
479 }
480
481 if (target->state == TARGET_RESET)
482 {
483 /* Cannot switch context while running so endreset is
484 * called with target->state == TARGET_RESET
485 */
486 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
487 cortex_m3->dcb_dhcsr);
488 cortex_m3_endreset_event(target);
489 target->state = TARGET_RUNNING;
490 prev_target_state = TARGET_RUNNING;
491 }
492
493 if (cortex_m3->dcb_dhcsr & S_HALT)
494 {
495 target->state = TARGET_HALTED;
496
497 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
498 {
499 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
500 return retval;
501
502 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
503 }
504 if (prev_target_state == TARGET_DEBUG_RUNNING)
505 {
506 LOG_DEBUG(" ");
507 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
508 return retval;
509
510 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
511 }
512 }
513
514 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
515 * How best to model low power modes?
516 */
517
518 if (target->state == TARGET_UNKNOWN)
519 {
520 /* check if processor is retiring instructions */
521 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
522 {
523 target->state = TARGET_RUNNING;
524 return ERROR_OK;
525 }
526 }
527
528 return ERROR_OK;
529 }
530
531 static int cortex_m3_halt(struct target *target)
532 {
533 LOG_DEBUG("target->state: %s",
534 target_state_name(target));
535
536 if (target->state == TARGET_HALTED)
537 {
538 LOG_DEBUG("target was already halted");
539 return ERROR_OK;
540 }
541
542 if (target->state == TARGET_UNKNOWN)
543 {
544 LOG_WARNING("target was in unknown state when halt was requested");
545 }
546
547 if (target->state == TARGET_RESET)
548 {
549 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
550 {
551 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
552 return ERROR_TARGET_FAILURE;
553 }
554 else
555 {
556 /* we came here in a reset_halt or reset_init sequence
557 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
558 */
559 target->debug_reason = DBG_REASON_DBGRQ;
560
561 return ERROR_OK;
562 }
563 }
564
565 /* Write to Debug Halting Control and Status Register */
566 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
567
568 target->debug_reason = DBG_REASON_DBGRQ;
569
570 return ERROR_OK;
571 }
572
573 static int cortex_m3_soft_reset_halt(struct target *target)
574 {
575 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
576 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
577 uint32_t dcb_dhcsr = 0;
578 int retval, timeout = 0;
579
580 /* Enter debug state on reset; restore DEMCR in endreset_event() */
581 mem_ap_write_u32(swjdp, DCB_DEMCR,
582 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
583
584 /* Request a core-only reset */
585 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
586 AIRCR_VECTKEY | AIRCR_VECTRESET);
587 target->state = TARGET_RESET;
588
589 /* registers are now invalid */
590 register_cache_invalidate(cortex_m3->armv7m.core_cache);
591
592 while (timeout < 100)
593 {
594 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
595 if (retval == ERROR_OK)
596 {
597 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
598 &cortex_m3->nvic_dfsr);
599 if ((dcb_dhcsr & S_HALT)
600 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
601 {
602 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
603 "DFSR 0x%08x",
604 (unsigned) dcb_dhcsr,
605 (unsigned) cortex_m3->nvic_dfsr);
606 cortex_m3_poll(target);
607 /* FIXME restore user's vector catch config */
608 return ERROR_OK;
609 }
610 else
611 LOG_DEBUG("waiting for system reset-halt, "
612 "DHCSR 0x%08x, %d ms",
613 (unsigned) dcb_dhcsr, timeout);
614 }
615 timeout++;
616 alive_sleep(1);
617 }
618
619 return ERROR_OK;
620 }
621
622 static void cortex_m3_enable_breakpoints(struct target *target)
623 {
624 struct breakpoint *breakpoint = target->breakpoints;
625
626 /* set any pending breakpoints */
627 while (breakpoint)
628 {
629 if (!breakpoint->set)
630 cortex_m3_set_breakpoint(target, breakpoint);
631 breakpoint = breakpoint->next;
632 }
633 }
634
635 static int cortex_m3_resume(struct target *target, int current,
636 uint32_t address, int handle_breakpoints, int debug_execution)
637 {
638 struct armv7m_common *armv7m = target_to_armv7m(target);
639 struct breakpoint *breakpoint = NULL;
640 uint32_t resume_pc;
641 struct reg *r;
642
643 if (target->state != TARGET_HALTED)
644 {
645 LOG_WARNING("target not halted");
646 return ERROR_TARGET_NOT_HALTED;
647 }
648
649 if (!debug_execution)
650 {
651 target_free_all_working_areas(target);
652 cortex_m3_enable_breakpoints(target);
653 cortex_m3_enable_watchpoints(target);
654 }
655
656 if (debug_execution)
657 {
658 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
659
660 /* Disable interrupts */
661 /* We disable interrupts in the PRIMASK register instead of
662 * masking with C_MASKINTS. This is probably the same issue
663 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
664 * in parallel with disabled interrupts can cause local faults
665 * to not be taken.
666 *
667 * REVISIT this clearly breaks non-debug execution, since the
668 * PRIMASK register state isn't saved/restored... workaround
669 * by never resuming app code after debug execution.
670 */
671 buf_set_u32(r->value, 0, 1, 1);
672 r->dirty = true;
673 r->valid = true;
674
675 /* Make sure we are in Thumb mode */
676 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
677 buf_set_u32(r->value, 24, 1, 1);
678 r->dirty = true;
679 r->valid = true;
680 }
681
682 /* current = 1: continue on current pc, otherwise continue at <address> */
683 r = armv7m->arm.pc;
684 if (!current)
685 {
686 buf_set_u32(r->value, 0, 32, address);
687 r->dirty = true;
688 r->valid = true;
689 }
690
691 /* if we halted last time due to a bkpt instruction
692 * then we have to manually step over it, otherwise
693 * the core will break again */
694
695 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
696 && !debug_execution)
697 {
698 armv7m_maybe_skip_bkpt_inst(target, NULL);
699 }
700
701 resume_pc = buf_get_u32(r->value, 0, 32);
702
703 armv7m_restore_context(target);
704
705 /* the front-end may request us not to handle breakpoints */
706 if (handle_breakpoints)
707 {
708 /* Single step past breakpoint at current address */
709 if ((breakpoint = breakpoint_find(target, resume_pc)))
710 {
711 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
712 breakpoint->address,
713 breakpoint->unique_id);
714 cortex_m3_unset_breakpoint(target, breakpoint);
715 cortex_m3_single_step_core(target);
716 cortex_m3_set_breakpoint(target, breakpoint);
717 }
718 }
719
720 /* Restart core */
721 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
722
723 target->debug_reason = DBG_REASON_NOTHALTED;
724
725 /* registers are now invalid */
726 register_cache_invalidate(armv7m->core_cache);
727
728 if (!debug_execution)
729 {
730 target->state = TARGET_RUNNING;
731 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
732 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
733 }
734 else
735 {
736 target->state = TARGET_DEBUG_RUNNING;
737 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
738 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
739 }
740
741 return ERROR_OK;
742 }
743
744 /* int irqstepcount = 0; */
745 static int cortex_m3_step(struct target *target, int current,
746 uint32_t address, int handle_breakpoints)
747 {
748 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
749 struct armv7m_common *armv7m = &cortex_m3->armv7m;
750 struct swjdp_common *swjdp = &armv7m->swjdp_info;
751 struct breakpoint *breakpoint = NULL;
752 struct reg *pc = armv7m->arm.pc;
753 bool bkpt_inst_found = false;
754
755 if (target->state != TARGET_HALTED)
756 {
757 LOG_WARNING("target not halted");
758 return ERROR_TARGET_NOT_HALTED;
759 }
760
761 /* current = 1: continue on current pc, otherwise continue at <address> */
762 if (!current)
763 buf_set_u32(pc->value, 0, 32, address);
764
765 /* the front-end may request us not to handle breakpoints */
766 if (handle_breakpoints) {
767 breakpoint = breakpoint_find(target,
768 buf_get_u32(pc->value, 0, 32));
769 if (breakpoint)
770 cortex_m3_unset_breakpoint(target, breakpoint);
771 }
772
773 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
774
775 target->debug_reason = DBG_REASON_SINGLESTEP;
776
777 armv7m_restore_context(target);
778
779 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
780
781 /* if no bkpt instruction is found at pc then we can perform
782 * a normal step, otherwise we have to manually step over the bkpt
783 * instruction - as such simulate a step */
784 if (bkpt_inst_found == false)
785 {
786 /* set step and clear halt */
787 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
788 }
789
790 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
791
792 /* registers are now invalid */
793 register_cache_invalidate(cortex_m3->armv7m.core_cache);
794
795 if (breakpoint)
796 cortex_m3_set_breakpoint(target, breakpoint);
797
798 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
799 " nvic_icsr = 0x%" PRIx32,
800 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
801
802 cortex_m3_debug_entry(target);
803 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
804
805 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
806 " nvic_icsr = 0x%" PRIx32,
807 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
808
809 return ERROR_OK;
810 }
811
812 static int cortex_m3_assert_reset(struct target *target)
813 {
814 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
815 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
816 int assert_srst = 1;
817
818 LOG_DEBUG("target->state: %s",
819 target_state_name(target));
820
821 enum reset_types jtag_reset_config = jtag_get_reset_config();
822
823 /*
824 * We can reset Cortex-M3 targets using just the NVIC without
825 * requiring SRST, getting a SoC reset (or a core-only reset)
826 * instead of a system reset.
827 */
828 if (!(jtag_reset_config & RESET_HAS_SRST))
829 assert_srst = 0;
830
831 /* Enable debug requests */
832 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
833 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
834 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
835
836 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
837
838 if (!target->reset_halt)
839 {
840 /* Set/Clear C_MASKINTS in a separate operation */
841 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
842 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
843 DBGKEY | C_DEBUGEN | C_HALT);
844
845 /* clear any debug flags before resuming */
846 cortex_m3_clear_halt(target);
847
848 /* clear C_HALT in dhcsr reg */
849 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
850 }
851 else
852 {
853 /* Halt in debug on reset; endreset_event() restores DEMCR.
854 *
855 * REVISIT catching BUSERR presumably helps to defend against
856 * bad vector table entries. Should this include MMERR or
857 * other flags too?
858 */
859 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
860 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
861 }
862
863 /*
864 * When nRST is asserted on most Stellaris devices, it clears some of
865 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
866 * and OpenOCD depends on those TRMs. So we won't use SRST on those
867 * chips. (Only power-on reset should affect debug state, beyond a
868 * few specified bits; not the chip's nRST input, wired to SRST.)
869 *
870 * REVISIT current errata specs don't seem to cover this issue.
871 * Do we have more details than this email?
872 * https://lists.berlios.de/pipermail
873 * /openocd-development/2008-August/003065.html
874 */
875 if (strcmp(target->variant, "lm3s") == 0)
876 {
877 /* Check for silicon revisions with the issue. */
878 uint32_t did0;
879
880 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
881 {
882 switch ((did0 >> 16) & 0xff)
883 {
884 case 0:
885 /* all Sandstorm suffer issue */
886 assert_srst = 0;
887 break;
888
889 case 1:
890 case 3:
891 /* Fury and DustDevil rev A have
892 * this nRST problem. It should
893 * be fixed in rev B silicon.
894 */
895 if (((did0 >> 8) & 0xff) == 0)
896 assert_srst = 0;
897 break;
898 case 4:
899 /* Tempest should be fine. */
900 break;
901 }
902 }
903 }
904
905 if (assert_srst)
906 {
907 /* default to asserting srst */
908 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
909 {
910 jtag_add_reset(1, 1);
911 }
912 else
913 {
914 jtag_add_reset(0, 1);
915 }
916 }
917 else
918 {
919 /* Use a standard Cortex-M3 software reset mechanism.
920 * SYSRESETREQ will reset SoC peripherals outside the
921 * core, like watchdog timers, if the SoC wires it up
922 * correctly. Else VECRESET can reset just the core.
923 */
924 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
925 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
926 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
927
928 {
929 /* I do not know why this is necessary, but it
930 * fixes strange effects (step/resume cause NMI
931 * after reset) on LM3S6918 -- Michael Schwingen
932 */
933 uint32_t tmp;
934 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
935 }
936 }
937
938 target->state = TARGET_RESET;
939 jtag_add_sleep(50000);
940
941 register_cache_invalidate(cortex_m3->armv7m.core_cache);
942
943 if (target->reset_halt)
944 {
945 int retval;
946 if ((retval = target_halt(target)) != ERROR_OK)
947 return retval;
948 }
949
950 return ERROR_OK;
951 }
952
953 static int cortex_m3_deassert_reset(struct target *target)
954 {
955 LOG_DEBUG("target->state: %s",
956 target_state_name(target));
957
958 /* deassert reset lines */
959 jtag_add_reset(0, 0);
960
961 return ERROR_OK;
962 }
963
964 static int
965 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
966 {
967 int retval;
968 int fp_num = 0;
969 uint32_t hilo;
970 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
971 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
972
973 if (breakpoint->set)
974 {
975 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
976 return ERROR_OK;
977 }
978
979 if (cortex_m3->auto_bp_type)
980 {
981 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
982 }
983
984 if (breakpoint->type == BKPT_HARD)
985 {
986 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
987 fp_num++;
988 if (fp_num >= cortex_m3->fp_num_code)
989 {
990 LOG_ERROR("Can not find free FPB Comparator!");
991 return ERROR_FAIL;
992 }
993 breakpoint->set = fp_num + 1;
994 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
995 comparator_list[fp_num].used = 1;
996 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
997 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
998 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
999 if (!cortex_m3->fpb_enabled)
1000 {
1001 LOG_DEBUG("FPB wasn't enabled, do it now");
1002 target_write_u32(target, FP_CTRL, 3);
1003 }
1004 }
1005 else if (breakpoint->type == BKPT_SOFT)
1006 {
1007 uint8_t code[4];
1008
1009 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1010 * semihosting; don't use that. Otherwise the BKPT
1011 * parameter is arbitrary.
1012 */
1013 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1014 retval = target_read_memory(target,
1015 breakpoint->address & 0xFFFFFFFE,
1016 breakpoint->length, 1,
1017 breakpoint->orig_instr);
1018 if (retval != ERROR_OK)
1019 return retval;
1020 retval = target_write_memory(target,
1021 breakpoint->address & 0xFFFFFFFE,
1022 breakpoint->length, 1,
1023 code);
1024 if (retval != ERROR_OK)
1025 return retval;
1026 breakpoint->set = true;
1027 }
1028
1029 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1030 breakpoint->unique_id,
1031 (int)(breakpoint->type),
1032 breakpoint->address,
1033 breakpoint->length,
1034 breakpoint->set);
1035
1036 return ERROR_OK;
1037 }
1038
1039 static int
1040 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1041 {
1042 int retval;
1043 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1044 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1045
1046 if (!breakpoint->set)
1047 {
1048 LOG_WARNING("breakpoint not set");
1049 return ERROR_OK;
1050 }
1051
1052 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1053 breakpoint->unique_id,
1054 (int)(breakpoint->type),
1055 breakpoint->address,
1056 breakpoint->length,
1057 breakpoint->set);
1058
1059 if (breakpoint->type == BKPT_HARD)
1060 {
1061 int fp_num = breakpoint->set - 1;
1062 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1063 {
1064 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1065 return ERROR_OK;
1066 }
1067 comparator_list[fp_num].used = 0;
1068 comparator_list[fp_num].fpcr_value = 0;
1069 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1070 }
1071 else
1072 {
1073 /* restore original instruction (kept in target endianness) */
1074 if (breakpoint->length == 4)
1075 {
1076 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1077 {
1078 return retval;
1079 }
1080 }
1081 else
1082 {
1083 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1084 {
1085 return retval;
1086 }
1087 }
1088 }
1089 breakpoint->set = false;
1090
1091 return ERROR_OK;
1092 }
1093
1094 static int
1095 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1096 {
1097 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1098
1099 if (cortex_m3->auto_bp_type)
1100 {
1101 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1102 #ifdef ARMV7_GDB_HACKS
1103 if (breakpoint->length != 2) {
1104 /* XXX Hack: Replace all breakpoints with length != 2 with
1105 * a hardware breakpoint. */
1106 breakpoint->type = BKPT_HARD;
1107 breakpoint->length = 2;
1108 }
1109 #endif
1110 }
1111
1112 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1113 {
1114 LOG_INFO("flash patch comparator requested outside code memory region");
1115 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1116 }
1117
1118 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1119 {
1120 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1121 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1122 }
1123
1124 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1125 {
1126 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1127 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1128 }
1129
1130 if ((breakpoint->length != 2))
1131 {
1132 LOG_INFO("only breakpoints of two bytes length supported");
1133 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1134 }
1135
1136 if (breakpoint->type == BKPT_HARD)
1137 cortex_m3->fp_code_available--;
1138 cortex_m3_set_breakpoint(target, breakpoint);
1139
1140 return ERROR_OK;
1141 }
1142
1143 static int
1144 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1145 {
1146 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1147
1148 /* REVISIT why check? FBP can be updated with core running ... */
1149 if (target->state != TARGET_HALTED)
1150 {
1151 LOG_WARNING("target not halted");
1152 return ERROR_TARGET_NOT_HALTED;
1153 }
1154
1155 if (cortex_m3->auto_bp_type)
1156 {
1157 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1158 }
1159
1160 if (breakpoint->set)
1161 {
1162 cortex_m3_unset_breakpoint(target, breakpoint);
1163 }
1164
1165 if (breakpoint->type == BKPT_HARD)
1166 cortex_m3->fp_code_available++;
1167
1168 return ERROR_OK;
1169 }
1170
1171 static int
1172 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1173 {
1174 int dwt_num = 0;
1175 uint32_t mask, temp;
1176 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1177
1178 /* watchpoint params were validated earlier */
1179 mask = 0;
1180 temp = watchpoint->length;
1181 while (temp) {
1182 temp >>= 1;
1183 mask++;
1184 }
1185 mask--;
1186
1187 /* REVISIT Don't fully trust these "not used" records ... users
1188 * may set up breakpoints by hand, e.g. dual-address data value
1189 * watchpoint using comparator #1; comparator #0 matching cycle
1190 * count; send data trace info through ITM and TPIU; etc
1191 */
1192 struct cortex_m3_dwt_comparator *comparator;
1193
1194 for (comparator = cortex_m3->dwt_comparator_list;
1195 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1196 comparator++, dwt_num++)
1197 continue;
1198 if (dwt_num >= cortex_m3->dwt_num_comp)
1199 {
1200 LOG_ERROR("Can not find free DWT Comparator");
1201 return ERROR_FAIL;
1202 }
1203 comparator->used = 1;
1204 watchpoint->set = dwt_num + 1;
1205
1206 comparator->comp = watchpoint->address;
1207 target_write_u32(target, comparator->dwt_comparator_address + 0,
1208 comparator->comp);
1209
1210 comparator->mask = mask;
1211 target_write_u32(target, comparator->dwt_comparator_address + 4,
1212 comparator->mask);
1213
1214 switch (watchpoint->rw) {
1215 case WPT_READ:
1216 comparator->function = 5;
1217 break;
1218 case WPT_WRITE:
1219 comparator->function = 6;
1220 break;
1221 case WPT_ACCESS:
1222 comparator->function = 7;
1223 break;
1224 }
1225 target_write_u32(target, comparator->dwt_comparator_address + 8,
1226 comparator->function);
1227
1228 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1229 watchpoint->unique_id, dwt_num,
1230 (unsigned) comparator->comp,
1231 (unsigned) comparator->mask,
1232 (unsigned) comparator->function);
1233 return ERROR_OK;
1234 }
1235
1236 static int
1237 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1238 {
1239 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1240 struct cortex_m3_dwt_comparator *comparator;
1241 int dwt_num;
1242
1243 if (!watchpoint->set)
1244 {
1245 LOG_WARNING("watchpoint (wpid: %d) not set",
1246 watchpoint->unique_id);
1247 return ERROR_OK;
1248 }
1249
1250 dwt_num = watchpoint->set - 1;
1251
1252 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1253 watchpoint->unique_id, dwt_num,
1254 (unsigned) watchpoint->address);
1255
1256 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1257 {
1258 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1259 return ERROR_OK;
1260 }
1261
1262 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1263 comparator->used = 0;
1264 comparator->function = 0;
1265 target_write_u32(target, comparator->dwt_comparator_address + 8,
1266 comparator->function);
1267
1268 watchpoint->set = false;
1269
1270 return ERROR_OK;
1271 }
1272
1273 static int
1274 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1275 {
1276 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1277
1278 if (cortex_m3->dwt_comp_available < 1)
1279 {
1280 LOG_DEBUG("no comparators?");
1281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1282 }
1283
1284 /* hardware doesn't support data value masking */
1285 if (watchpoint->mask != ~(uint32_t)0) {
1286 LOG_DEBUG("watchpoint value masks not supported");
1287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1288 }
1289
1290 /* hardware allows address masks of up to 32K */
1291 unsigned mask;
1292
1293 for (mask = 0; mask < 16; mask++) {
1294 if ((1u << mask) == watchpoint->length)
1295 break;
1296 }
1297 if (mask == 16) {
1298 LOG_DEBUG("unsupported watchpoint length");
1299 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1300 }
1301 if (watchpoint->address & ((1 << mask) - 1)) {
1302 LOG_DEBUG("watchpoint address is unaligned");
1303 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1304 }
1305
1306 /* Caller doesn't seem to be able to describe watching for data
1307 * values of zero; that flags "no value".
1308 *
1309 * REVISIT This DWT may well be able to watch for specific data
1310 * values. Requires comparator #1 to set DATAVMATCH and match
1311 * the data, and another comparator (DATAVADDR0) matching addr.
1312 */
1313 if (watchpoint->value) {
1314 LOG_DEBUG("data value watchpoint not YET supported");
1315 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1316 }
1317
1318 cortex_m3->dwt_comp_available--;
1319 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1320
1321 return ERROR_OK;
1322 }
1323
1324 static int
1325 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1326 {
1327 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1328
1329 /* REVISIT why check? DWT can be updated with core running ... */
1330 if (target->state != TARGET_HALTED)
1331 {
1332 LOG_WARNING("target not halted");
1333 return ERROR_TARGET_NOT_HALTED;
1334 }
1335
1336 if (watchpoint->set)
1337 {
1338 cortex_m3_unset_watchpoint(target, watchpoint);
1339 }
1340
1341 cortex_m3->dwt_comp_available++;
1342 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1343
1344 return ERROR_OK;
1345 }
1346
1347 static void cortex_m3_enable_watchpoints(struct target *target)
1348 {
1349 struct watchpoint *watchpoint = target->watchpoints;
1350
1351 /* set any pending watchpoints */
1352 while (watchpoint)
1353 {
1354 if (!watchpoint->set)
1355 cortex_m3_set_watchpoint(target, watchpoint);
1356 watchpoint = watchpoint->next;
1357 }
1358 }
1359
1360 static int cortex_m3_load_core_reg_u32(struct target *target,
1361 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1362 {
1363 int retval;
1364 struct armv7m_common *armv7m = target_to_armv7m(target);
1365 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1366
1367 /* NOTE: we "know" here that the register identifiers used
1368 * in the v7m header match the Cortex-M3 Debug Core Register
1369 * Selector values for R0..R15, xPSR, MSP, and PSP.
1370 */
1371 switch (num) {
1372 case 0 ... 18:
1373 /* read a normal core register */
1374 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1375
1376 if (retval != ERROR_OK)
1377 {
1378 LOG_ERROR("JTAG failure %i",retval);
1379 return ERROR_JTAG_DEVICE_ERROR;
1380 }
1381 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1382 break;
1383
1384 case ARMV7M_PRIMASK:
1385 case ARMV7M_BASEPRI:
1386 case ARMV7M_FAULTMASK:
1387 case ARMV7M_CONTROL:
1388 /* Cortex-M3 packages these four registers as bitfields
1389 * in one Debug Core register. So say r0 and r2 docs;
1390 * it was removed from r1 docs, but still works.
1391 */
1392 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1393
1394 switch (num)
1395 {
1396 case ARMV7M_PRIMASK:
1397 *value = buf_get_u32((uint8_t*)value, 0, 1);
1398 break;
1399
1400 case ARMV7M_BASEPRI:
1401 *value = buf_get_u32((uint8_t*)value, 8, 8);
1402 break;
1403
1404 case ARMV7M_FAULTMASK:
1405 *value = buf_get_u32((uint8_t*)value, 16, 1);
1406 break;
1407
1408 case ARMV7M_CONTROL:
1409 *value = buf_get_u32((uint8_t*)value, 24, 2);
1410 break;
1411 }
1412
1413 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1414 break;
1415
1416 default:
1417 return ERROR_INVALID_ARGUMENTS;
1418 }
1419
1420 return ERROR_OK;
1421 }
1422
1423 static int cortex_m3_store_core_reg_u32(struct target *target,
1424 enum armv7m_regtype type, uint32_t num, uint32_t value)
1425 {
1426 int retval;
1427 uint32_t reg;
1428 struct armv7m_common *armv7m = target_to_armv7m(target);
1429 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1430
1431 #ifdef ARMV7_GDB_HACKS
1432 /* If the LR register is being modified, make sure it will put us
1433 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1434 * hack to deal with the fact that gdb will sometimes "forge"
1435 * return addresses, and doesn't set the LSB correctly (i.e., when
1436 * printing expressions containing function calls, it sets LR = 0.)
1437 * Valid exception return codes have bit 0 set too.
1438 */
1439 if (num == ARMV7M_R14)
1440 value |= 0x01;
1441 #endif
1442
1443 /* NOTE: we "know" here that the register identifiers used
1444 * in the v7m header match the Cortex-M3 Debug Core Register
1445 * Selector values for R0..R15, xPSR, MSP, and PSP.
1446 */
1447 switch (num) {
1448 case 0 ... 18:
1449 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1450 if (retval != ERROR_OK)
1451 {
1452 struct reg *r;
1453
1454 LOG_ERROR("JTAG failure %i", retval);
1455 r = armv7m->core_cache->reg_list + num;
1456 r->dirty = r->valid;
1457 return ERROR_JTAG_DEVICE_ERROR;
1458 }
1459 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1460 break;
1461
1462 case ARMV7M_PRIMASK:
1463 case ARMV7M_BASEPRI:
1464 case ARMV7M_FAULTMASK:
1465 case ARMV7M_CONTROL:
1466 /* Cortex-M3 packages these four registers as bitfields
1467 * in one Debug Core register. So say r0 and r2 docs;
1468 * it was removed from r1 docs, but still works.
1469 */
1470 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1471
1472 switch (num)
1473 {
1474 case ARMV7M_PRIMASK:
1475 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1476 break;
1477
1478 case ARMV7M_BASEPRI:
1479 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1480 break;
1481
1482 case ARMV7M_FAULTMASK:
1483 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1484 break;
1485
1486 case ARMV7M_CONTROL:
1487 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1488 break;
1489 }
1490
1491 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1492
1493 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1494 break;
1495
1496 default:
1497 return ERROR_INVALID_ARGUMENTS;
1498 }
1499
1500 return ERROR_OK;
1501 }
1502
1503 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1504 uint32_t size, uint32_t count, uint8_t *buffer)
1505 {
1506 struct armv7m_common *armv7m = target_to_armv7m(target);
1507 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1508 int retval = ERROR_INVALID_ARGUMENTS;
1509
1510 /* cortex_m3 handles unaligned memory access */
1511 if (count && buffer) {
1512 switch (size) {
1513 case 4:
1514 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1515 break;
1516 case 2:
1517 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1518 break;
1519 case 1:
1520 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1521 break;
1522 }
1523 }
1524
1525 return retval;
1526 }
1527
1528 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1529 uint32_t size, uint32_t count, uint8_t *buffer)
1530 {
1531 struct armv7m_common *armv7m = target_to_armv7m(target);
1532 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1533 int retval = ERROR_INVALID_ARGUMENTS;
1534
1535 if (count && buffer) {
1536 switch (size) {
1537 case 4:
1538 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1539 break;
1540 case 2:
1541 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1542 break;
1543 case 1:
1544 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1545 break;
1546 }
1547 }
1548
1549 return retval;
1550 }
1551
1552 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1553 uint32_t count, uint8_t *buffer)
1554 {
1555 return cortex_m3_write_memory(target, address, 4, count, buffer);
1556 }
1557
1558 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1559 struct target *target)
1560 {
1561 armv7m_build_reg_cache(target);
1562 return ERROR_OK;
1563 }
1564
1565 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1566 * on r/w if the core is not running, and clear on resume or reset ... or
1567 * at least, in a post_restore_context() method.
1568 */
1569
1570 struct dwt_reg_state {
1571 struct target *target;
1572 uint32_t addr;
1573 uint32_t value; /* scratch/cache */
1574 };
1575
1576 static int cortex_m3_dwt_get_reg(struct reg *reg)
1577 {
1578 struct dwt_reg_state *state = reg->arch_info;
1579
1580 return target_read_u32(state->target, state->addr, &state->value);
1581 }
1582
1583 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1584 {
1585 struct dwt_reg_state *state = reg->arch_info;
1586
1587 return target_write_u32(state->target, state->addr,
1588 buf_get_u32(buf, 0, reg->size));
1589 }
1590
1591 struct dwt_reg {
1592 uint32_t addr;
1593 char *name;
1594 unsigned size;
1595 };
1596
1597 static struct dwt_reg dwt_base_regs[] = {
1598 { DWT_CTRL, "dwt_ctrl", 32, },
1599 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1600 * increments while the core is asleep.
1601 */
1602 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1603 /* plus some 8 bit counters, useful for profiling with TPIU */
1604 };
1605
1606 static struct dwt_reg dwt_comp[] = {
1607 #define DWT_COMPARATOR(i) \
1608 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1609 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1610 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1611 DWT_COMPARATOR(0),
1612 DWT_COMPARATOR(1),
1613 DWT_COMPARATOR(2),
1614 DWT_COMPARATOR(3),
1615 #undef DWT_COMPARATOR
1616 };
1617
1618 static const struct reg_arch_type dwt_reg_type = {
1619 .get = cortex_m3_dwt_get_reg,
1620 .set = cortex_m3_dwt_set_reg,
1621 };
1622
1623 static void
1624 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1625 {
1626 struct dwt_reg_state *state;
1627
1628 state = calloc(1, sizeof *state);
1629 if (!state)
1630 return;
1631 state->addr = d->addr;
1632 state->target = t;
1633
1634 r->name = d->name;
1635 r->size = d->size;
1636 r->value = &state->value;
1637 r->arch_info = state;
1638 r->type = &dwt_reg_type;
1639 }
1640
1641 static void
1642 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1643 {
1644 uint32_t dwtcr;
1645 struct reg_cache *cache;
1646 struct cortex_m3_dwt_comparator *comparator;
1647 int reg, i;
1648
1649 target_read_u32(target, DWT_CTRL, &dwtcr);
1650 if (!dwtcr) {
1651 LOG_DEBUG("no DWT");
1652 return;
1653 }
1654
1655 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1656 cm3->dwt_comp_available = cm3->dwt_num_comp;
1657 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1658 sizeof(struct cortex_m3_dwt_comparator));
1659 if (!cm3->dwt_comparator_list) {
1660 fail0:
1661 cm3->dwt_num_comp = 0;
1662 LOG_ERROR("out of mem");
1663 return;
1664 }
1665
1666 cache = calloc(1, sizeof *cache);
1667 if (!cache) {
1668 fail1:
1669 free(cm3->dwt_comparator_list);
1670 goto fail0;
1671 }
1672 cache->name = "cortex-m3 dwt registers";
1673 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1674 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1675 if (!cache->reg_list) {
1676 free(cache);
1677 goto fail1;
1678 }
1679
1680 for (reg = 0; reg < 2; reg++)
1681 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1682 dwt_base_regs + reg);
1683
1684 comparator = cm3->dwt_comparator_list;
1685 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1686 int j;
1687
1688 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1689 for (j = 0; j < 3; j++, reg++)
1690 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1691 dwt_comp + 3 * i + j);
1692 }
1693
1694 *register_get_last_cache_p(&target->reg_cache) = cache;
1695 cm3->dwt_cache = cache;
1696
1697 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1698 dwtcr, cm3->dwt_num_comp,
1699 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1700
1701 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1702 * implement single-address data value watchpoints ... so we
1703 * won't need to check it later, when asked to set one up.
1704 */
1705 }
1706
1707 static int cortex_m3_examine(struct target *target)
1708 {
1709 int retval;
1710 uint32_t cpuid, fpcr;
1711 int i;
1712 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1713 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1714
1715 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1716 return retval;
1717
1718 if (!target_was_examined(target))
1719 {
1720 target_set_examined(target);
1721
1722 /* Read from Device Identification Registers */
1723 retval = target_read_u32(target, CPUID, &cpuid);
1724 if (retval != ERROR_OK)
1725 return retval;
1726
1727 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1728 LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1729 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1730 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1731
1732 /* NOTE: FPB and DWT are both optional. */
1733
1734 /* Setup FPB */
1735 target_read_u32(target, FP_CTRL, &fpcr);
1736 cortex_m3->auto_bp_type = 1;
1737 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1738 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1739 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1740 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1741 cortex_m3->fpb_enabled = fpcr & 1;
1742 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1743 {
1744 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1745 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1746 }
1747 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1748
1749 /* Setup DWT */
1750 cortex_m3_dwt_setup(cortex_m3, target);
1751
1752 /* These hardware breakpoints only work for code in flash! */
1753 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1754 target_name(target),
1755 cortex_m3->fp_num_code,
1756 cortex_m3->dwt_num_comp);
1757 }
1758
1759 return ERROR_OK;
1760 }
1761
1762 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1763 {
1764 uint16_t dcrdr;
1765
1766 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1767 *ctrl = (uint8_t)dcrdr;
1768 *value = (uint8_t)(dcrdr >> 8);
1769
1770 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1771
1772 /* write ack back to software dcc register
1773 * signify we have read data */
1774 if (dcrdr & (1 << 0))
1775 {
1776 dcrdr = 0;
1777 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1778 }
1779
1780 return ERROR_OK;
1781 }
1782
1783 static int cortex_m3_target_request_data(struct target *target,
1784 uint32_t size, uint8_t *buffer)
1785 {
1786 struct armv7m_common *armv7m = target_to_armv7m(target);
1787 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1788 uint8_t data;
1789 uint8_t ctrl;
1790 uint32_t i;
1791
1792 for (i = 0; i < (size * 4); i++)
1793 {
1794 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1795 buffer[i] = data;
1796 }
1797
1798 return ERROR_OK;
1799 }
1800
1801 static int cortex_m3_handle_target_request(void *priv)
1802 {
1803 struct target *target = priv;
1804 if (!target_was_examined(target))
1805 return ERROR_OK;
1806 struct armv7m_common *armv7m = target_to_armv7m(target);
1807 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1808
1809 if (!target->dbg_msg_enabled)
1810 return ERROR_OK;
1811
1812 if (target->state == TARGET_RUNNING)
1813 {
1814 uint8_t data;
1815 uint8_t ctrl;
1816
1817 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1818
1819 /* check if we have data */
1820 if (ctrl & (1 << 0))
1821 {
1822 uint32_t request;
1823
1824 /* we assume target is quick enough */
1825 request = data;
1826 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1827 request |= (data << 8);
1828 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1829 request |= (data << 16);
1830 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1831 request |= (data << 24);
1832 target_request(target, request);
1833 }
1834 }
1835
1836 return ERROR_OK;
1837 }
1838
1839 static int cortex_m3_init_arch_info(struct target *target,
1840 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1841 {
1842 int retval;
1843 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1844
1845 armv7m_init_arch_info(target, armv7m);
1846
1847 /* prepare JTAG information for the new target */
1848 cortex_m3->jtag_info.tap = tap;
1849 cortex_m3->jtag_info.scann_size = 4;
1850
1851 armv7m->swjdp_info.dp_select_value = -1;
1852 armv7m->swjdp_info.ap_csw_value = -1;
1853 armv7m->swjdp_info.ap_tar_value = -1;
1854 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1855 armv7m->swjdp_info.memaccess_tck = 8;
1856 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1857
1858 /* register arch-specific functions */
1859 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1860
1861 armv7m->post_debug_entry = NULL;
1862
1863 armv7m->pre_restore_context = NULL;
1864 armv7m->post_restore_context = NULL;
1865
1866 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1867 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1868
1869 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1870
1871 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1872 {
1873 return retval;
1874 }
1875
1876 return ERROR_OK;
1877 }
1878
1879 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1880 {
1881 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1882
1883 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1884 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1885
1886 return ERROR_OK;
1887 }
1888
1889 /*--------------------------------------------------------------------------*/
1890
1891 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1892 struct cortex_m3_common *cm3)
1893 {
1894 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1895 command_print(cmd_ctx, "target is not a Cortex-M3");
1896 return ERROR_TARGET_INVALID;
1897 }
1898 return ERROR_OK;
1899 }
1900
1901 /*
1902 * Only stuff below this line should need to verify that its target
1903 * is a Cortex-M3. Everything else should have indirected through the
1904 * cortexm3_target structure, which is only used with CM3 targets.
1905 */
1906
1907 /*
1908 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1909 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1910 * that *only* Thumb2 disassembly matters. There are also some small
1911 * additions to Thumb2 that are specific to ARMv7-M.
1912 */
1913 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1914 {
1915 int retval;
1916 struct target *target = get_current_target(CMD_CTX);
1917 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1918 uint32_t address;
1919 unsigned long count = 1;
1920 struct arm_instruction cur_instruction;
1921
1922 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1923 if (retval != ERROR_OK)
1924 return retval;
1925
1926 errno = 0;
1927 switch (CMD_ARGC) {
1928 case 2:
1929 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1930 /* FALL THROUGH */
1931 case 1:
1932 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1933 break;
1934 default:
1935 command_print(CMD_CTX,
1936 "usage: cortex_m3 disassemble <address> [<count>]");
1937 return ERROR_OK;
1938 }
1939
1940 while (count--) {
1941 retval = thumb2_opcode(target, address, &cur_instruction);
1942 if (retval != ERROR_OK)
1943 return retval;
1944 command_print(CMD_CTX, "%s", cur_instruction.text);
1945 address += cur_instruction.instruction_size;
1946 }
1947
1948 return ERROR_OK;
1949 }
1950
1951 static const struct {
1952 char name[10];
1953 unsigned mask;
1954 } vec_ids[] = {
1955 { "hard_err", VC_HARDERR, },
1956 { "int_err", VC_INTERR, },
1957 { "bus_err", VC_BUSERR, },
1958 { "state_err", VC_STATERR, },
1959 { "chk_err", VC_CHKERR, },
1960 { "nocp_err", VC_NOCPERR, },
1961 { "mm_err", VC_MMERR, },
1962 { "reset", VC_CORERESET, },
1963 };
1964
1965 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1966 {
1967 struct target *target = get_current_target(CMD_CTX);
1968 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1969 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1970 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1971 uint32_t demcr = 0;
1972 int retval;
1973
1974 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1975 if (retval != ERROR_OK)
1976 return retval;
1977
1978 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1979
1980 if (CMD_ARGC > 0) {
1981 unsigned catch = 0;
1982
1983 if (CMD_ARGC == 1) {
1984 if (strcmp(CMD_ARGV[0], "all") == 0) {
1985 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1986 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1987 | VC_MMERR | VC_CORERESET;
1988 goto write;
1989 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1990 goto write;
1991 }
1992 }
1993 while (CMD_ARGC-- > 0) {
1994 unsigned i;
1995 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1996 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1997 continue;
1998 catch |= vec_ids[i].mask;
1999 break;
2000 }
2001 if (i == ARRAY_SIZE(vec_ids)) {
2002 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2003 return ERROR_INVALID_ARGUMENTS;
2004 }
2005 }
2006 write:
2007 /* For now, armv7m->demcr only stores vector catch flags. */
2008 armv7m->demcr = catch;
2009
2010 demcr &= ~0xffff;
2011 demcr |= catch;
2012
2013 /* write, but don't assume it stuck (why not??) */
2014 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2015 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2016
2017 /* FIXME be sure to clear DEMCR on clean server shutdown.
2018 * Otherwise the vector catch hardware could fire when there's
2019 * no debugger hooked up, causing much confusion...
2020 */
2021 }
2022
2023 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2024 {
2025 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2026 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2027 }
2028
2029 return ERROR_OK;
2030 }
2031
2032 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2033 {
2034 struct target *target = get_current_target(CMD_CTX);
2035 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2036 int retval;
2037
2038 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2039 if (retval != ERROR_OK)
2040 return retval;
2041
2042 if (target->state != TARGET_HALTED)
2043 {
2044 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2045 return ERROR_OK;
2046 }
2047
2048 if (CMD_ARGC > 0)
2049 {
2050 bool enable;
2051 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2052 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2053 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2054 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2055 }
2056
2057 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2058 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2059
2060 return ERROR_OK;
2061 }
2062
2063 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2064 {
2065 .name = "disassemble",
2066 .handler = handle_cortex_m3_disassemble_command,
2067 .mode = COMMAND_EXEC,
2068 .help = "disassemble Thumb2 instructions",
2069 .usage = "address [count]",
2070 },
2071 {
2072 .name = "maskisr",
2073 .handler = handle_cortex_m3_mask_interrupts_command,
2074 .mode = COMMAND_EXEC,
2075 .help = "mask cortex_m3 interrupts",
2076 .usage = "['on'|'off']",
2077 },
2078 {
2079 .name = "vector_catch",
2080 .handler = handle_cortex_m3_vector_catch_command,
2081 .mode = COMMAND_EXEC,
2082 .help = "configure hardware vectors to trigger debug entry",
2083 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2084 },
2085 COMMAND_REGISTRATION_DONE
2086 };
2087 static const struct command_registration cortex_m3_command_handlers[] = {
2088 {
2089 .chain = armv7m_command_handlers,
2090 },
2091 {
2092 .name = "cortex_m3",
2093 .mode = COMMAND_EXEC,
2094 .help = "Cortex-M3 command group",
2095 .chain = cortex_m3_exec_command_handlers,
2096 },
2097 COMMAND_REGISTRATION_DONE
2098 };
2099
2100 struct target_type cortexm3_target =
2101 {
2102 .name = "cortex_m3",
2103
2104 .poll = cortex_m3_poll,
2105 .arch_state = armv7m_arch_state,
2106
2107 .target_request_data = cortex_m3_target_request_data,
2108
2109 .halt = cortex_m3_halt,
2110 .resume = cortex_m3_resume,
2111 .step = cortex_m3_step,
2112
2113 .assert_reset = cortex_m3_assert_reset,
2114 .deassert_reset = cortex_m3_deassert_reset,
2115 .soft_reset_halt = cortex_m3_soft_reset_halt,
2116
2117 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2118
2119 .read_memory = cortex_m3_read_memory,
2120 .write_memory = cortex_m3_write_memory,
2121 .bulk_write_memory = cortex_m3_bulk_write_memory,
2122 .checksum_memory = armv7m_checksum_memory,
2123 .blank_check_memory = armv7m_blank_check_memory,
2124
2125 .run_algorithm = armv7m_run_algorithm,
2126
2127 .add_breakpoint = cortex_m3_add_breakpoint,
2128 .remove_breakpoint = cortex_m3_remove_breakpoint,
2129 .add_watchpoint = cortex_m3_add_watchpoint,
2130 .remove_watchpoint = cortex_m3_remove_watchpoint,
2131
2132 .commands = cortex_m3_command_handlers,
2133 .target_create = cortex_m3_target_create,
2134 .init_target = cortex_m3_init_target,
2135 .examine = cortex_m3_examine,
2136 };
Luca's development patches