?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: keep a handle to the PC
[openocd/ellerodev.git] / src / target / arm7_9_common.c
blob2176729182b98d98f5e76de0fac331873b265a1e
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007-2009 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * Copyright (C) 2009 by David Brownell *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
30 ***************************************************************************/
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "breakpoints.h"
36 #include "embeddedice.h"
37 #include "target_request.h"
38 #include "etm.h"
39 #include <helper/time_support.h>
40 #include "arm_simulator.h"
41 #include "arm_semihosting.h"
42 #include "algorithm.h"
43 #include "register.h"
44 #include "armv4_5.h"
45
46
47 /**
48 * @file
49 * Hold common code supporting the ARM7 and ARM9 core generations.
50 *
51 * While the ARM core implementations evolved substantially during these
52 * two generations, they look quite similar from the JTAG perspective.
53 * Both have similar debug facilities, based on the same two scan chains
54 * providing access to the core and to an EmbeddedICE module. Both can
55 * support similar ETM and ETB modules, for tracing. And both expose
56 * what could be viewed as "ARM Classic", with multiple processor modes,
57 * shadowed registers, and support for the Thumb instruction set.
58 *
59 * Processor differences include things like presence or absence of MMU
60 * and cache, pipeline sizes, use of a modified Harvard Architecure
61 * (with separate instruction and data busses from the CPU), support
62 * for cpu clock gating during idle, and more.
63 */
64
65 static int arm7_9_debug_entry(struct target *target);
66
67 /**
68 * Clear watchpoints for an ARM7/9 target.
69 *
70 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
71 * @return JTAG error status after executing queue
72 */
73 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
74 {
75 LOG_DEBUG("-");
76 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
77 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
78 arm7_9->sw_breakpoint_count = 0;
79 arm7_9->sw_breakpoints_added = 0;
80 arm7_9->wp0_used = 0;
81 arm7_9->wp1_used = arm7_9->wp1_used_default;
82 arm7_9->wp_available = arm7_9->wp_available_max;
83
84 return jtag_execute_queue();
85 }
86
87 /**
88 * Assign a watchpoint to one of the two available hardware comparators in an
89 * ARM7 or ARM9 target.
90 *
91 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
92 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
93 */
94 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
95 {
96 if (!arm7_9->wp0_used)
97 {
98 arm7_9->wp0_used = 1;
99 breakpoint->set = 1;
100 arm7_9->wp_available--;
101 }
102 else if (!arm7_9->wp1_used)
103 {
104 arm7_9->wp1_used = 1;
105 breakpoint->set = 2;
106 arm7_9->wp_available--;
107 }
108 else
109 {
110 LOG_ERROR("BUG: no hardware comparator available");
111 }
112 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
113 breakpoint->unique_id,
114 breakpoint->address,
115 breakpoint->set );
116 }
117
118 /**
119 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
120 *
121 * @param arm7_9 Pointer to common struct for ARM7/9 targets
122 * @return Error codes if there is a problem finding a watchpoint or the result
123 * of executing the JTAG queue
124 */
125 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
126 {
127 if (arm7_9->sw_breakpoints_added)
128 {
129 return ERROR_OK;
130 }
131 if (arm7_9->wp_available < 1)
132 {
133 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
135 }
136 arm7_9->wp_available--;
137
138 /* pick a breakpoint unit */
139 if (!arm7_9->wp0_used)
140 {
141 arm7_9->sw_breakpoints_added = 1;
142 arm7_9->wp0_used = 3;
143 } else if (!arm7_9->wp1_used)
144 {
145 arm7_9->sw_breakpoints_added = 2;
146 arm7_9->wp1_used = 3;
147 }
148 else
149 {
150 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
151 return ERROR_FAIL;
152 }
153
154 if (arm7_9->sw_breakpoints_added == 1)
155 {
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 }
162 else if (arm7_9->sw_breakpoints_added == 2)
163 {
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
165 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
166 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
169 }
170 else
171 {
172 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
173 return ERROR_FAIL;
174 }
175 LOG_DEBUG("SW BP using hw wp: %d",
176 arm7_9->sw_breakpoints_added );
177
178 return jtag_execute_queue();
179 }
180
181 /**
182 * Setup the common pieces for an ARM7/9 target after reset or on startup.
183 *
184 * @param target Pointer to an ARM7/9 target to setup
185 * @return Result of clearing the watchpoints on the target
186 */
187 int arm7_9_setup(struct target *target)
188 {
189 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
190
191 return arm7_9_clear_watchpoints(arm7_9);
192 }
193
194 /**
195 * Set either a hardware or software breakpoint on an ARM7/9 target. The
196 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
197 * might have erased the values in Embedded ICE.
198 *
199 * @param target Pointer to the target device to set the breakpoints on
200 * @param breakpoint Pointer to the breakpoint to be set
201 * @return For hardware breakpoints, this is the result of executing the JTAG
202 * queue. For software breakpoints, this will be the status of the
203 * required memory reads and writes
204 */
205 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
206 {
207 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
208 int retval = ERROR_OK;
209
210 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
211 breakpoint->unique_id,
212 breakpoint->address,
213 breakpoint->type);
214
215 if (target->state != TARGET_HALTED)
216 {
217 LOG_WARNING("target not halted");
218 return ERROR_TARGET_NOT_HALTED;
219 }
220
221 if (breakpoint->type == BKPT_HARD)
222 {
223 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
224 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
225
226 /* reassign a hw breakpoint */
227 if (breakpoint->set == 0)
228 {
229 arm7_9_assign_wp(arm7_9, breakpoint);
230 }
231
232 if (breakpoint->set == 1)
233 {
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
236 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
237 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
239 }
240 else if (breakpoint->set == 2)
241 {
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
243 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
244 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
246 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
247 }
248 else
249 {
250 LOG_ERROR("BUG: no hardware comparator available");
251 return ERROR_OK;
252 }
253
254 retval = jtag_execute_queue();
255 }
256 else if (breakpoint->type == BKPT_SOFT)
257 {
258 /* did we already set this breakpoint? */
259 if (breakpoint->set)
260 return ERROR_OK;
261
262 if (breakpoint->length == 4)
263 {
264 uint32_t verify = 0xffffffff;
265 /* keep the original instruction in target endianness */
266 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
267 {
268 return retval;
269 }
270 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
271 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
272 {
273 return retval;
274 }
275
276 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
277 {
278 return retval;
279 }
280 if (verify != arm7_9->arm_bkpt)
281 {
282 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
283 return ERROR_OK;
284 }
285 }
286 else
287 {
288 uint16_t verify = 0xffff;
289 /* keep the original instruction in target endianness */
290 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
291 {
292 return retval;
293 }
294 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
295 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
296 {
297 return retval;
298 }
299
300 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
301 {
302 return retval;
303 }
304 if (verify != arm7_9->thumb_bkpt)
305 {
306 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
307 return ERROR_OK;
308 }
309 }
310
311 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
312 return retval;
313
314 arm7_9->sw_breakpoint_count++;
315
316 breakpoint->set = 1;
317 }
318
319 return retval;
320 }
321
322 /**
323 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
324 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
325 * will be updated. Otherwise, the software breakpoint will be restored to its
326 * original instruction if it hasn't already been modified.
327 *
328 * @param target Pointer to ARM7/9 target to unset the breakpoint from
329 * @param breakpoint Pointer to breakpoint to be unset
330 * @return For hardware breakpoints, this is the result of executing the JTAG
331 * queue. For software breakpoints, this will be the status of the
332 * required memory reads and writes
333 */
334 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
335 {
336 int retval = ERROR_OK;
337 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
338
339 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
340 breakpoint->unique_id,
341 breakpoint->address );
342
343 if (!breakpoint->set)
344 {
345 LOG_WARNING("breakpoint not set");
346 return ERROR_OK;
347 }
348
349 if (breakpoint->type == BKPT_HARD)
350 {
351 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
352 breakpoint->unique_id,
353 breakpoint->set );
354 if (breakpoint->set == 1)
355 {
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
357 arm7_9->wp0_used = 0;
358 arm7_9->wp_available++;
359 }
360 else if (breakpoint->set == 2)
361 {
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
363 arm7_9->wp1_used = 0;
364 arm7_9->wp_available++;
365 }
366 retval = jtag_execute_queue();
367 breakpoint->set = 0;
368 }
369 else
370 {
371 /* restore original instruction (kept in target endianness) */
372 if (breakpoint->length == 4)
373 {
374 uint32_t current_instr;
375 /* check that user program as not modified breakpoint instruction */
376 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
377 {
378 return retval;
379 }
380 if (current_instr == arm7_9->arm_bkpt)
381 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
382 {
383 return retval;
384 }
385 }
386 else
387 {
388 uint16_t current_instr;
389 /* check that user program as not modified breakpoint instruction */
390 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
391 {
392 return retval;
393 }
394 if (current_instr == arm7_9->thumb_bkpt)
395 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
396 {
397 return retval;
398 }
399 }
400
401 if (--arm7_9->sw_breakpoint_count==0)
402 {
403 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
404 if (arm7_9->sw_breakpoints_added == 1)
405 {
406 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
407 }
408 else if (arm7_9->sw_breakpoints_added == 2)
409 {
410 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
411 }
412 }
413
414 breakpoint->set = 0;
415 }
416
417 return retval;
418 }
419
420 /**
421 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
422 * dangling breakpoints and that the desired breakpoint can be added.
423 *
424 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
425 * @param breakpoint Pointer to the breakpoint to be added
426 * @return An error status if there is a problem adding the breakpoint or the
427 * result of setting the breakpoint
428 */
429 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
430 {
431 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
432
433 if (arm7_9->breakpoint_count == 0)
434 {
435 /* make sure we don't have any dangling breakpoints. This is vital upon
436 * GDB connect/disconnect
437 */
438 arm7_9_clear_watchpoints(arm7_9);
439 }
440
441 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
442 {
443 LOG_INFO("no watchpoint unit available for hardware breakpoint");
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
445 }
446
447 if ((breakpoint->length != 2) && (breakpoint->length != 4))
448 {
449 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
450 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
451 }
452
453 if (breakpoint->type == BKPT_HARD)
454 {
455 arm7_9_assign_wp(arm7_9, breakpoint);
456 }
457
458 arm7_9->breakpoint_count++;
459
460 return arm7_9_set_breakpoint(target, breakpoint);
461 }
462
463 /**
464 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
465 * dangling breakpoints and updates available watchpoints if it is a hardware
466 * breakpoint.
467 *
468 * @param target Pointer to the target to have a breakpoint removed
469 * @param breakpoint Pointer to the breakpoint to be removed
470 * @return Error status if there was a problem unsetting the breakpoint or the
471 * watchpoints could not be cleared
472 */
473 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
474 {
475 int retval = ERROR_OK;
476 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
477
478 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
479 {
480 return retval;
481 }
482
483 if (breakpoint->type == BKPT_HARD)
484 arm7_9->wp_available++;
485
486 arm7_9->breakpoint_count--;
487 if (arm7_9->breakpoint_count == 0)
488 {
489 /* make sure we don't have any dangling breakpoints */
490 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
491 {
492 return retval;
493 }
494 }
495
496 return ERROR_OK;
497 }
498
499 /**
500 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
501 * considered a bug to call this function when there are no available watchpoint
502 * units.
503 *
504 * @param target Pointer to an ARM7/9 target to set a watchpoint on
505 * @param watchpoint Pointer to the watchpoint to be set
506 * @return Error status if watchpoint set fails or the result of executing the
507 * JTAG queue
508 */
509 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
510 {
511 int retval = ERROR_OK;
512 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
513 int rw_mask = 1;
514 uint32_t mask;
515
516 mask = watchpoint->length - 1;
517
518 if (target->state != TARGET_HALTED)
519 {
520 LOG_WARNING("target not halted");
521 return ERROR_TARGET_NOT_HALTED;
522 }
523
524 if (watchpoint->rw == WPT_ACCESS)
525 rw_mask = 0;
526 else
527 rw_mask = 1;
528
529 if (!arm7_9->wp0_used)
530 {
531 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
532 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
534 if (watchpoint->mask != 0xffffffffu)
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
536 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
538
539 if ((retval = jtag_execute_queue()) != ERROR_OK)
540 {
541 return retval;
542 }
543 watchpoint->set = 1;
544 arm7_9->wp0_used = 2;
545 }
546 else if (!arm7_9->wp1_used)
547 {
548 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
549 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
551 if (watchpoint->mask != 0xffffffffu)
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
553 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
555
556 if ((retval = jtag_execute_queue()) != ERROR_OK)
557 {
558 return retval;
559 }
560 watchpoint->set = 2;
561 arm7_9->wp1_used = 2;
562 }
563 else
564 {
565 LOG_ERROR("BUG: no hardware comparator available");
566 return ERROR_OK;
567 }
568
569 return ERROR_OK;
570 }
571
572 /**
573 * Unset an existing watchpoint and clear the used watchpoint unit.
574 *
575 * @param target Pointer to the target to have the watchpoint removed
576 * @param watchpoint Pointer to the watchpoint to be removed
577 * @return Error status while trying to unset the watchpoint or the result of
578 * executing the JTAG queue
579 */
580 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
581 {
582 int retval = ERROR_OK;
583 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
584
585 if (target->state != TARGET_HALTED)
586 {
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED;
589 }
590
591 if (!watchpoint->set)
592 {
593 LOG_WARNING("breakpoint not set");
594 return ERROR_OK;
595 }
596
597 if (watchpoint->set == 1)
598 {
599 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
600 if ((retval = jtag_execute_queue()) != ERROR_OK)
601 {
602 return retval;
603 }
604 arm7_9->wp0_used = 0;
605 }
606 else if (watchpoint->set == 2)
607 {
608 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
609 if ((retval = jtag_execute_queue()) != ERROR_OK)
610 {
611 return retval;
612 }
613 arm7_9->wp1_used = 0;
614 }
615 watchpoint->set = 0;
616
617 return ERROR_OK;
618 }
619
620 /**
621 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
622 * available, an error response is returned.
623 *
624 * @param target Pointer to the ARM7/9 target to add a watchpoint to
625 * @param watchpoint Pointer to the watchpoint to be added
626 * @return Error status while trying to add the watchpoint
627 */
628 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
629 {
630 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
631
632 if (arm7_9->wp_available < 1)
633 {
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
635 }
636
637 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
638 {
639 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
640 }
641
642 arm7_9->wp_available--;
643
644 return ERROR_OK;
645 }
646
647 /**
648 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
649 * the used watchpoint unit will be reopened.
650 *
651 * @param target Pointer to the target to remove a watchpoint from
652 * @param watchpoint Pointer to the watchpoint to be removed
653 * @return Result of trying to unset the watchpoint
654 */
655 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
656 {
657 int retval = ERROR_OK;
658 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
659
660 if (watchpoint->set)
661 {
662 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
663 {
664 return retval;
665 }
666 }
667
668 arm7_9->wp_available++;
669
670 return ERROR_OK;
671 }
672
673 /**
674 * Restarts the target by sending a RESTART instruction and moving the JTAG
675 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
676 * asserted by the processor.
677 *
678 * @param target Pointer to target to issue commands to
679 * @return Error status if there is a timeout or a problem while executing the
680 * JTAG queue
681 */
682 int arm7_9_execute_sys_speed(struct target *target)
683 {
684 int retval;
685 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
686 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
687 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
688
689 /* set RESTART instruction */
690 jtag_set_end_state(TAP_IDLE);
691 if (arm7_9->need_bypass_before_restart) {
692 arm7_9->need_bypass_before_restart = 0;
693 arm_jtag_set_instr(jtag_info, 0xf, NULL);
694 }
695 arm_jtag_set_instr(jtag_info, 0x4, NULL);
696
697 long long then = timeval_ms();
698 int timeout;
699 while (!(timeout = ((timeval_ms()-then) > 1000)))
700 {
701 /* read debug status register */
702 embeddedice_read_reg(dbg_stat);
703 if ((retval = jtag_execute_queue()) != ERROR_OK)
704 return retval;
705 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
706 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
707 break;
708 if (debug_level >= 3)
709 {
710 alive_sleep(100);
711 } else
712 {
713 keep_alive();
714 }
715 }
716 if (timeout)
717 {
718 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
719 return ERROR_TARGET_TIMEOUT;
720 }
721
722 return ERROR_OK;
723 }
724
725 /**
726 * Restarts the target by sending a RESTART instruction and moving the JTAG
727 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
728 * waiting until they are.
729 *
730 * @param target Pointer to the target to issue commands to
731 * @return Always ERROR_OK
732 */
733 int arm7_9_execute_fast_sys_speed(struct target *target)
734 {
735 static int set = 0;
736 static uint8_t check_value[4], check_mask[4];
737
738 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
739 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
740 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
741
742 /* set RESTART instruction */
743 jtag_set_end_state(TAP_IDLE);
744 if (arm7_9->need_bypass_before_restart) {
745 arm7_9->need_bypass_before_restart = 0;
746 arm_jtag_set_instr(jtag_info, 0xf, NULL);
747 }
748 arm_jtag_set_instr(jtag_info, 0x4, NULL);
749
750 if (!set)
751 {
752 /* check for DBGACK and SYSCOMP set (others don't care) */
753
754 /* NB! These are constants that must be available until after next jtag_execute() and
755 * we evaluate the values upon first execution in lieu of setting up these constants
756 * during early setup.
757 * */
758 buf_set_u32(check_value, 0, 32, 0x9);
759 buf_set_u32(check_mask, 0, 32, 0x9);
760 set = 1;
761 }
762
763 /* read debug status register */
764 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
765
766 return ERROR_OK;
767 }
768
769 /**
770 * Get some data from the ARM7/9 target.
771 *
772 * @param target Pointer to the ARM7/9 target to read data from
773 * @param size The number of 32bit words to be read
774 * @param buffer Pointer to the buffer that will hold the data
775 * @return The result of receiving data from the Embedded ICE unit
776 */
777 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
778 {
779 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
780 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
781 uint32_t *data;
782 int retval = ERROR_OK;
783 uint32_t i;
784
785 data = malloc(size * (sizeof(uint32_t)));
786
787 retval = embeddedice_receive(jtag_info, data, size);
788
789 /* return the 32-bit ints in the 8-bit array */
790 for (i = 0; i < size; i++)
791 {
792 h_u32_to_le(buffer + (i * 4), data[i]);
793 }
794
795 free(data);
796
797 return retval;
798 }
799
800 /**
801 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
802 * target is running and the DCC control register has the W bit high, this will
803 * execute the request on the target.
804 *
805 * @param priv Void pointer expected to be a struct target pointer
806 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
807 * from the Embedded ICE unit
808 */
809 int arm7_9_handle_target_request(void *priv)
810 {
811 int retval = ERROR_OK;
812 struct target *target = priv;
813 if (!target_was_examined(target))
814 return ERROR_OK;
815 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
816 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
817 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
818
819 if (!target->dbg_msg_enabled)
820 return ERROR_OK;
821
822 if (target->state == TARGET_RUNNING)
823 {
824 /* read DCC control register */
825 embeddedice_read_reg(dcc_control);
826 if ((retval = jtag_execute_queue()) != ERROR_OK)
827 {
828 return retval;
829 }
830
831 /* check W bit */
832 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
833 {
834 uint32_t request;
835
836 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
837 {
838 return retval;
839 }
840 if ((retval = target_request(target, request)) != ERROR_OK)
841 {
842 return retval;
843 }
844 }
845 }
846
847 return ERROR_OK;
848 }
849
850 /**
851 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
852 * is manipulated to the right halted state based on its current state. This is
853 * what happens:
854 *
855 * <table>
856 * <tr><th > State</th><th > Action</th></tr>
857 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
858 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
859 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
860 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
861 * </table>
862 *
863 * If the target does not end up in the halted state, a warning is produced. If
864 * DBGACK is cleared, then the target is expected to either be running or
865 * running in debug.
866 *
867 * @param target Pointer to the ARM7/9 target to poll
868 * @return ERROR_OK or an error status if a command fails
869 */
870 int arm7_9_poll(struct target *target)
871 {
872 int retval;
873 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
874 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
875
876 /* read debug status register */
877 embeddedice_read_reg(dbg_stat);
878 if ((retval = jtag_execute_queue()) != ERROR_OK)
879 {
880 return retval;
881 }
882
883 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
884 {
885 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
886 if (target->state == TARGET_UNKNOWN)
887 {
888 /* Starting OpenOCD with target in debug-halt */
889 target->state = TARGET_RUNNING;
890 LOG_DEBUG("DBGACK already set during server startup.");
891 }
892 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
893 {
894 target->state = TARGET_HALTED;
895
896 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
897 return retval;
898
899 if (arm_semihosting(target, &retval) != 0)
900 return retval;
901
902 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
903 {
904 return retval;
905 }
906 }
907 if (target->state == TARGET_DEBUG_RUNNING)
908 {
909 target->state = TARGET_HALTED;
910 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
911 return retval;
912
913 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
914 {
915 return retval;
916 }
917 }
918 if (target->state != TARGET_HALTED)
919 {
920 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
921 }
922 }
923 else
924 {
925 if (target->state != TARGET_DEBUG_RUNNING)
926 target->state = TARGET_RUNNING;
927 }
928
929 return ERROR_OK;
930 }
931
932 /**
933 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
934 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
935 * affected) completely stop the JTAG clock while the core is held in reset
936 * (SRST). It isn't possible to program the halt condition once reset is
937 * asserted, hence a hook that allows the target to set up its reset-halt
938 * condition is setup prior to asserting reset.
939 *
940 * @param target Pointer to an ARM7/9 target to assert reset on
941 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
942 */
943 int arm7_9_assert_reset(struct target *target)
944 {
945 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
946 enum reset_types jtag_reset_config = jtag_get_reset_config();
947 bool use_event = false;
948
949 LOG_DEBUG("target->state: %s",
950 target_state_name(target));
951
952 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
953 use_event = true;
954 else if (!(jtag_reset_config & RESET_HAS_SRST)) {
955 LOG_ERROR("%s: how to reset?", target_name(target));
956 return ERROR_FAIL;
957 }
958
959 /* At this point trst has been asserted/deasserted once. We would
960 * like to program EmbeddedICE while SRST is asserted, instead of
961 * depending on SRST to leave that module alone. However, many CPUs
962 * gate the JTAG clock while SRST is asserted; or JTAG may need
963 * clock stability guarantees (adaptive clocking might help).
964 *
965 * So we assume JTAG access during SRST is off the menu unless it's
966 * been specifically enabled.
967 */
968 bool srst_asserted = false;
969
970 if (!use_event
971 && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
972 && (jtag_reset_config & RESET_SRST_NO_GATING))
973 {
974 jtag_add_reset(0, 1);
975 srst_asserted = true;
976 }
977
978 if (target->reset_halt)
979 {
980 /*
981 * For targets that don't support communication while SRST is
982 * asserted, we need to set up the reset vector catch first.
983 *
984 * When we use TRST+SRST and that's equivalent to a power-up
985 * reset, these settings may well be reset anyway; so setting
986 * them here won't matter.
987 */
988 if (arm7_9->has_vector_catch)
989 {
990 /* program vector catch register to catch reset */
991 embeddedice_write_reg(&arm7_9->eice_cache
992 ->reg_list[EICE_VEC_CATCH], 0x1);
993
994 /* extra runtest added as issues were found with
995 * certain ARM9 cores (maybe more) - AT91SAM9260
996 * and STR9
997 */
998 jtag_add_runtest(1, jtag_get_end_state());
999 }
1000 else
1001 {
1002 /* program watchpoint unit to match on reset vector
1003 * address
1004 */
1005 embeddedice_write_reg(&arm7_9->eice_cache
1006 ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1007 embeddedice_write_reg(&arm7_9->eice_cache
1008 ->reg_list[EICE_W0_ADDR_MASK], 0x3);
1009 embeddedice_write_reg(&arm7_9->eice_cache
1010 ->reg_list[EICE_W0_DATA_MASK],
1011 0xffffffff);
1012 embeddedice_write_reg(&arm7_9->eice_cache
1013 ->reg_list[EICE_W0_CONTROL_VALUE],
1014 EICE_W_CTRL_ENABLE);
1015 embeddedice_write_reg(&arm7_9->eice_cache
1016 ->reg_list[EICE_W0_CONTROL_MASK],
1017 ~EICE_W_CTRL_nOPC & 0xff);
1018 }
1019 }
1020
1021 if (use_event) {
1022 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1023 } else {
1024 /* If we use SRST ... we'd like to issue just SRST, but the
1025 * board or chip may be set up so we have to assert TRST as
1026 * well. On some chips that combination is equivalent to a
1027 * power-up reset, and generally clobbers EICE state.
1028 */
1029 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1030 jtag_add_reset(1, 1);
1031 else if (!srst_asserted)
1032 jtag_add_reset(0, 1);
1033 jtag_add_sleep(50000);
1034 }
1035
1036 target->state = TARGET_RESET;
1037 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1038
1039 /* REVISIT why isn't standard debug entry logic sufficient?? */
1040 if (target->reset_halt
1041 && (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
1042 || use_event))
1043 {
1044 /* debug entry was prepared above */
1045 target->debug_reason = DBG_REASON_DBGRQ;
1046 }
1047
1048 return ERROR_OK;
1049 }
1050
1051 /**
1052 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1053 * and the target is being reset into a halt, a warning will be triggered
1054 * because it is not possible to reset into a halted mode in this case. The
1055 * target is halted using the target's functions.
1056 *
1057 * @param target Pointer to the target to have the reset deasserted
1058 * @return ERROR_OK or an error from polling or halting the target
1059 */
1060 int arm7_9_deassert_reset(struct target *target)
1061 {
1062 int retval = ERROR_OK;
1063 LOG_DEBUG("target->state: %s",
1064 target_state_name(target));
1065
1066 /* deassert reset lines */
1067 jtag_add_reset(0, 0);
1068
1069 enum reset_types jtag_reset_config = jtag_get_reset_config();
1070 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1071 {
1072 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1073 /* set up embedded ice registers again */
1074 if ((retval = target_examine_one(target)) != ERROR_OK)
1075 return retval;
1076
1077 if ((retval = target_poll(target)) != ERROR_OK)
1078 {
1079 return retval;
1080 }
1081
1082 if ((retval = target_halt(target)) != ERROR_OK)
1083 {
1084 return retval;
1085 }
1086
1087 }
1088 return retval;
1089 }
1090
1091 /**
1092 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1093 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1094 * vector catch was used, it is restored. Otherwise, the control value is
1095 * restored and the watchpoint unit is restored if it was in use.
1096 *
1097 * @param target Pointer to the ARM7/9 target to have halt cleared
1098 * @return Always ERROR_OK
1099 */
1100 int arm7_9_clear_halt(struct target *target)
1101 {
1102 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1103 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1104
1105 /* we used DBGRQ only if we didn't come out of reset */
1106 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1107 {
1108 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1109 */
1110 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1111 embeddedice_store_reg(dbg_ctrl);
1112 }
1113 else
1114 {
1115 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1116 {
1117 /* if we came out of reset, and vector catch is supported, we used
1118 * vector catch to enter debug state
1119 * restore the register in that case
1120 */
1121 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1122 }
1123 else
1124 {
1125 /* restore registers if watchpoint unit 0 was in use
1126 */
1127 if (arm7_9->wp0_used)
1128 {
1129 if (arm7_9->debug_entry_from_reset)
1130 {
1131 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1132 }
1133 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1134 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1135 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1136 }
1137 /* control value always has to be restored, as it was either disabled,
1138 * or enabled with possibly different bits
1139 */
1140 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1141 }
1142 }
1143
1144 return ERROR_OK;
1145 }
1146
1147 /**
1148 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1149 * and then there is a wait until the processor shows the halt. This wait can
1150 * timeout and results in an error being returned. The software reset involves
1151 * clearing the halt, updating the debug control register, changing to ARM mode,
1152 * reset of the program counter, and reset of all of the registers.
1153 *
1154 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1155 * @return Error status if any of the commands fail, otherwise ERROR_OK
1156 */
1157 int arm7_9_soft_reset_halt(struct target *target)
1158 {
1159 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1160 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1161 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1162 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1163 int i;
1164 int retval;
1165
1166 /* FIX!!! replace some of this code with tcl commands
1167 *
1168 * halt # the halt command is synchronous
1169 * armv4_5 core_state arm
1170 *
1171 */
1172
1173 if ((retval = target_halt(target)) != ERROR_OK)
1174 return retval;
1175
1176 long long then = timeval_ms();
1177 int timeout;
1178 while (!(timeout = ((timeval_ms()-then) > 1000)))
1179 {
1180 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1181 break;
1182 embeddedice_read_reg(dbg_stat);
1183 if ((retval = jtag_execute_queue()) != ERROR_OK)
1184 return retval;
1185 if (debug_level >= 3)
1186 {
1187 alive_sleep(100);
1188 } else
1189 {
1190 keep_alive();
1191 }
1192 }
1193 if (timeout)
1194 {
1195 LOG_ERROR("Failed to halt CPU after 1 sec");
1196 return ERROR_TARGET_TIMEOUT;
1197 }
1198 target->state = TARGET_HALTED;
1199
1200 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1201 * ensure that DBGRQ is cleared
1202 */
1203 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1204 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1205 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1206 embeddedice_store_reg(dbg_ctrl);
1207
1208 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1209 {
1210 return retval;
1211 }
1212
1213 /* if the target is in Thumb state, change to ARM state */
1214 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1215 {
1216 uint32_t r0_thumb, pc_thumb;
1217 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1218 /* Entered debug from Thumb mode */
1219 armv4_5->core_state = ARM_STATE_THUMB;
1220 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1221 }
1222
1223 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1224
1225 /* all register content is now invalid */
1226 register_cache_invalidate(armv4_5->core_cache);
1227
1228 /* SVC, ARM state, IRQ and FIQ disabled */
1229 uint32_t cpsr;
1230
1231 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1232 cpsr &= ~0xff;
1233 cpsr |= 0xd3;
1234 arm_set_cpsr(armv4_5, cpsr);
1235 armv4_5->cpsr->dirty = 1;
1236
1237 /* start fetching from 0x0 */
1238 buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
1239 armv4_5->pc->dirty = 1;
1240 armv4_5->pc->valid = 1;
1241
1242 /* reset registers */
1243 for (i = 0; i <= 14; i++)
1244 {
1245 struct reg *r = arm_reg_current(armv4_5, i);
1246
1247 buf_set_u32(r->value, 0, 32, 0xffffffff);
1248 r->dirty = 1;
1249 r->valid = 1;
1250 }
1251
1252 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1253 {
1254 return retval;
1255 }
1256
1257 return ERROR_OK;
1258 }
1259
1260 /**
1261 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1262 * line or by programming a watchpoint to trigger on any address. It is
1263 * considered a bug to call this function while the target is in the
1264 * TARGET_RESET state.
1265 *
1266 * @param target Pointer to the ARM7/9 target to be halted
1267 * @return Always ERROR_OK
1268 */
1269 int arm7_9_halt(struct target *target)
1270 {
1271 if (target->state == TARGET_RESET)
1272 {
1273 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1274 return ERROR_OK;
1275 }
1276
1277 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1278 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1279
1280 LOG_DEBUG("target->state: %s",
1281 target_state_name(target));
1282
1283 if (target->state == TARGET_HALTED)
1284 {
1285 LOG_DEBUG("target was already halted");
1286 return ERROR_OK;
1287 }
1288
1289 if (target->state == TARGET_UNKNOWN)
1290 {
1291 LOG_WARNING("target was in unknown state when halt was requested");
1292 }
1293
1294 if (arm7_9->use_dbgrq)
1295 {
1296 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1297 */
1298 if (arm7_9->set_special_dbgrq) {
1299 arm7_9->set_special_dbgrq(target);
1300 } else {
1301 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1302 embeddedice_store_reg(dbg_ctrl);
1303 }
1304 }
1305 else
1306 {
1307 /* program watchpoint unit to match on any address
1308 */
1309 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1310 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1311 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1312 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1313 }
1314
1315 target->debug_reason = DBG_REASON_DBGRQ;
1316
1317 return ERROR_OK;
1318 }
1319
1320 /**
1321 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1322 * ARM. The JTAG queue is then executed and the reason for debug entry is
1323 * examined. Once done, the target is verified to be halted and the processor
1324 * is forced into ARM mode. The core registers are saved for the current core
1325 * mode and the program counter (register 15) is updated as needed. The core
1326 * registers and CPSR and SPSR are saved for restoration later.
1327 *
1328 * @param target Pointer to target that is entering debug mode
1329 * @return Error code if anything fails, otherwise ERROR_OK
1330 */
1331 static int arm7_9_debug_entry(struct target *target)
1332 {
1333 int i;
1334 uint32_t context[16];
1335 uint32_t* context_p[16];
1336 uint32_t r0_thumb, pc_thumb;
1337 uint32_t cpsr, cpsr_mask = 0;
1338 int retval;
1339 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1340 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1341 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1342 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1343
1344 #ifdef _DEBUG_ARM7_9_
1345 LOG_DEBUG("-");
1346 #endif
1347
1348 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1349 * ensure that DBGRQ is cleared
1350 */
1351 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1352 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1353 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1354 embeddedice_store_reg(dbg_ctrl);
1355
1356 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1357 {
1358 return retval;
1359 }
1360
1361 if ((retval = jtag_execute_queue()) != ERROR_OK)
1362 {
1363 return retval;
1364 }
1365
1366 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1367 return retval;
1368
1369
1370 if (target->state != TARGET_HALTED)
1371 {
1372 LOG_WARNING("target not halted");
1373 return ERROR_TARGET_NOT_HALTED;
1374 }
1375
1376 /* if the target is in Thumb state, change to ARM state */
1377 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1378 {
1379 LOG_DEBUG("target entered debug from Thumb state");
1380 /* Entered debug from Thumb mode */
1381 armv4_5->core_state = ARM_STATE_THUMB;
1382 cpsr_mask = 1 << 5;
1383 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1384 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1385 ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1386 } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1387 /* \todo Get some vaguely correct handling of Jazelle, if
1388 * anyone ever uses it and full info becomes available.
1389 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1390 * B.7.3 for the reverse. That'd be the bare minimum...
1391 */
1392 LOG_DEBUG("target entered debug from Jazelle state");
1393 armv4_5->core_state = ARM_STATE_JAZELLE;
1394 cpsr_mask = 1 << 24;
1395 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1396 } else {
1397 LOG_DEBUG("target entered debug from ARM state");
1398 /* Entered debug from ARM mode */
1399 armv4_5->core_state = ARM_STATE_ARM;
1400 }
1401
1402 for (i = 0; i < 16; i++)
1403 context_p[i] = &context[i];
1404 /* save core registers (r0 - r15 of current core mode) */
1405 arm7_9->read_core_regs(target, 0xffff, context_p);
1406
1407 arm7_9->read_xpsr(target, &cpsr, 0);
1408
1409 if ((retval = jtag_execute_queue()) != ERROR_OK)
1410 return retval;
1411
1412 /* Sync our CPSR copy with J or T bits EICE reported, but
1413 * which we then erased by putting the core into ARM mode.
1414 */
1415 arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
1416
1417 if (!is_arm_mode(armv4_5->core_mode))
1418 {
1419 target->state = TARGET_UNKNOWN;
1420 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1421 return ERROR_TARGET_FAILURE;
1422 }
1423
1424 LOG_DEBUG("target entered debug state in %s mode",
1425 arm_mode_name(armv4_5->core_mode));
1426
1427 if (armv4_5->core_state == ARM_STATE_THUMB)
1428 {
1429 LOG_DEBUG("thumb state, applying fixups");
1430 context[0] = r0_thumb;
1431 context[15] = pc_thumb;
1432 } else if (armv4_5->core_state == ARM_STATE_ARM)
1433 {
1434 /* adjust value stored by STM */
1435 context[15] -= 3 * 4;
1436 }
1437
1438 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1439 context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1440 else
1441 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1442
1443 for (i = 0; i <= 15; i++)
1444 {
1445 struct reg *r = arm_reg_current(armv4_5, i);
1446
1447 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1448
1449 buf_set_u32(r->value, 0, 32, context[i]);
1450 /* r0 and r15 (pc) have to be restored later */
1451 r->dirty = (i == 0) || (i == 15);
1452 r->valid = 1;
1453 }
1454
1455 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1456
1457 /* exceptions other than USR & SYS have a saved program status register */
1458 if (armv4_5->spsr) {
1459 uint32_t spsr;
1460 arm7_9->read_xpsr(target, &spsr, 1);
1461 if ((retval = jtag_execute_queue()) != ERROR_OK)
1462 {
1463 return retval;
1464 }
1465 buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
1466 armv4_5->spsr->dirty = 0;
1467 armv4_5->spsr->valid = 1;
1468 }
1469
1470 if ((retval = jtag_execute_queue()) != ERROR_OK)
1471 return retval;
1472
1473 if (arm7_9->post_debug_entry)
1474 arm7_9->post_debug_entry(target);
1475
1476 return ERROR_OK;
1477 }
1478
1479 /**
1480 * Validate the full context for an ARM7/9 target in all processor modes. If
1481 * there are any invalid registers for the target, they will all be read. This
1482 * includes the PSR.
1483 *
1484 * @param target Pointer to the ARM7/9 target to capture the full context from
1485 * @return Error if the target is not halted, has an invalid core mode, or if
1486 * the JTAG queue fails to execute
1487 */
1488 int arm7_9_full_context(struct target *target)
1489 {
1490 int i;
1491 int retval;
1492 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1493 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1494
1495 LOG_DEBUG("-");
1496
1497 if (target->state != TARGET_HALTED)
1498 {
1499 LOG_WARNING("target not halted");
1500 return ERROR_TARGET_NOT_HALTED;
1501 }
1502
1503 if (!is_arm_mode(armv4_5->core_mode))
1504 return ERROR_FAIL;
1505
1506 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1507 * SYS shares registers with User, so we don't touch SYS
1508 */
1509 for (i = 0; i < 6; i++)
1510 {
1511 uint32_t mask = 0;
1512 uint32_t* reg_p[16];
1513 int j;
1514 int valid = 1;
1515
1516 /* check if there are invalid registers in the current mode
1517 */
1518 for (j = 0; j <= 16; j++)
1519 {
1520 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1521 valid = 0;
1522 }
1523
1524 if (!valid)
1525 {
1526 uint32_t tmp_cpsr;
1527
1528 /* change processor mode (and mask T bit) */
1529 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1530 & 0xe0;
1531 tmp_cpsr |= armv4_5_number_to_mode(i);
1532 tmp_cpsr &= ~0x20;
1533 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1534
1535 for (j = 0; j < 15; j++)
1536 {
1537 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1538 {
1539 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1540 mask |= 1 << j;
1541 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1542 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1543 }
1544 }
1545
1546 /* if only the PSR is invalid, mask is all zeroes */
1547 if (mask)
1548 arm7_9->read_core_regs(target, mask, reg_p);
1549
1550 /* check if the PSR has to be read */
1551 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1552 {
1553 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1554 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1555 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1556 }
1557 }
1558 }
1559
1560 /* restore processor mode (mask T bit) */
1561 arm7_9->write_xpsr_im8(target,
1562 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1563 0, 0);
1564
1565 if ((retval = jtag_execute_queue()) != ERROR_OK)
1566 {
1567 return retval;
1568 }
1569 return ERROR_OK;
1570 }
1571
1572 /**
1573 * Restore the processor context on an ARM7/9 target. The full processor
1574 * context is analyzed to see if any of the registers are dirty on this end, but
1575 * have a valid new value. If this is the case, the processor is changed to the
1576 * appropriate mode and the new register values are written out to the
1577 * processor. If there happens to be a dirty register with an invalid value, an
1578 * error will be logged.
1579 *
1580 * @param target Pointer to the ARM7/9 target to have its context restored
1581 * @return Error status if the target is not halted or the core mode in the
1582 * armv4_5 struct is invalid.
1583 */
1584 int arm7_9_restore_context(struct target *target)
1585 {
1586 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1587 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1588 struct reg *reg;
1589 struct arm_reg *reg_arch_info;
1590 enum arm_mode current_mode = armv4_5->core_mode;
1591 int i, j;
1592 int dirty;
1593 int mode_change;
1594
1595 LOG_DEBUG("-");
1596
1597 if (target->state != TARGET_HALTED)
1598 {
1599 LOG_WARNING("target not halted");
1600 return ERROR_TARGET_NOT_HALTED;
1601 }
1602
1603 if (arm7_9->pre_restore_context)
1604 arm7_9->pre_restore_context(target);
1605
1606 if (!is_arm_mode(armv4_5->core_mode))
1607 return ERROR_FAIL;
1608
1609 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1610 * SYS shares registers with User, so we don't touch SYS
1611 */
1612 for (i = 0; i < 6; i++)
1613 {
1614 LOG_DEBUG("examining %s mode",
1615 arm_mode_name(armv4_5->core_mode));
1616 dirty = 0;
1617 mode_change = 0;
1618 /* check if there are dirty registers in the current mode
1619 */
1620 for (j = 0; j <= 16; j++)
1621 {
1622 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1623 reg_arch_info = reg->arch_info;
1624 if (reg->dirty == 1)
1625 {
1626 if (reg->valid == 1)
1627 {
1628 dirty = 1;
1629 LOG_DEBUG("examining dirty reg: %s", reg->name);
1630 if ((reg_arch_info->mode != ARM_MODE_ANY)
1631 && (reg_arch_info->mode != current_mode)
1632 && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
1633 && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
1634 {
1635 mode_change = 1;
1636 LOG_DEBUG("require mode change");
1637 }
1638 }
1639 else
1640 {
1641 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1642 }
1643 }
1644 }
1645
1646 if (dirty)
1647 {
1648 uint32_t mask = 0x0;
1649 int num_regs = 0;
1650 uint32_t regs[16];
1651
1652 if (mode_change)
1653 {
1654 uint32_t tmp_cpsr;
1655
1656 /* change processor mode (mask T bit) */
1657 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1658 0, 8) & 0xe0;
1659 tmp_cpsr |= armv4_5_number_to_mode(i);
1660 tmp_cpsr &= ~0x20;
1661 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1662 current_mode = armv4_5_number_to_mode(i);
1663 }
1664
1665 for (j = 0; j <= 14; j++)
1666 {
1667 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1668 reg_arch_info = reg->arch_info;
1669
1670
1671 if (reg->dirty == 1)
1672 {
1673 regs[j] = buf_get_u32(reg->value, 0, 32);
1674 mask |= 1 << j;
1675 num_regs++;
1676 reg->dirty = 0;
1677 reg->valid = 1;
1678 LOG_DEBUG("writing register %i mode %s "
1679 "with value 0x%8.8" PRIx32, j,
1680 arm_mode_name(armv4_5->core_mode),
1681 regs[j]);
1682 }
1683 }
1684
1685 if (mask)
1686 {
1687 arm7_9->write_core_regs(target, mask, regs);
1688 }
1689
1690 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1691 reg_arch_info = reg->arch_info;
1692 if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
1693 {
1694 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1695 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1696 }
1697 }
1698 }
1699
1700 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1701 {
1702 /* restore processor mode (mask T bit) */
1703 uint32_t tmp_cpsr;
1704
1705 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1706 tmp_cpsr |= armv4_5_number_to_mode(i);
1707 tmp_cpsr &= ~0x20;
1708 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1709 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1710 }
1711 else if (armv4_5->cpsr->dirty)
1712 {
1713 /* CPSR has been changed, full restore necessary (mask T bit) */
1714 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1715 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1716 arm7_9->write_xpsr(target,
1717 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1718 & ~0x20, 0);
1719 armv4_5->cpsr->dirty = 0;
1720 armv4_5->cpsr->valid = 1;
1721 }
1722
1723 /* restore PC */
1724 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1725 buf_get_u32(armv4_5->pc->value, 0, 32));
1726 arm7_9->write_pc(target, buf_get_u32(armv4_5->pc->value, 0, 32));
1727 armv4_5->pc->dirty = 0;
1728
1729 if (arm7_9->post_restore_context)
1730 arm7_9->post_restore_context(target);
1731
1732 return ERROR_OK;
1733 }
1734
1735 /**
1736 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1737 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1738 * restart.
1739 *
1740 * @param target Pointer to the ARM7/9 target to be restarted
1741 * @return Result of executing the JTAG queue
1742 */
1743 int arm7_9_restart_core(struct target *target)
1744 {
1745 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1746 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1747
1748 /* set RESTART instruction */
1749 jtag_set_end_state(TAP_IDLE);
1750 if (arm7_9->need_bypass_before_restart) {
1751 arm7_9->need_bypass_before_restart = 0;
1752 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1753 }
1754 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1755
1756 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1757 return jtag_execute_queue();
1758 }
1759
1760 /**
1761 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1762 * iterated through and are set on the target if they aren't already set.
1763 *
1764 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1765 */
1766 void arm7_9_enable_watchpoints(struct target *target)
1767 {
1768 struct watchpoint *watchpoint = target->watchpoints;
1769
1770 while (watchpoint)
1771 {
1772 if (watchpoint->set == 0)
1773 arm7_9_set_watchpoint(target, watchpoint);
1774 watchpoint = watchpoint->next;
1775 }
1776 }
1777
1778 /**
1779 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1780 * iterated through and are set on the target.
1781 *
1782 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1783 */
1784 void arm7_9_enable_breakpoints(struct target *target)
1785 {
1786 struct breakpoint *breakpoint = target->breakpoints;
1787
1788 /* set any pending breakpoints */
1789 while (breakpoint)
1790 {
1791 arm7_9_set_breakpoint(target, breakpoint);
1792 breakpoint = breakpoint->next;
1793 }
1794 }
1795
1796 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1797 {
1798 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1799 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1800 struct breakpoint *breakpoint = target->breakpoints;
1801 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1802 int err, retval = ERROR_OK;
1803
1804 LOG_DEBUG("-");
1805
1806 if (target->state != TARGET_HALTED)
1807 {
1808 LOG_WARNING("target not halted");
1809 return ERROR_TARGET_NOT_HALTED;
1810 }
1811
1812 if (!debug_execution)
1813 {
1814 target_free_all_working_areas(target);
1815 }
1816
1817 /* current = 1: continue on current pc, otherwise continue at <address> */
1818 if (!current)
1819 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1820
1821 uint32_t current_pc;
1822 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1823
1824 /* the front-end may request us not to handle breakpoints */
1825 if (handle_breakpoints)
1826 {
1827 breakpoint = breakpoint_find(target,
1828 buf_get_u32(armv4_5->pc->value, 0, 32));
1829 if (breakpoint != NULL)
1830 {
1831 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1832 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1833 {
1834 return retval;
1835 }
1836
1837 /* calculate PC of next instruction */
1838 uint32_t next_pc;
1839 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1840 {
1841 uint32_t current_opcode;
1842 target_read_u32(target, current_pc, &current_opcode);
1843 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1844 return retval;
1845 }
1846
1847 LOG_DEBUG("enable single-step");
1848 arm7_9->enable_single_step(target, next_pc);
1849
1850 target->debug_reason = DBG_REASON_SINGLESTEP;
1851
1852 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1853 {
1854 return retval;
1855 }
1856
1857 if (armv4_5->core_state == ARM_STATE_ARM)
1858 arm7_9->branch_resume(target);
1859 else if (armv4_5->core_state == ARM_STATE_THUMB)
1860 {
1861 arm7_9->branch_resume_thumb(target);
1862 }
1863 else
1864 {
1865 LOG_ERROR("unhandled core state");
1866 return ERROR_FAIL;
1867 }
1868
1869 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1870 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1871 err = arm7_9_execute_sys_speed(target);
1872
1873 LOG_DEBUG("disable single-step");
1874 arm7_9->disable_single_step(target);
1875
1876 if (err != ERROR_OK)
1877 {
1878 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1879 {
1880 return retval;
1881 }
1882 target->state = TARGET_UNKNOWN;
1883 return err;
1884 }
1885
1886 arm7_9_debug_entry(target);
1887 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
1888 buf_get_u32(armv4_5->pc->value, 0, 32));
1889
1890 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1891 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1892 {
1893 return retval;
1894 }
1895 }
1896 }
1897
1898 /* enable any pending breakpoints and watchpoints */
1899 arm7_9_enable_breakpoints(target);
1900 arm7_9_enable_watchpoints(target);
1901
1902 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1903 {
1904 return retval;
1905 }
1906
1907 if (armv4_5->core_state == ARM_STATE_ARM)
1908 {
1909 arm7_9->branch_resume(target);
1910 }
1911 else if (armv4_5->core_state == ARM_STATE_THUMB)
1912 {
1913 arm7_9->branch_resume_thumb(target);
1914 }
1915 else
1916 {
1917 LOG_ERROR("unhandled core state");
1918 return ERROR_FAIL;
1919 }
1920
1921 /* deassert DBGACK and INTDIS */
1922 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1923 /* INTDIS only when we really resume, not during debug execution */
1924 if (!debug_execution)
1925 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1926 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1927
1928 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1929 {
1930 return retval;
1931 }
1932
1933 target->debug_reason = DBG_REASON_NOTHALTED;
1934
1935 if (!debug_execution)
1936 {
1937 /* registers are now invalid */
1938 register_cache_invalidate(armv4_5->core_cache);
1939 target->state = TARGET_RUNNING;
1940 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1941 {
1942 return retval;
1943 }
1944 }
1945 else
1946 {
1947 target->state = TARGET_DEBUG_RUNNING;
1948 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1949 {
1950 return retval;
1951 }
1952 }
1953
1954 LOG_DEBUG("target resumed");
1955
1956 return ERROR_OK;
1957 }
1958
1959 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1960 {
1961 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1962 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1963 uint32_t current_pc;
1964 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1965
1966 if (next_pc != current_pc)
1967 {
1968 /* setup an inverse breakpoint on the current PC
1969 * - comparator 1 matches the current address
1970 * - rangeout from comparator 1 is connected to comparator 0 rangein
1971 * - comparator 0 matches any address, as long as rangein is low */
1972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1980 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1981 }
1982 else
1983 {
1984 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1985 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1986 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1987 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1988 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1989 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1990 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1991 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1992 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1993 }
1994 }
1995
1996 void arm7_9_disable_eice_step(struct target *target)
1997 {
1998 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1999
2000 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
2001 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
2002 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
2003 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
2004 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
2005 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
2006 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
2007 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
2008 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
2009 }
2010
2011 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2012 {
2013 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2014 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2015 struct breakpoint *breakpoint = NULL;
2016 int err, retval;
2017
2018 if (target->state != TARGET_HALTED)
2019 {
2020 LOG_WARNING("target not halted");
2021 return ERROR_TARGET_NOT_HALTED;
2022 }
2023
2024 /* current = 1: continue on current pc, otherwise continue at <address> */
2025 if (!current)
2026 buf_set_u32(armv4_5->pc->value, 0, 32, address);
2027
2028 uint32_t current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
2029
2030 /* the front-end may request us not to handle breakpoints */
2031 if (handle_breakpoints)
2032 breakpoint = breakpoint_find(target, current_pc);
2033 if (breakpoint != NULL) {
2034 retval = arm7_9_unset_breakpoint(target, breakpoint);
2035 if (retval != ERROR_OK)
2036 return retval;
2037 }
2038
2039 target->debug_reason = DBG_REASON_SINGLESTEP;
2040
2041 /* calculate PC of next instruction */
2042 uint32_t next_pc;
2043 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2044 {
2045 uint32_t current_opcode;
2046 target_read_u32(target, current_pc, &current_opcode);
2047 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2048 return retval;
2049 }
2050
2051 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2052 {
2053 return retval;
2054 }
2055
2056 arm7_9->enable_single_step(target, next_pc);
2057
2058 if (armv4_5->core_state == ARM_STATE_ARM)
2059 {
2060 arm7_9->branch_resume(target);
2061 }
2062 else if (armv4_5->core_state == ARM_STATE_THUMB)
2063 {
2064 arm7_9->branch_resume_thumb(target);
2065 }
2066 else
2067 {
2068 LOG_ERROR("unhandled core state");
2069 return ERROR_FAIL;
2070 }
2071
2072 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2073 {
2074 return retval;
2075 }
2076
2077 err = arm7_9_execute_sys_speed(target);
2078 arm7_9->disable_single_step(target);
2079
2080 /* registers are now invalid */
2081 register_cache_invalidate(armv4_5->core_cache);
2082
2083 if (err != ERROR_OK)
2084 {
2085 target->state = TARGET_UNKNOWN;
2086 } else {
2087 arm7_9_debug_entry(target);
2088 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2089 {
2090 return retval;
2091 }
2092 LOG_DEBUG("target stepped");
2093 }
2094
2095 if (breakpoint)
2096 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2097 {
2098 return retval;
2099 }
2100
2101 return err;
2102 }
2103
2104 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2105 int num, enum arm_mode mode)
2106 {
2107 uint32_t* reg_p[16];
2108 uint32_t value;
2109 int retval;
2110 struct arm_reg *areg = r->arch_info;
2111 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2112 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2113
2114 if (!is_arm_mode(armv4_5->core_mode))
2115 return ERROR_FAIL;
2116 if ((num < 0) || (num > 16))
2117 return ERROR_INVALID_ARGUMENTS;
2118
2119 if ((mode != ARM_MODE_ANY)
2120 && (mode != armv4_5->core_mode)
2121 && (areg->mode != ARM_MODE_ANY))
2122 {
2123 uint32_t tmp_cpsr;
2124
2125 /* change processor mode (mask T bit) */
2126 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2127 tmp_cpsr |= mode;
2128 tmp_cpsr &= ~0x20;
2129 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2130 }
2131
2132 if ((num >= 0) && (num <= 15))
2133 {
2134 /* read a normal core register */
2135 reg_p[num] = &value;
2136
2137 arm7_9->read_core_regs(target, 1 << num, reg_p);
2138 }
2139 else
2140 {
2141 /* read a program status register
2142 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2143 */
2144 arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
2145 }
2146
2147 if ((retval = jtag_execute_queue()) != ERROR_OK)
2148 {
2149 return retval;
2150 }
2151
2152 r->valid = 1;
2153 r->dirty = 0;
2154 buf_set_u32(r->value, 0, 32, value);
2155
2156 if ((mode != ARM_MODE_ANY)
2157 && (mode != armv4_5->core_mode)
2158 && (areg->mode != ARM_MODE_ANY)) {
2159 /* restore processor mode (mask T bit) */
2160 arm7_9->write_xpsr_im8(target,
2161 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2162 & ~0x20, 0, 0);
2163 }
2164
2165 return ERROR_OK;
2166 }
2167
2168 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2169 int num, enum arm_mode mode, uint32_t value)
2170 {
2171 uint32_t reg[16];
2172 struct arm_reg *areg = r->arch_info;
2173 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2174 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2175
2176 if (!is_arm_mode(armv4_5->core_mode))
2177 return ERROR_FAIL;
2178 if ((num < 0) || (num > 16))
2179 return ERROR_INVALID_ARGUMENTS;
2180
2181 if ((mode != ARM_MODE_ANY)
2182 && (mode != armv4_5->core_mode)
2183 && (areg->mode != ARM_MODE_ANY)) {
2184 uint32_t tmp_cpsr;
2185
2186 /* change processor mode (mask T bit) */
2187 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2188 tmp_cpsr |= mode;
2189 tmp_cpsr &= ~0x20;
2190 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2191 }
2192
2193 if ((num >= 0) && (num <= 15))
2194 {
2195 /* write a normal core register */
2196 reg[num] = value;
2197
2198 arm7_9->write_core_regs(target, 1 << num, reg);
2199 }
2200 else
2201 {
2202 /* write a program status register
2203 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2204 */
2205 int spsr = (areg->mode != ARM_MODE_ANY);
2206
2207 /* if we're writing the CPSR, mask the T bit */
2208 if (!spsr)
2209 value &= ~0x20;
2210
2211 arm7_9->write_xpsr(target, value, spsr);
2212 }
2213
2214 r->valid = 1;
2215 r->dirty = 0;
2216
2217 if ((mode != ARM_MODE_ANY)
2218 && (mode != armv4_5->core_mode)
2219 && (areg->mode != ARM_MODE_ANY)) {
2220 /* restore processor mode (mask T bit) */
2221 arm7_9->write_xpsr_im8(target,
2222 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2223 & ~0x20, 0, 0);
2224 }
2225
2226 return jtag_execute_queue();
2227 }
2228
2229 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2230 {
2231 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2232 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2233 uint32_t reg[16];
2234 uint32_t num_accesses = 0;
2235 int thisrun_accesses;
2236 int i;
2237 uint32_t cpsr;
2238 int retval;
2239 int last_reg = 0;
2240
2241 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2242
2243 if (target->state != TARGET_HALTED)
2244 {
2245 LOG_WARNING("target not halted");
2246 return ERROR_TARGET_NOT_HALTED;
2247 }
2248
2249 /* sanitize arguments */
2250 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2251 return ERROR_INVALID_ARGUMENTS;
2252
2253 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2254 return ERROR_TARGET_UNALIGNED_ACCESS;
2255
2256 /* load the base register with the address of the first word */
2257 reg[0] = address;
2258 arm7_9->write_core_regs(target, 0x1, reg);
2259
2260 int j = 0;
2261
2262 switch (size)
2263 {
2264 case 4:
2265 while (num_accesses < count)
2266 {
2267 uint32_t reg_list;
2268 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2269 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2270
2271 if (last_reg <= thisrun_accesses)
2272 last_reg = thisrun_accesses;
2273
2274 arm7_9->load_word_regs(target, reg_list);
2275
2276 /* fast memory reads are only safe when the target is running
2277 * from a sufficiently high clock (32 kHz is usually too slow)
2278 */
2279 if (arm7_9->fast_memory_access)
2280 retval = arm7_9_execute_fast_sys_speed(target);
2281 else
2282 retval = arm7_9_execute_sys_speed(target);
2283 if (retval != ERROR_OK)
2284 return retval;
2285
2286 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2287
2288 /* advance buffer, count number of accesses */
2289 buffer += thisrun_accesses * 4;
2290 num_accesses += thisrun_accesses;
2291
2292 if ((j++%1024) == 0)
2293 {
2294 keep_alive();
2295 }
2296 }
2297 break;
2298 case 2:
2299 while (num_accesses < count)
2300 {
2301 uint32_t reg_list;
2302 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2303 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2304
2305 for (i = 1; i <= thisrun_accesses; i++)
2306 {
2307 if (i > last_reg)
2308 last_reg = i;
2309 arm7_9->load_hword_reg(target, i);
2310 /* fast memory reads are only safe when the target is running
2311 * from a sufficiently high clock (32 kHz is usually too slow)
2312 */
2313 if (arm7_9->fast_memory_access)
2314 retval = arm7_9_execute_fast_sys_speed(target);
2315 else
2316 retval = arm7_9_execute_sys_speed(target);
2317 if (retval != ERROR_OK)
2318 {
2319 return retval;
2320 }
2321
2322 }
2323
2324 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2325
2326 /* advance buffer, count number of accesses */
2327 buffer += thisrun_accesses * 2;
2328 num_accesses += thisrun_accesses;
2329
2330 if ((j++%1024) == 0)
2331 {
2332 keep_alive();
2333 }
2334 }
2335 break;
2336 case 1:
2337 while (num_accesses < count)
2338 {
2339 uint32_t reg_list;
2340 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2341 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2342
2343 for (i = 1; i <= thisrun_accesses; i++)
2344 {
2345 if (i > last_reg)
2346 last_reg = i;
2347 arm7_9->load_byte_reg(target, i);
2348 /* fast memory reads are only safe when the target is running
2349 * from a sufficiently high clock (32 kHz is usually too slow)
2350 */
2351 if (arm7_9->fast_memory_access)
2352 retval = arm7_9_execute_fast_sys_speed(target);
2353 else
2354 retval = arm7_9_execute_sys_speed(target);
2355 if (retval != ERROR_OK)
2356 {
2357 return retval;
2358 }
2359 }
2360
2361 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2362
2363 /* advance buffer, count number of accesses */
2364 buffer += thisrun_accesses * 1;
2365 num_accesses += thisrun_accesses;
2366
2367 if ((j++%1024) == 0)
2368 {
2369 keep_alive();
2370 }
2371 }
2372 break;
2373 }
2374
2375 if (!is_arm_mode(armv4_5->core_mode))
2376 return ERROR_FAIL;
2377
2378 for (i = 0; i <= last_reg; i++) {
2379 struct reg *r = arm_reg_current(armv4_5, i);
2380
2381 r->dirty = r->valid;
2382 }
2383
2384 arm7_9->read_xpsr(target, &cpsr, 0);
2385 if ((retval = jtag_execute_queue()) != ERROR_OK)
2386 {
2387 LOG_ERROR("JTAG error while reading cpsr");
2388 return ERROR_TARGET_DATA_ABORT;
2389 }
2390
2391 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2392 {
2393 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2394
2395 arm7_9->write_xpsr_im8(target,
2396 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2397 & ~0x20, 0, 0);
2398
2399 return ERROR_TARGET_DATA_ABORT;
2400 }
2401
2402 return ERROR_OK;
2403 }
2404
2405 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2406 {
2407 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2408 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2409 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2410
2411 uint32_t reg[16];
2412 uint32_t num_accesses = 0;
2413 int thisrun_accesses;
2414 int i;
2415 uint32_t cpsr;
2416 int retval;
2417 int last_reg = 0;
2418
2419 #ifdef _DEBUG_ARM7_9_
2420 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2421 #endif
2422
2423 if (target->state != TARGET_HALTED)
2424 {
2425 LOG_WARNING("target not halted");
2426 return ERROR_TARGET_NOT_HALTED;
2427 }
2428
2429 /* sanitize arguments */
2430 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2431 return ERROR_INVALID_ARGUMENTS;
2432
2433 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2434 return ERROR_TARGET_UNALIGNED_ACCESS;
2435
2436 /* load the base register with the address of the first word */
2437 reg[0] = address;
2438 arm7_9->write_core_regs(target, 0x1, reg);
2439
2440 /* Clear DBGACK, to make sure memory fetches work as expected */
2441 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2442 embeddedice_store_reg(dbg_ctrl);
2443
2444 switch (size)
2445 {
2446 case 4:
2447 while (num_accesses < count)
2448 {
2449 uint32_t reg_list;
2450 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2451 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2452
2453 for (i = 1; i <= thisrun_accesses; i++)
2454 {
2455 if (i > last_reg)
2456 last_reg = i;
2457 reg[i] = target_buffer_get_u32(target, buffer);
2458 buffer += 4;
2459 }
2460
2461 arm7_9->write_core_regs(target, reg_list, reg);
2462
2463 arm7_9->store_word_regs(target, reg_list);
2464
2465 /* fast memory writes are only safe when the target is running
2466 * from a sufficiently high clock (32 kHz is usually too slow)
2467 */
2468 if (arm7_9->fast_memory_access)
2469 retval = arm7_9_execute_fast_sys_speed(target);
2470 else
2471 retval = arm7_9_execute_sys_speed(target);
2472 if (retval != ERROR_OK)
2473 {
2474 return retval;
2475 }
2476
2477 num_accesses += thisrun_accesses;
2478 }
2479 break;
2480 case 2:
2481 while (num_accesses < count)
2482 {
2483 uint32_t reg_list;
2484 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2485 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2486
2487 for (i = 1; i <= thisrun_accesses; i++)
2488 {
2489 if (i > last_reg)
2490 last_reg = i;
2491 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2492 buffer += 2;
2493 }
2494
2495 arm7_9->write_core_regs(target, reg_list, reg);
2496
2497 for (i = 1; i <= thisrun_accesses; i++)
2498 {
2499 arm7_9->store_hword_reg(target, i);
2500
2501 /* fast memory writes are only safe when the target is running
2502 * from a sufficiently high clock (32 kHz is usually too slow)
2503 */
2504 if (arm7_9->fast_memory_access)
2505 retval = arm7_9_execute_fast_sys_speed(target);
2506 else
2507 retval = arm7_9_execute_sys_speed(target);
2508 if (retval != ERROR_OK)
2509 {
2510 return retval;
2511 }
2512 }
2513
2514 num_accesses += thisrun_accesses;
2515 }
2516 break;
2517 case 1:
2518 while (num_accesses < count)
2519 {
2520 uint32_t reg_list;
2521 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2522 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2523
2524 for (i = 1; i <= thisrun_accesses; i++)
2525 {
2526 if (i > last_reg)
2527 last_reg = i;
2528 reg[i] = *buffer++ & 0xff;
2529 }
2530
2531 arm7_9->write_core_regs(target, reg_list, reg);
2532
2533 for (i = 1; i <= thisrun_accesses; i++)
2534 {
2535 arm7_9->store_byte_reg(target, i);
2536 /* fast memory writes are only safe when the target is running
2537 * from a sufficiently high clock (32 kHz is usually too slow)
2538 */
2539 if (arm7_9->fast_memory_access)
2540 retval = arm7_9_execute_fast_sys_speed(target);
2541 else
2542 retval = arm7_9_execute_sys_speed(target);
2543 if (retval != ERROR_OK)
2544 {
2545 return retval;
2546 }
2547
2548 }
2549
2550 num_accesses += thisrun_accesses;
2551 }
2552 break;
2553 }
2554
2555 /* Re-Set DBGACK */
2556 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2557 embeddedice_store_reg(dbg_ctrl);
2558
2559 if (!is_arm_mode(armv4_5->core_mode))
2560 return ERROR_FAIL;
2561
2562 for (i = 0; i <= last_reg; i++) {
2563 struct reg *r = arm_reg_current(armv4_5, i);
2564
2565 r->dirty = r->valid;
2566 }
2567
2568 arm7_9->read_xpsr(target, &cpsr, 0);
2569 if ((retval = jtag_execute_queue()) != ERROR_OK)
2570 {
2571 LOG_ERROR("JTAG error while reading cpsr");
2572 return ERROR_TARGET_DATA_ABORT;
2573 }
2574
2575 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2576 {
2577 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2578
2579 arm7_9->write_xpsr_im8(target,
2580 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2581 & ~0x20, 0, 0);
2582
2583 return ERROR_TARGET_DATA_ABORT;
2584 }
2585
2586 return ERROR_OK;
2587 }
2588
2589 static int dcc_count;
2590 static uint8_t *dcc_buffer;
2591
2592 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2593 {
2594 int retval = ERROR_OK;
2595 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2596
2597 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2598 return retval;
2599
2600 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2601 int count = dcc_count;
2602 uint8_t *buffer = dcc_buffer;
2603 if (count > 2)
2604 {
2605 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2606 * core function repeated. */
2607 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2608 buffer += 4;
2609
2610 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2611 uint8_t reg_addr = ice_reg->addr & 0x1f;
2612 struct jtag_tap *tap;
2613 tap = ice_reg->jtag_info->tap;
2614
2615 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2616 buffer += (count-2)*4;
2617
2618 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2619 } else
2620 {
2621 int i;
2622 for (i = 0; i < count; i++)
2623 {
2624 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2625 buffer += 4;
2626 }
2627 }
2628
2629 if ((retval = target_halt(target))!= ERROR_OK)
2630 {
2631 return retval;
2632 }
2633 return target_wait_state(target, TARGET_HALTED, 500);
2634 }
2635
2636 static const uint32_t dcc_code[] =
2637 {
2638 /* r0 == input, points to memory buffer
2639 * r1 == scratch
2640 */
2641
2642 /* spin until DCC control (c0) reports data arrived */
2643 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2644 0xe3110001, /* tst r1, #1 */
2645 0x0afffffc, /* bne w */
2646
2647 /* read word from DCC (c1), write to memory */
2648 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2649 0xe4801004, /* str r1, [r0], #4 */
2650
2651 /* repeat */
2652 0xeafffff9 /* b w */
2653 };
2654
2655 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2656 {
2657 int retval;
2658 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2659 int i;
2660
2661 if (!arm7_9->dcc_downloads)
2662 return target_write_memory(target, address, 4, count, buffer);
2663
2664 /* regrab previously allocated working_area, or allocate a new one */
2665 if (!arm7_9->dcc_working_area)
2666 {
2667 uint8_t dcc_code_buf[6 * 4];
2668
2669 /* make sure we have a working area */
2670 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2671 {
2672 LOG_INFO("no working area available, falling back to memory writes");
2673 return target_write_memory(target, address, 4, count, buffer);
2674 }
2675
2676 /* copy target instructions to target endianness */
2677 for (i = 0; i < 6; i++)
2678 {
2679 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2680 }
2681
2682 /* write DCC code to working area */
2683 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2684 {
2685 return retval;
2686 }
2687 }
2688
2689 struct arm_algorithm armv4_5_info;
2690 struct reg_param reg_params[1];
2691
2692 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
2693 armv4_5_info.core_mode = ARM_MODE_SVC;
2694 armv4_5_info.core_state = ARM_STATE_ARM;
2695
2696 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2697
2698 buf_set_u32(reg_params[0].value, 0, 32, address);
2699
2700 dcc_count = count;
2701 dcc_buffer = buffer;
2702 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2703 arm7_9->dcc_working_area->address,
2704 arm7_9->dcc_working_area->address + 6*4,
2705 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2706
2707 if (retval == ERROR_OK)
2708 {
2709 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2710 if (endaddress != (address + count*4))
2711 {
2712 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2713 retval = ERROR_FAIL;
2714 }
2715 }
2716
2717 destroy_reg_param(&reg_params[0]);
2718
2719 return retval;
2720 }
2721
2722 /**
2723 * Perform per-target setup that requires JTAG access.
2724 */
2725 int arm7_9_examine(struct target *target)
2726 {
2727 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2728 int retval;
2729
2730 if (!target_was_examined(target)) {
2731 struct reg_cache *t, **cache_p;
2732
2733 t = embeddedice_build_reg_cache(target, arm7_9);
2734 if (t == NULL)
2735 return ERROR_FAIL;
2736
2737 cache_p = register_get_last_cache_p(&target->reg_cache);
2738 (*cache_p) = t;
2739 arm7_9->eice_cache = (*cache_p);
2740
2741 if (arm7_9->armv4_5_common.etm)
2742 (*cache_p)->next = etm_build_reg_cache(target,
2743 &arm7_9->jtag_info,
2744 arm7_9->armv4_5_common.etm);
2745
2746 target_set_examined(target);
2747 }
2748
2749 retval = embeddedice_setup(target);
2750 if (retval == ERROR_OK)
2751 retval = arm7_9_setup(target);
2752 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2753 retval = etm_setup(target);
2754 return retval;
2755 }
2756
2757
2758 int arm7_9_check_reset(struct target *target)
2759 {
2760 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2761
2762 if (get_target_reset_nag() && !arm7_9->dcc_downloads)
2763 {
2764 LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
2765 }
2766
2767 if (get_target_reset_nag() && (target->working_area_size == 0))
2768 {
2769 LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
2770 }
2771
2772 if (get_target_reset_nag() && !arm7_9->fast_memory_access)
2773 {
2774 LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
2775 }
2776
2777 return ERROR_OK;
2778 }
2779
2780 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2781 {
2782 struct target *target = get_current_target(CMD_CTX);
2783 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2784
2785 if (!is_arm7_9(arm7_9))
2786 {
2787 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2788 return ERROR_TARGET_INVALID;
2789 }
2790
2791 if (CMD_ARGC > 0)
2792 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2793
2794 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2795
2796 return ERROR_OK;
2797 }
2798
2799 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2800 {
2801 struct target *target = get_current_target(CMD_CTX);
2802 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2803
2804 if (!is_arm7_9(arm7_9))
2805 {
2806 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2807 return ERROR_TARGET_INVALID;
2808 }
2809
2810 if (CMD_ARGC > 0)
2811 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2812
2813 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2814
2815 return ERROR_OK;
2816 }
2817
2818 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2819 {
2820 struct target *target = get_current_target(CMD_CTX);
2821 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2822
2823 if (!is_arm7_9(arm7_9))
2824 {
2825 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2826 return ERROR_TARGET_INVALID;
2827 }
2828
2829 if (CMD_ARGC > 0)
2830 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2831
2832 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2833
2834 return ERROR_OK;
2835 }
2836
2837 COMMAND_HANDLER(handle_arm7_9_semihosting_command)
2838 {
2839 struct target *target = get_current_target(CMD_CTX);
2840 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2841
2842 if (!is_arm7_9(arm7_9))
2843 {
2844 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2845 return ERROR_TARGET_INVALID;
2846 }
2847
2848 if (CMD_ARGC > 0)
2849 {
2850 int semihosting;
2851
2852 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
2853
2854 if (!target_was_examined(target))
2855 {
2856 LOG_ERROR("Target not examined yet");
2857 return ERROR_FAIL;
2858 }
2859
2860 if (arm7_9->has_vector_catch) {
2861 struct reg *vector_catch = &arm7_9->eice_cache
2862 ->reg_list[EICE_VEC_CATCH];
2863
2864 if (!vector_catch->valid)
2865 embeddedice_read_reg(vector_catch);
2866 buf_set_u32(vector_catch->value, 2, 1, semihosting);
2867 embeddedice_store_reg(vector_catch);
2868 } else {
2869 /* TODO: allow optional high vectors and/or BKPT_HARD */
2870 if (semihosting)
2871 breakpoint_add(target, 8, 4, BKPT_SOFT);
2872 else
2873 breakpoint_remove(target, 8);
2874 }
2875
2876 /* FIXME never let that "catch" be dropped! */
2877 arm7_9->armv4_5_common.is_semihosting = semihosting;
2878
2879 }
2880
2881 command_print(CMD_CTX, "semihosting is %s",
2882 arm7_9->armv4_5_common.is_semihosting
2883 ? "enabled" : "disabled");
2884
2885 return ERROR_OK;
2886 }
2887
2888 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2889 {
2890 int retval = ERROR_OK;
2891 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2892
2893 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2894
2895 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2896 return retval;
2897
2898 /* caller must have allocated via calloc(), so everything's zeroed */
2899
2900 arm7_9->wp_available_max = 2;
2901
2902 arm7_9->fast_memory_access = false;
2903 arm7_9->dcc_downloads = false;
2904
2905 armv4_5->arch_info = arm7_9;
2906 armv4_5->read_core_reg = arm7_9_read_core_reg;
2907 armv4_5->write_core_reg = arm7_9_write_core_reg;
2908 armv4_5->full_context = arm7_9_full_context;
2909
2910 retval = arm_init_arch_info(target, armv4_5);
2911 if (retval != ERROR_OK)
2912 return retval;
2913
2914 return target_register_timer_callback(arm7_9_handle_target_request,
2915 1, 1, target);
2916 }
2917
2918 static const struct command_registration arm7_9_any_command_handlers[] = {
2919 {
2920 "dbgrq",
2921 .handler = handle_arm7_9_dbgrq_command,
2922 .mode = COMMAND_ANY,
2923 .usage = "['enable'|'disable']",
2924 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2925 "for target halt requests",
2926 },
2927 {
2928 "fast_memory_access",
2929 .handler = handle_arm7_9_fast_memory_access_command,
2930 .mode = COMMAND_ANY,
2931 .usage = "['enable'|'disable']",
2932 .help = "use fast memory accesses instead of slower "
2933 "but potentially safer accesses",
2934 },
2935 {
2936 "dcc_downloads",
2937 .handler = handle_arm7_9_dcc_downloads_command,
2938 .mode = COMMAND_ANY,
2939 .usage = "['enable'|'disable']",
2940 .help = "use DCC downloads for larger memory writes",
2941 },
2942 {
2943 "semihosting",
2944 .handler = handle_arm7_9_semihosting_command,
2945 .mode = COMMAND_EXEC,
2946 .usage = "['enable'|'disable']",
2947 .help = "activate support for semihosting operations",
2948 },
2949 COMMAND_REGISTRATION_DONE
2950 };
2951 const struct command_registration arm7_9_command_handlers[] = {
2952 {
2953 .chain = arm_command_handlers,
2954 },
2955 {
2956 .chain = etm_command_handlers,
2957 },
2958 {
2959 .name = "arm7_9",
2960 .mode = COMMAND_ANY,
2961 .help = "arm7/9 specific commands",
2962 .chain = arm7_9_any_command_handlers,
2963 },
2964 COMMAND_REGISTRATION_DONE
2965 };
Luca's development patches