?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARMv7: help/usage updates
[openocd/ellerodev.git] / src / target / cortex_m3.c
blobc6b1bb2d893df90ef4c20ee348b87f71ebc6c1b4
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
58 static void cortex_m3_enable_watchpoints(struct target *target);
59 static int cortex_m3_store_core_reg_u32(struct target *target,
60 enum armv7m_regtype type, uint32_t num, uint32_t value);
61
62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
63 uint32_t *value, int regnum)
64 {
65 int retval;
66 uint32_t dcrdr;
67
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
70
71 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
72
73 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
74
75 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
76 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
77 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
78
79 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
80 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
81 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
82
83 retval = swjdp_transaction_endcheck(swjdp);
84
85 /* restore DCB_DCRDR - this needs to be in a seperate
86 * transaction otherwise the emulated DCC channel breaks */
87 if (retval == ERROR_OK)
88 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
89
90 return retval;
91 }
92
93 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
94 uint32_t value, int regnum)
95 {
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101
102 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
103
104 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
105
106 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
107 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
108 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
109
110 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
111 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
112 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
113
114 retval = swjdp_transaction_endcheck(swjdp);
115
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
120
121 return retval;
122 }
123
124 static int cortex_m3_write_debug_halt_mask(struct target *target,
125 uint32_t mask_on, uint32_t mask_off)
126 {
127 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
128 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
129
130 /* mask off status bits */
131 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
132 /* create new register mask */
133 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
134
135 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
136 }
137
138 static int cortex_m3_clear_halt(struct target *target)
139 {
140 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
141 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
142
143 /* clear step if any */
144 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
145
146 /* Read Debug Fault Status Register */
147 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
148
149 /* Clear Debug Fault Status */
150 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
151 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
152
153 return ERROR_OK;
154 }
155
156 static int cortex_m3_single_step_core(struct target *target)
157 {
158 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
159 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
160 uint32_t dhcsr_save;
161
162 /* backup dhcsr reg */
163 dhcsr_save = cortex_m3->dcb_dhcsr;
164
165 /* Mask interrupts before clearing halt, if done already. This avoids
166 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
167 * HALT can put the core into an unknown state.
168 */
169 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
170 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
171 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
172 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
173 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
174 LOG_DEBUG(" ");
175
176 /* restore dhcsr reg */
177 cortex_m3->dcb_dhcsr = dhcsr_save;
178 cortex_m3_clear_halt(target);
179
180 return ERROR_OK;
181 }
182
183 static int cortex_m3_endreset_event(struct target *target)
184 {
185 int i;
186 uint32_t dcb_demcr;
187 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
188 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
189 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
190 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
191
192 /* FIXME handling of DEMCR clobbers vector_catch config ... */
193 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
194 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
195
196 /* this register is used for emulated dcc channel */
197 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
198
199 /* Enable debug requests */
200 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
201 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
202 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
203
204 /* clear any interrupt masking */
205 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
206
207 /* Enable trace and DWT; trap hard and bus faults.
208 *
209 * REVISIT why trap those two? And why trash the vector_catch
210 * config, instead of preserving it? Catching HARDERR and BUSERR
211 * will interfere with code that handles those itself...
212 */
213 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
214
215 /* Monitor bus faults as such (instead of as generic HARDERR), but
216 * leave memory management and usage faults disabled.
217 *
218 * REVISIT setting BUSFAULTENA interferes with code which relies
219 * on the default setting. Why do it?
220 */
221 mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
222
223 /* Paranoia: evidently some (early?) chips don't preserve all the
224 * debug state (including FBP, DWT, etc) across reset...
225 */
226
227 /* Enable FPB */
228 target_write_u32(target, FP_CTRL, 3);
229 cortex_m3->fpb_enabled = 1;
230
231 /* Restore FPB registers */
232 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
233 {
234 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
235 }
236
237 /* Restore DWT registers */
238 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
239 {
240 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
241 dwt_list[i].comp);
242 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
243 dwt_list[i].mask);
244 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
245 dwt_list[i].function);
246 }
247 swjdp_transaction_endcheck(swjdp);
248
249 register_cache_invalidate(cortex_m3->armv7m.core_cache);
250
251 /* make sure we have latest dhcsr flags */
252 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
253
254 return ERROR_OK;
255 }
256
257 static int cortex_m3_examine_debug_reason(struct target *target)
258 {
259 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
260
261 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
262 /* only check the debug reason if we don't know it already */
263
264 if ((target->debug_reason != DBG_REASON_DBGRQ)
265 && (target->debug_reason != DBG_REASON_SINGLESTEP))
266 {
267 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
268 {
269 target->debug_reason = DBG_REASON_BREAKPOINT;
270 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
271 target->debug_reason = DBG_REASON_WPTANDBKPT;
272 }
273 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
274 target->debug_reason = DBG_REASON_WATCHPOINT;
275 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
276 target->debug_reason = DBG_REASON_BREAKPOINT;
277 else /* EXTERNAL, HALTED */
278 target->debug_reason = DBG_REASON_UNDEFINED;
279 }
280
281 return ERROR_OK;
282 }
283
284 static int cortex_m3_examine_exception_reason(struct target *target)
285 {
286 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
287 struct armv7m_common *armv7m = target_to_armv7m(target);
288 struct swjdp_common *swjdp = &armv7m->swjdp_info;
289
290 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
291 switch (armv7m->exception_number)
292 {
293 case 2: /* NMI */
294 break;
295 case 3: /* Hard Fault */
296 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
297 if (except_sr & 0x40000000)
298 {
299 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
300 }
301 break;
302 case 4: /* Memory Management */
303 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
304 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
305 break;
306 case 5: /* Bus Fault */
307 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
308 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
309 break;
310 case 6: /* Usage Fault */
311 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
312 break;
313 case 11: /* SVCall */
314 break;
315 case 12: /* Debug Monitor */
316 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
317 break;
318 case 14: /* PendSV */
319 break;
320 case 15: /* SysTick */
321 break;
322 default:
323 except_sr = 0;
324 break;
325 }
326 swjdp_transaction_endcheck(swjdp);
327 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
328 shcsr, except_sr, cfsr, except_ar);
329 return ERROR_OK;
330 }
331
332 static int cortex_m3_debug_entry(struct target *target)
333 {
334 int i;
335 uint32_t xPSR;
336 int retval;
337 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
338 struct armv7m_common *armv7m = &cortex_m3->armv7m;
339 struct swjdp_common *swjdp = &armv7m->swjdp_info;
340 struct reg *r;
341
342 LOG_DEBUG(" ");
343
344 cortex_m3_clear_halt(target);
345 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
346
347 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
348 return retval;
349
350 /* Examine target state and mode */
351 /* First load register acessible through core debug port*/
352 int num_regs = armv7m->core_cache->num_regs;
353
354 for (i = 0; i < num_regs; i++)
355 {
356 if (!armv7m->core_cache->reg_list[i].valid)
357 armv7m->read_core_reg(target, i);
358 }
359
360 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
361 xPSR = buf_get_u32(r->value, 0, 32);
362
363 #ifdef ARMV7_GDB_HACKS
364 /* FIXME this breaks on scan chains with more than one Cortex-M3.
365 * Instead, each CM3 should have its own dummy value...
366 */
367 /* copy real xpsr reg for gdb, setting thumb bit */
368 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
369 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
370 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
371 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
372 #endif
373
374 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
375 if (xPSR & 0xf00)
376 {
377 r->dirty = r->valid;
378 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
379 }
380
381 /* Are we in an exception handler */
382 if (xPSR & 0x1FF)
383 {
384 armv7m->core_mode = ARMV7M_MODE_HANDLER;
385 armv7m->exception_number = (xPSR & 0x1FF);
386 }
387 else
388 {
389 armv7m->core_mode = buf_get_u32(armv7m->core_cache
390 ->reg_list[ARMV7M_CONTROL].value, 0, 1);
391 armv7m->exception_number = 0;
392 }
393
394 if (armv7m->exception_number)
395 {
396 cortex_m3_examine_exception_reason(target);
397 }
398
399 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
400 armv7m_mode_strings[armv7m->core_mode],
401 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
402 target_state_name(target));
403
404 if (armv7m->post_debug_entry)
405 armv7m->post_debug_entry(target);
406
407 return ERROR_OK;
408 }
409
410 static int cortex_m3_poll(struct target *target)
411 {
412 int retval;
413 enum target_state prev_target_state = target->state;
414 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
415 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
416
417 /* Read from Debug Halting Control and Status Register */
418 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
419 if (retval != ERROR_OK)
420 {
421 target->state = TARGET_UNKNOWN;
422 return retval;
423 }
424
425 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
426 {
427 /* check if still in reset */
428 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
429
430 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
431 {
432 target->state = TARGET_RESET;
433 return ERROR_OK;
434 }
435 }
436
437 if (target->state == TARGET_RESET)
438 {
439 /* Cannot switch context while running so endreset is
440 * called with target->state == TARGET_RESET
441 */
442 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
443 cortex_m3->dcb_dhcsr);
444 cortex_m3_endreset_event(target);
445 target->state = TARGET_RUNNING;
446 prev_target_state = TARGET_RUNNING;
447 }
448
449 if (cortex_m3->dcb_dhcsr & S_HALT)
450 {
451 target->state = TARGET_HALTED;
452
453 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
454 {
455 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
456 return retval;
457
458 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
459 }
460 if (prev_target_state == TARGET_DEBUG_RUNNING)
461 {
462 LOG_DEBUG(" ");
463 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
464 return retval;
465
466 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
467 }
468 }
469
470 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
471 * How best to model low power modes?
472 */
473
474 if (target->state == TARGET_UNKNOWN)
475 {
476 /* check if processor is retiring instructions */
477 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
478 {
479 target->state = TARGET_RUNNING;
480 return ERROR_OK;
481 }
482 }
483
484 return ERROR_OK;
485 }
486
487 static int cortex_m3_halt(struct target *target)
488 {
489 LOG_DEBUG("target->state: %s",
490 target_state_name(target));
491
492 if (target->state == TARGET_HALTED)
493 {
494 LOG_DEBUG("target was already halted");
495 return ERROR_OK;
496 }
497
498 if (target->state == TARGET_UNKNOWN)
499 {
500 LOG_WARNING("target was in unknown state when halt was requested");
501 }
502
503 if (target->state == TARGET_RESET)
504 {
505 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
506 {
507 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
508 return ERROR_TARGET_FAILURE;
509 }
510 else
511 {
512 /* we came here in a reset_halt or reset_init sequence
513 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
514 */
515 target->debug_reason = DBG_REASON_DBGRQ;
516
517 return ERROR_OK;
518 }
519 }
520
521 /* Write to Debug Halting Control and Status Register */
522 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
523
524 target->debug_reason = DBG_REASON_DBGRQ;
525
526 return ERROR_OK;
527 }
528
529 static int cortex_m3_soft_reset_halt(struct target *target)
530 {
531 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
532 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
533 uint32_t dcb_dhcsr = 0;
534 int retval, timeout = 0;
535
536 /* Enter debug state on reset; see end_reset_event() */
537 mem_ap_write_u32(swjdp, DCB_DEMCR,
538 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
539
540 /* Request a core-only reset */
541 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
542 AIRCR_VECTKEY | AIRCR_VECTRESET);
543 target->state = TARGET_RESET;
544
545 /* registers are now invalid */
546 register_cache_invalidate(cortex_m3->armv7m.core_cache);
547
548 while (timeout < 100)
549 {
550 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
551 if (retval == ERROR_OK)
552 {
553 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
554 &cortex_m3->nvic_dfsr);
555 if ((dcb_dhcsr & S_HALT)
556 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
557 {
558 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
559 "DFSR 0x%08x",
560 (unsigned) dcb_dhcsr,
561 (unsigned) cortex_m3->nvic_dfsr);
562 cortex_m3_poll(target);
563 /* FIXME restore user's vector catch config */
564 return ERROR_OK;
565 }
566 else
567 LOG_DEBUG("waiting for system reset-halt, "
568 "DHCSR 0x%08x, %d ms",
569 (unsigned) dcb_dhcsr, timeout);
570 }
571 timeout++;
572 alive_sleep(1);
573 }
574
575 return ERROR_OK;
576 }
577
578 static void cortex_m3_enable_breakpoints(struct target *target)
579 {
580 struct breakpoint *breakpoint = target->breakpoints;
581
582 /* set any pending breakpoints */
583 while (breakpoint)
584 {
585 if (!breakpoint->set)
586 cortex_m3_set_breakpoint(target, breakpoint);
587 breakpoint = breakpoint->next;
588 }
589 }
590
591 static int cortex_m3_resume(struct target *target, int current,
592 uint32_t address, int handle_breakpoints, int debug_execution)
593 {
594 struct armv7m_common *armv7m = target_to_armv7m(target);
595 struct breakpoint *breakpoint = NULL;
596 uint32_t resume_pc;
597 struct reg *r;
598
599 if (target->state != TARGET_HALTED)
600 {
601 LOG_WARNING("target not halted");
602 return ERROR_TARGET_NOT_HALTED;
603 }
604
605 if (!debug_execution)
606 {
607 target_free_all_working_areas(target);
608 cortex_m3_enable_breakpoints(target);
609 cortex_m3_enable_watchpoints(target);
610 }
611
612 if (debug_execution)
613 {
614 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
615
616 /* Disable interrupts */
617 /* We disable interrupts in the PRIMASK register instead of
618 * masking with C_MASKINTS. This is probably the same issue
619 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
620 * in parallel with disabled interrupts can cause local faults
621 * to not be taken.
622 *
623 * REVISIT this clearly breaks non-debug execution, since the
624 * PRIMASK register state isn't saved/restored... workaround
625 * by never resuming app code after debug execution.
626 */
627 buf_set_u32(r->value, 0, 1, 1);
628 r->dirty = true;
629 r->valid = true;
630
631 /* Make sure we are in Thumb mode */
632 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
633 buf_set_u32(r->value, 24, 1, 1);
634 r->dirty = true;
635 r->valid = true;
636 }
637
638 /* current = 1: continue on current pc, otherwise continue at <address> */
639 r = armv7m->core_cache->reg_list + 15;
640 if (!current)
641 {
642 buf_set_u32(r->value, 0, 32, address);
643 r->dirty = true;
644 r->valid = true;
645 }
646
647 resume_pc = buf_get_u32(r->value, 0, 32);
648
649 armv7m_restore_context(target);
650
651 /* the front-end may request us not to handle breakpoints */
652 if (handle_breakpoints)
653 {
654 /* Single step past breakpoint at current address */
655 if ((breakpoint = breakpoint_find(target, resume_pc)))
656 {
657 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
658 breakpoint->address,
659 breakpoint->unique_id);
660 cortex_m3_unset_breakpoint(target, breakpoint);
661 cortex_m3_single_step_core(target);
662 cortex_m3_set_breakpoint(target, breakpoint);
663 }
664 }
665
666 /* Restart core */
667 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
668
669 target->debug_reason = DBG_REASON_NOTHALTED;
670
671 /* registers are now invalid */
672 register_cache_invalidate(armv7m->core_cache);
673
674 if (!debug_execution)
675 {
676 target->state = TARGET_RUNNING;
677 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
678 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
679 }
680 else
681 {
682 target->state = TARGET_DEBUG_RUNNING;
683 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
684 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
685 }
686
687 return ERROR_OK;
688 }
689
690 /* int irqstepcount = 0; */
691 static int cortex_m3_step(struct target *target, int current,
692 uint32_t address, int handle_breakpoints)
693 {
694 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
695 struct armv7m_common *armv7m = &cortex_m3->armv7m;
696 struct swjdp_common *swjdp = &armv7m->swjdp_info;
697 struct breakpoint *breakpoint = NULL;
698 struct reg *pc = armv7m->core_cache->reg_list + 15;
699
700 if (target->state != TARGET_HALTED)
701 {
702 LOG_WARNING("target not halted");
703 return ERROR_TARGET_NOT_HALTED;
704 }
705
706 /* current = 1: continue on current pc, otherwise continue at <address> */
707 if (!current)
708 buf_set_u32(pc->value, 0, 32, address);
709
710 /* the front-end may request us not to handle breakpoints */
711 if (handle_breakpoints) {
712 breakpoint = breakpoint_find(target,
713 buf_get_u32(pc->value, 0, 32));
714 if (breakpoint)
715 cortex_m3_unset_breakpoint(target, breakpoint);
716 }
717
718 target->debug_reason = DBG_REASON_SINGLESTEP;
719
720 armv7m_restore_context(target);
721
722 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
723
724 /* set step and clear halt */
725 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
726 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
727
728 /* registers are now invalid */
729 register_cache_invalidate(cortex_m3->armv7m.core_cache);
730
731 if (breakpoint)
732 cortex_m3_set_breakpoint(target, breakpoint);
733
734 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
735 " nvic_icsr = 0x%" PRIx32,
736 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
737
738 cortex_m3_debug_entry(target);
739 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
740
741 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
742 " nvic_icsr = 0x%" PRIx32,
743 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
744 return ERROR_OK;
745 }
746
747 static int cortex_m3_assert_reset(struct target *target)
748 {
749 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
750 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
751 int assert_srst = 1;
752
753 LOG_DEBUG("target->state: %s",
754 target_state_name(target));
755
756 enum reset_types jtag_reset_config = jtag_get_reset_config();
757
758 /*
759 * We can reset Cortex-M3 targets using just the NVIC without
760 * requiring SRST, getting a SoC reset (or a core-only reset)
761 * instead of a system reset.
762 */
763 if (!(jtag_reset_config & RESET_HAS_SRST))
764 assert_srst = 0;
765
766 /* Enable debug requests */
767 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
768 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
769 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
770
771 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
772
773 if (!target->reset_halt)
774 {
775 /* Set/Clear C_MASKINTS in a separate operation */
776 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
777 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
778 DBGKEY | C_DEBUGEN | C_HALT);
779
780 /* clear any debug flags before resuming */
781 cortex_m3_clear_halt(target);
782
783 /* clear C_HALT in dhcsr reg */
784 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
785
786 /* Enter debug state on reset, cf. end_reset_event() */
787 mem_ap_write_u32(swjdp, DCB_DEMCR,
788 TRCENA | VC_HARDERR | VC_BUSERR);
789 }
790 else
791 {
792 /* Enter debug state on reset, cf. end_reset_event() */
793 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
794 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
795 }
796
797 /*
798 * When nRST is asserted on most Stellaris devices, it clears some of
799 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
800 * and OpenOCD depends on those TRMs. So we won't use SRST on those
801 * chips. (Only power-on reset should affect debug state, beyond a
802 * few specified bits; not the chip's nRST input, wired to SRST.)
803 *
804 * REVISIT current errata specs don't seem to cover this issue.
805 * Do we have more details than this email?
806 * https://lists.berlios.de/pipermail
807 * /openocd-development/2008-August/003065.html
808 */
809 if (strcmp(target->variant, "lm3s") == 0)
810 {
811 /* Check for silicon revisions with the issue. */
812 uint32_t did0;
813
814 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
815 {
816 switch ((did0 >> 16) & 0xff)
817 {
818 case 0:
819 /* all Sandstorm suffer issue */
820 assert_srst = 0;
821 break;
822
823 case 1:
824 case 3:
825 /* Fury and DustDevil rev A have
826 * this nRST problem. It should
827 * be fixed in rev B silicon.
828 */
829 if (((did0 >> 8) & 0xff) == 0)
830 assert_srst = 0;
831 break;
832 case 4:
833 /* Tempest should be fine. */
834 break;
835 }
836 }
837 }
838
839 if (assert_srst)
840 {
841 /* default to asserting srst */
842 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
843 {
844 jtag_add_reset(1, 1);
845 }
846 else
847 {
848 jtag_add_reset(0, 1);
849 }
850 }
851 else
852 {
853 /* Use a standard Cortex-M3 software reset mechanism.
854 * SYSRESETREQ will reset SoC peripherals outside the
855 * core, like watchdog timers, if the SoC wires it up
856 * correctly. Else VECRESET can reset just the core.
857 */
858 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
859 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
860 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
861
862 {
863 /* I do not know why this is necessary, but it
864 * fixes strange effects (step/resume cause NMI
865 * after reset) on LM3S6918 -- Michael Schwingen
866 */
867 uint32_t tmp;
868 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
869 }
870 }
871
872 target->state = TARGET_RESET;
873 jtag_add_sleep(50000);
874
875 register_cache_invalidate(cortex_m3->armv7m.core_cache);
876
877 if (target->reset_halt)
878 {
879 int retval;
880 if ((retval = target_halt(target)) != ERROR_OK)
881 return retval;
882 }
883
884 return ERROR_OK;
885 }
886
887 static int cortex_m3_deassert_reset(struct target *target)
888 {
889 LOG_DEBUG("target->state: %s",
890 target_state_name(target));
891
892 /* deassert reset lines */
893 jtag_add_reset(0, 0);
894
895 return ERROR_OK;
896 }
897
898 static int
899 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
900 {
901 int retval;
902 int fp_num = 0;
903 uint32_t hilo;
904 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
905 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
906
907 if (breakpoint->set)
908 {
909 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
910 return ERROR_OK;
911 }
912
913 if (cortex_m3->auto_bp_type)
914 {
915 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
916 }
917
918 if (breakpoint->type == BKPT_HARD)
919 {
920 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
921 fp_num++;
922 if (fp_num >= cortex_m3->fp_num_code)
923 {
924 LOG_ERROR("Can not find free FPB Comparator!");
925 return ERROR_FAIL;
926 }
927 breakpoint->set = fp_num + 1;
928 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
929 comparator_list[fp_num].used = 1;
930 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
931 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
932 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
933 if (!cortex_m3->fpb_enabled)
934 {
935 LOG_DEBUG("FPB wasn't enabled, do it now");
936 target_write_u32(target, FP_CTRL, 3);
937 }
938 }
939 else if (breakpoint->type == BKPT_SOFT)
940 {
941 uint8_t code[4];
942
943 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
944 * semihosting; don't use that. Otherwise the BKPT
945 * parameter is arbitrary.
946 */
947 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
948 retval = target_read_memory(target,
949 breakpoint->address & 0xFFFFFFFE,
950 breakpoint->length, 1,
951 breakpoint->orig_instr);
952 if (retval != ERROR_OK)
953 return retval;
954 retval = target_write_memory(target,
955 breakpoint->address & 0xFFFFFFFE,
956 breakpoint->length, 1,
957 code);
958 if (retval != ERROR_OK)
959 return retval;
960 breakpoint->set = true;
961 }
962
963 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
964 breakpoint->unique_id,
965 (int)(breakpoint->type),
966 breakpoint->address,
967 breakpoint->length,
968 breakpoint->set);
969
970 return ERROR_OK;
971 }
972
973 static int
974 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
975 {
976 int retval;
977 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
978 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
979
980 if (!breakpoint->set)
981 {
982 LOG_WARNING("breakpoint not set");
983 return ERROR_OK;
984 }
985
986 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
987 breakpoint->unique_id,
988 (int)(breakpoint->type),
989 breakpoint->address,
990 breakpoint->length,
991 breakpoint->set);
992
993 if (breakpoint->type == BKPT_HARD)
994 {
995 int fp_num = breakpoint->set - 1;
996 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
997 {
998 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
999 return ERROR_OK;
1000 }
1001 comparator_list[fp_num].used = 0;
1002 comparator_list[fp_num].fpcr_value = 0;
1003 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1004 }
1005 else
1006 {
1007 /* restore original instruction (kept in target endianness) */
1008 if (breakpoint->length == 4)
1009 {
1010 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1011 {
1012 return retval;
1013 }
1014 }
1015 else
1016 {
1017 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1018 {
1019 return retval;
1020 }
1021 }
1022 }
1023 breakpoint->set = false;
1024
1025 return ERROR_OK;
1026 }
1027
1028 static int
1029 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1030 {
1031 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1032
1033 if (cortex_m3->auto_bp_type)
1034 {
1035 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1036 #ifdef ARMV7_GDB_HACKS
1037 if (breakpoint->length != 2) {
1038 /* XXX Hack: Replace all breakpoints with length != 2 with
1039 * a hardware breakpoint. */
1040 breakpoint->type = BKPT_HARD;
1041 breakpoint->length = 2;
1042 }
1043 #endif
1044 }
1045
1046 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1047 {
1048 LOG_INFO("flash patch comparator requested outside code memory region");
1049 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1050 }
1051
1052 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1053 {
1054 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1055 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1056 }
1057
1058 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1059 {
1060 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1061 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1062 }
1063
1064 if ((breakpoint->length != 2))
1065 {
1066 LOG_INFO("only breakpoints of two bytes length supported");
1067 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1068 }
1069
1070 if (breakpoint->type == BKPT_HARD)
1071 cortex_m3->fp_code_available--;
1072 cortex_m3_set_breakpoint(target, breakpoint);
1073
1074 return ERROR_OK;
1075 }
1076
1077 static int
1078 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1079 {
1080 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1081
1082 /* REVISIT why check? FBP can be updated with core running ... */
1083 if (target->state != TARGET_HALTED)
1084 {
1085 LOG_WARNING("target not halted");
1086 return ERROR_TARGET_NOT_HALTED;
1087 }
1088
1089 if (cortex_m3->auto_bp_type)
1090 {
1091 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1092 }
1093
1094 if (breakpoint->set)
1095 {
1096 cortex_m3_unset_breakpoint(target, breakpoint);
1097 }
1098
1099 if (breakpoint->type == BKPT_HARD)
1100 cortex_m3->fp_code_available++;
1101
1102 return ERROR_OK;
1103 }
1104
1105 static int
1106 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1107 {
1108 int dwt_num = 0;
1109 uint32_t mask, temp;
1110 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1111
1112 /* watchpoint params were validated earlier */
1113 mask = 0;
1114 temp = watchpoint->length;
1115 while (temp) {
1116 temp >>= 1;
1117 mask++;
1118 }
1119 mask--;
1120
1121 /* REVISIT Don't fully trust these "not used" records ... users
1122 * may set up breakpoints by hand, e.g. dual-address data value
1123 * watchpoint using comparator #1; comparator #0 matching cycle
1124 * count; send data trace info through ITM and TPIU; etc
1125 */
1126 struct cortex_m3_dwt_comparator *comparator;
1127
1128 for (comparator = cortex_m3->dwt_comparator_list;
1129 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1130 comparator++, dwt_num++)
1131 continue;
1132 if (dwt_num >= cortex_m3->dwt_num_comp)
1133 {
1134 LOG_ERROR("Can not find free DWT Comparator");
1135 return ERROR_FAIL;
1136 }
1137 comparator->used = 1;
1138 watchpoint->set = dwt_num + 1;
1139
1140 comparator->comp = watchpoint->address;
1141 target_write_u32(target, comparator->dwt_comparator_address + 0,
1142 comparator->comp);
1143
1144 comparator->mask = mask;
1145 target_write_u32(target, comparator->dwt_comparator_address + 4,
1146 comparator->mask);
1147
1148 switch (watchpoint->rw) {
1149 case WPT_READ:
1150 comparator->function = 5;
1151 break;
1152 case WPT_WRITE:
1153 comparator->function = 6;
1154 break;
1155 case WPT_ACCESS:
1156 comparator->function = 7;
1157 break;
1158 }
1159 target_write_u32(target, comparator->dwt_comparator_address + 8,
1160 comparator->function);
1161
1162 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1163 watchpoint->unique_id, dwt_num,
1164 (unsigned) comparator->comp,
1165 (unsigned) comparator->mask,
1166 (unsigned) comparator->function);
1167 return ERROR_OK;
1168 }
1169
1170 static int
1171 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1172 {
1173 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1174 struct cortex_m3_dwt_comparator *comparator;
1175 int dwt_num;
1176
1177 if (!watchpoint->set)
1178 {
1179 LOG_WARNING("watchpoint (wpid: %d) not set",
1180 watchpoint->unique_id);
1181 return ERROR_OK;
1182 }
1183
1184 dwt_num = watchpoint->set - 1;
1185
1186 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1187 watchpoint->unique_id, dwt_num,
1188 (unsigned) watchpoint->address);
1189
1190 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1191 {
1192 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1193 return ERROR_OK;
1194 }
1195
1196 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1197 comparator->used = 0;
1198 comparator->function = 0;
1199 target_write_u32(target, comparator->dwt_comparator_address + 8,
1200 comparator->function);
1201
1202 watchpoint->set = false;
1203
1204 return ERROR_OK;
1205 }
1206
1207 static int
1208 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1209 {
1210 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1211
1212 if (cortex_m3->dwt_comp_available < 1)
1213 {
1214 LOG_DEBUG("no comparators?");
1215 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1216 }
1217
1218 /* hardware doesn't support data value masking */
1219 if (watchpoint->mask != ~(uint32_t)0) {
1220 LOG_DEBUG("watchpoint value masks not supported");
1221 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1222 }
1223
1224 /* hardware allows address masks of up to 32K */
1225 unsigned mask;
1226
1227 for (mask = 0; mask < 16; mask++) {
1228 if ((1u << mask) == watchpoint->length)
1229 break;
1230 }
1231 if (mask == 16) {
1232 LOG_DEBUG("unsupported watchpoint length");
1233 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1234 }
1235 if (watchpoint->address & ((1 << mask) - 1)) {
1236 LOG_DEBUG("watchpoint address is unaligned");
1237 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1238 }
1239
1240 /* Caller doesn't seem to be able to describe watching for data
1241 * values of zero; that flags "no value".
1242 *
1243 * REVISIT This DWT may well be able to watch for specific data
1244 * values. Requires comparator #1 to set DATAVMATCH and match
1245 * the data, and another comparator (DATAVADDR0) matching addr.
1246 */
1247 if (watchpoint->value) {
1248 LOG_DEBUG("data value watchpoint not YET supported");
1249 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1250 }
1251
1252 cortex_m3->dwt_comp_available--;
1253 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1254
1255 return ERROR_OK;
1256 }
1257
1258 static int
1259 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1260 {
1261 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1262
1263 /* REVISIT why check? DWT can be updated with core running ... */
1264 if (target->state != TARGET_HALTED)
1265 {
1266 LOG_WARNING("target not halted");
1267 return ERROR_TARGET_NOT_HALTED;
1268 }
1269
1270 if (watchpoint->set)
1271 {
1272 cortex_m3_unset_watchpoint(target, watchpoint);
1273 }
1274
1275 cortex_m3->dwt_comp_available++;
1276 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1277
1278 return ERROR_OK;
1279 }
1280
1281 static void cortex_m3_enable_watchpoints(struct target *target)
1282 {
1283 struct watchpoint *watchpoint = target->watchpoints;
1284
1285 /* set any pending watchpoints */
1286 while (watchpoint)
1287 {
1288 if (!watchpoint->set)
1289 cortex_m3_set_watchpoint(target, watchpoint);
1290 watchpoint = watchpoint->next;
1291 }
1292 }
1293
1294 static int cortex_m3_load_core_reg_u32(struct target *target,
1295 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1296 {
1297 int retval;
1298 struct armv7m_common *armv7m = target_to_armv7m(target);
1299 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1300
1301 /* NOTE: we "know" here that the register identifiers used
1302 * in the v7m header match the Cortex-M3 Debug Core Register
1303 * Selector values for R0..R15, xPSR, MSP, and PSP.
1304 */
1305 switch (num) {
1306 case 0 ... 18:
1307 /* read a normal core register */
1308 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1309
1310 if (retval != ERROR_OK)
1311 {
1312 LOG_ERROR("JTAG failure %i",retval);
1313 return ERROR_JTAG_DEVICE_ERROR;
1314 }
1315 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1316 break;
1317
1318 case ARMV7M_PRIMASK:
1319 case ARMV7M_BASEPRI:
1320 case ARMV7M_FAULTMASK:
1321 case ARMV7M_CONTROL:
1322 /* Cortex-M3 packages these four registers as bitfields
1323 * in one Debug Core register. So say r0 and r2 docs;
1324 * it was removed from r1 docs, but still works.
1325 */
1326 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1327
1328 switch (num)
1329 {
1330 case ARMV7M_PRIMASK:
1331 *value = buf_get_u32((uint8_t*)value, 0, 1);
1332 break;
1333
1334 case ARMV7M_BASEPRI:
1335 *value = buf_get_u32((uint8_t*)value, 8, 8);
1336 break;
1337
1338 case ARMV7M_FAULTMASK:
1339 *value = buf_get_u32((uint8_t*)value, 16, 1);
1340 break;
1341
1342 case ARMV7M_CONTROL:
1343 *value = buf_get_u32((uint8_t*)value, 24, 2);
1344 break;
1345 }
1346
1347 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1348 break;
1349
1350 default:
1351 return ERROR_INVALID_ARGUMENTS;
1352 }
1353
1354 return ERROR_OK;
1355 }
1356
1357 static int cortex_m3_store_core_reg_u32(struct target *target,
1358 enum armv7m_regtype type, uint32_t num, uint32_t value)
1359 {
1360 int retval;
1361 uint32_t reg;
1362 struct armv7m_common *armv7m = target_to_armv7m(target);
1363 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1364
1365 #ifdef ARMV7_GDB_HACKS
1366 /* If the LR register is being modified, make sure it will put us
1367 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1368 * hack to deal with the fact that gdb will sometimes "forge"
1369 * return addresses, and doesn't set the LSB correctly (i.e., when
1370 * printing expressions containing function calls, it sets LR = 0.)
1371 * Valid exception return codes have bit 0 set too.
1372 */
1373 if (num == ARMV7M_R14)
1374 value |= 0x01;
1375 #endif
1376
1377 /* NOTE: we "know" here that the register identifiers used
1378 * in the v7m header match the Cortex-M3 Debug Core Register
1379 * Selector values for R0..R15, xPSR, MSP, and PSP.
1380 */
1381 switch (num) {
1382 case 0 ... 18:
1383 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1384 if (retval != ERROR_OK)
1385 {
1386 struct reg *r;
1387
1388 LOG_ERROR("JTAG failure %i", retval);
1389 r = armv7m->core_cache->reg_list + num;
1390 r->dirty = r->valid;
1391 return ERROR_JTAG_DEVICE_ERROR;
1392 }
1393 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1394 break;
1395
1396 case ARMV7M_PRIMASK:
1397 case ARMV7M_BASEPRI:
1398 case ARMV7M_FAULTMASK:
1399 case ARMV7M_CONTROL:
1400 /* Cortex-M3 packages these four registers as bitfields
1401 * in one Debug Core register. So say r0 and r2 docs;
1402 * it was removed from r1 docs, but still works.
1403 */
1404 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1405
1406 switch (num)
1407 {
1408 case ARMV7M_PRIMASK:
1409 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1410 break;
1411
1412 case ARMV7M_BASEPRI:
1413 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1414 break;
1415
1416 case ARMV7M_FAULTMASK:
1417 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1418 break;
1419
1420 case ARMV7M_CONTROL:
1421 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1422 break;
1423 }
1424
1425 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1426
1427 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1428 break;
1429
1430 default:
1431 return ERROR_INVALID_ARGUMENTS;
1432 }
1433
1434 return ERROR_OK;
1435 }
1436
1437 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1438 uint32_t size, uint32_t count, uint8_t *buffer)
1439 {
1440 struct armv7m_common *armv7m = target_to_armv7m(target);
1441 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1442 int retval = ERROR_INVALID_ARGUMENTS;
1443
1444 /* cortex_m3 handles unaligned memory access */
1445 if (count && buffer) {
1446 switch (size) {
1447 case 4:
1448 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1449 break;
1450 case 2:
1451 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1452 break;
1453 case 1:
1454 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1455 break;
1456 }
1457 }
1458
1459 return retval;
1460 }
1461
1462 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1463 uint32_t size, uint32_t count, uint8_t *buffer)
1464 {
1465 struct armv7m_common *armv7m = target_to_armv7m(target);
1466 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1467 int retval = ERROR_INVALID_ARGUMENTS;
1468
1469 if (count && buffer) {
1470 switch (size) {
1471 case 4:
1472 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1473 break;
1474 case 2:
1475 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1476 break;
1477 case 1:
1478 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1479 break;
1480 }
1481 }
1482
1483 return retval;
1484 }
1485
1486 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1487 uint32_t count, uint8_t *buffer)
1488 {
1489 return cortex_m3_write_memory(target, address, 4, count, buffer);
1490 }
1491
1492 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1493 struct target *target)
1494 {
1495 armv7m_build_reg_cache(target);
1496 return ERROR_OK;
1497 }
1498
1499 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1500 * on r/w if the core is not running, and clear on resume or reset ... or
1501 * at least, in a post_restore_context() method.
1502 */
1503
1504 struct dwt_reg_state {
1505 struct target *target;
1506 uint32_t addr;
1507 uint32_t value; /* scratch/cache */
1508 };
1509
1510 static int cortex_m3_dwt_get_reg(struct reg *reg)
1511 {
1512 struct dwt_reg_state *state = reg->arch_info;
1513
1514 return target_read_u32(state->target, state->addr, &state->value);
1515 }
1516
1517 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1518 {
1519 struct dwt_reg_state *state = reg->arch_info;
1520
1521 return target_write_u32(state->target, state->addr,
1522 buf_get_u32(buf, 0, reg->size));
1523 }
1524
1525 struct dwt_reg {
1526 uint32_t addr;
1527 char *name;
1528 unsigned size;
1529 };
1530
1531 static struct dwt_reg dwt_base_regs[] = {
1532 { DWT_CTRL, "dwt_ctrl", 32, },
1533 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1534 * increments while the core is asleep.
1535 */
1536 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1537 /* plus some 8 bit counters, useful for profiling with TPIU */
1538 };
1539
1540 static struct dwt_reg dwt_comp[] = {
1541 #define DWT_COMPARATOR(i) \
1542 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1543 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1544 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1545 DWT_COMPARATOR(0),
1546 DWT_COMPARATOR(1),
1547 DWT_COMPARATOR(2),
1548 DWT_COMPARATOR(3),
1549 #undef DWT_COMPARATOR
1550 };
1551
1552 static const struct reg_arch_type dwt_reg_type = {
1553 .get = cortex_m3_dwt_get_reg,
1554 .set = cortex_m3_dwt_set_reg,
1555 };
1556
1557 static void
1558 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1559 {
1560 struct dwt_reg_state *state;
1561
1562 state = calloc(1, sizeof *state);
1563 if (!state)
1564 return;
1565 state->addr = d->addr;
1566 state->target = t;
1567
1568 r->name = d->name;
1569 r->size = d->size;
1570 r->value = &state->value;
1571 r->arch_info = state;
1572 r->type = &dwt_reg_type;
1573 }
1574
1575 static void
1576 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1577 {
1578 uint32_t dwtcr;
1579 struct reg_cache *cache;
1580 struct cortex_m3_dwt_comparator *comparator;
1581 int reg, i;
1582
1583 target_read_u32(target, DWT_CTRL, &dwtcr);
1584 if (!dwtcr) {
1585 LOG_DEBUG("no DWT");
1586 return;
1587 }
1588
1589 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1590 cm3->dwt_comp_available = cm3->dwt_num_comp;
1591 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1592 sizeof(struct cortex_m3_dwt_comparator));
1593 if (!cm3->dwt_comparator_list) {
1594 fail0:
1595 cm3->dwt_num_comp = 0;
1596 LOG_ERROR("out of mem");
1597 return;
1598 }
1599
1600 cache = calloc(1, sizeof *cache);
1601 if (!cache) {
1602 fail1:
1603 free(cm3->dwt_comparator_list);
1604 goto fail0;
1605 }
1606 cache->name = "cortex-m3 dwt registers";
1607 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1608 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1609 if (!cache->reg_list) {
1610 free(cache);
1611 goto fail1;
1612 }
1613
1614 for (reg = 0; reg < 2; reg++)
1615 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1616 dwt_base_regs + reg);
1617
1618 comparator = cm3->dwt_comparator_list;
1619 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1620 int j;
1621
1622 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1623 for (j = 0; j < 3; j++, reg++)
1624 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1625 dwt_comp + 3 * i + j);
1626 }
1627
1628 *register_get_last_cache_p(&target->reg_cache) = cache;
1629 cm3->dwt_cache = cache;
1630
1631 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1632 dwtcr, cm3->dwt_num_comp,
1633 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1634
1635 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1636 * implement single-address data value watchpoints ... so we
1637 * won't need to check it later, when asked to set one up.
1638 */
1639 }
1640
1641 static int cortex_m3_examine(struct target *target)
1642 {
1643 int retval;
1644 uint32_t cpuid, fpcr;
1645 int i;
1646 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1647 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1648
1649 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1650 return retval;
1651
1652 if (!target_was_examined(target))
1653 {
1654 target_set_examined(target);
1655
1656 /* Read from Device Identification Registers */
1657 retval = target_read_u32(target, CPUID, &cpuid);
1658 if (retval != ERROR_OK)
1659 return retval;
1660
1661 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1662 LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
1663 (cpuid >> 20) & 0xf, (cpuid >> 0) & 0xf);
1664 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1665
1666 /* NOTE: FPB and DWT are both optional. */
1667
1668 /* Setup FPB */
1669 target_read_u32(target, FP_CTRL, &fpcr);
1670 cortex_m3->auto_bp_type = 1;
1671 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1672 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1673 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1674 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1675 cortex_m3->fpb_enabled = fpcr & 1;
1676 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1677 {
1678 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1679 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1680 }
1681 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1682
1683 /* Setup DWT */
1684 cortex_m3_dwt_setup(cortex_m3, target);
1685
1686 /* These hardware breakpoints only work for code in flash! */
1687 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1688 target_name(target),
1689 cortex_m3->fp_num_code,
1690 cortex_m3->dwt_num_comp);
1691 }
1692
1693 return ERROR_OK;
1694 }
1695
1696 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1697 {
1698 uint16_t dcrdr;
1699
1700 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1701 *ctrl = (uint8_t)dcrdr;
1702 *value = (uint8_t)(dcrdr >> 8);
1703
1704 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1705
1706 /* write ack back to software dcc register
1707 * signify we have read data */
1708 if (dcrdr & (1 << 0))
1709 {
1710 dcrdr = 0;
1711 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1712 }
1713
1714 return ERROR_OK;
1715 }
1716
1717 static int cortex_m3_target_request_data(struct target *target,
1718 uint32_t size, uint8_t *buffer)
1719 {
1720 struct armv7m_common *armv7m = target_to_armv7m(target);
1721 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1722 uint8_t data;
1723 uint8_t ctrl;
1724 uint32_t i;
1725
1726 for (i = 0; i < (size * 4); i++)
1727 {
1728 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1729 buffer[i] = data;
1730 }
1731
1732 return ERROR_OK;
1733 }
1734
1735 static int cortex_m3_handle_target_request(void *priv)
1736 {
1737 struct target *target = priv;
1738 if (!target_was_examined(target))
1739 return ERROR_OK;
1740 struct armv7m_common *armv7m = target_to_armv7m(target);
1741 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1742
1743 if (!target->dbg_msg_enabled)
1744 return ERROR_OK;
1745
1746 if (target->state == TARGET_RUNNING)
1747 {
1748 uint8_t data;
1749 uint8_t ctrl;
1750
1751 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1752
1753 /* check if we have data */
1754 if (ctrl & (1 << 0))
1755 {
1756 uint32_t request;
1757
1758 /* we assume target is quick enough */
1759 request = data;
1760 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1761 request |= (data << 8);
1762 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1763 request |= (data << 16);
1764 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1765 request |= (data << 24);
1766 target_request(target, request);
1767 }
1768 }
1769
1770 return ERROR_OK;
1771 }
1772
1773 static int cortex_m3_init_arch_info(struct target *target,
1774 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1775 {
1776 int retval;
1777 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1778
1779 armv7m_init_arch_info(target, armv7m);
1780
1781 /* prepare JTAG information for the new target */
1782 cortex_m3->jtag_info.tap = tap;
1783 cortex_m3->jtag_info.scann_size = 4;
1784
1785 armv7m->swjdp_info.dp_select_value = -1;
1786 armv7m->swjdp_info.ap_csw_value = -1;
1787 armv7m->swjdp_info.ap_tar_value = -1;
1788 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1789 armv7m->swjdp_info.memaccess_tck = 8;
1790 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1791
1792 /* register arch-specific functions */
1793 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1794
1795 armv7m->post_debug_entry = NULL;
1796
1797 armv7m->pre_restore_context = NULL;
1798 armv7m->post_restore_context = NULL;
1799
1800 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1801 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1802
1803 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1804
1805 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1806 {
1807 return retval;
1808 }
1809
1810 return ERROR_OK;
1811 }
1812
1813 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1814 {
1815 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1816
1817 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1818 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1819
1820 return ERROR_OK;
1821 }
1822
1823 /*--------------------------------------------------------------------------*/
1824
1825 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1826 struct cortex_m3_common *cm3)
1827 {
1828 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1829 command_print(cmd_ctx, "target is not a Cortex-M3");
1830 return ERROR_TARGET_INVALID;
1831 }
1832 return ERROR_OK;
1833 }
1834
1835 /*
1836 * Only stuff below this line should need to verify that its target
1837 * is a Cortex-M3. Everything else should have indirected through the
1838 * cortexm3_target structure, which is only used with CM3 targets.
1839 */
1840
1841 /*
1842 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1843 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1844 * that *only* Thumb2 disassembly matters. There are also some small
1845 * additions to Thumb2 that are specific to ARMv7-M.
1846 */
1847 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1848 {
1849 int retval;
1850 struct target *target = get_current_target(CMD_CTX);
1851 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1852 uint32_t address;
1853 unsigned long count = 1;
1854 struct arm_instruction cur_instruction;
1855
1856 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1857 if (retval != ERROR_OK)
1858 return retval;
1859
1860 errno = 0;
1861 switch (CMD_ARGC) {
1862 case 2:
1863 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1864 /* FALL THROUGH */
1865 case 1:
1866 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1867 break;
1868 default:
1869 command_print(CMD_CTX,
1870 "usage: cortex_m3 disassemble <address> [<count>]");
1871 return ERROR_OK;
1872 }
1873
1874 while (count--) {
1875 retval = thumb2_opcode(target, address, &cur_instruction);
1876 if (retval != ERROR_OK)
1877 return retval;
1878 command_print(CMD_CTX, "%s", cur_instruction.text);
1879 address += cur_instruction.instruction_size;
1880 }
1881
1882 return ERROR_OK;
1883 }
1884
1885 static const struct {
1886 char name[10];
1887 unsigned mask;
1888 } vec_ids[] = {
1889 { "hard_err", VC_HARDERR, },
1890 { "int_err", VC_INTERR, },
1891 { "bus_err", VC_BUSERR, },
1892 { "state_err", VC_STATERR, },
1893 { "chk_err", VC_CHKERR, },
1894 { "nocp_err", VC_NOCPERR, },
1895 { "mm_err", VC_MMERR, },
1896 { "reset", VC_CORERESET, },
1897 };
1898
1899 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1900 {
1901 struct target *target = get_current_target(CMD_CTX);
1902 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1903 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1904 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1905 uint32_t demcr = 0;
1906 int retval;
1907
1908 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1909 if (retval != ERROR_OK)
1910 return retval;
1911
1912 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1913
1914 if (CMD_ARGC > 0) {
1915 unsigned catch = 0;
1916
1917 if (CMD_ARGC == 1) {
1918 if (strcmp(CMD_ARGV[0], "all") == 0) {
1919 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1920 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1921 | VC_MMERR | VC_CORERESET;
1922 goto write;
1923 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1924 goto write;
1925 }
1926 }
1927 while (CMD_ARGC-- > 0) {
1928 unsigned i;
1929 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1930 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1931 continue;
1932 catch |= vec_ids[i].mask;
1933 break;
1934 }
1935 if (i == ARRAY_SIZE(vec_ids)) {
1936 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1937 return ERROR_INVALID_ARGUMENTS;
1938 }
1939 }
1940 write:
1941 demcr &= ~0xffff;
1942 demcr |= catch;
1943
1944 /* write, but don't assume it stuck */
1945 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1946 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1947 }
1948
1949 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1950 {
1951 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1952 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1953 }
1954
1955 return ERROR_OK;
1956 }
1957
1958 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1959 {
1960 struct target *target = get_current_target(CMD_CTX);
1961 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1962 int retval;
1963
1964 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1965 if (retval != ERROR_OK)
1966 return retval;
1967
1968 if (target->state != TARGET_HALTED)
1969 {
1970 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1971 return ERROR_OK;
1972 }
1973
1974 if (CMD_ARGC > 0)
1975 {
1976 bool enable;
1977 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
1978 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
1979 uint32_t mask_off = enable ? 0 : C_MASKINTS;
1980 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
1981 }
1982
1983 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1984 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1985
1986 return ERROR_OK;
1987 }
1988
1989 static const struct command_registration cortex_m3_exec_command_handlers[] = {
1990 {
1991 .name = "disassemble",
1992 .handler = handle_cortex_m3_disassemble_command,
1993 .mode = COMMAND_EXEC,
1994 .help = "disassemble Thumb2 instructions",
1995 .usage = "address [count]",
1996 },
1997 {
1998 .name = "maskisr",
1999 .handler = handle_cortex_m3_mask_interrupts_command,
2000 .mode = COMMAND_EXEC,
2001 .help = "mask cortex_m3 interrupts",
2002 .usage = "['on'|'off']",
2003 },
2004 {
2005 .name = "vector_catch",
2006 .handler = handle_cortex_m3_vector_catch_command,
2007 .mode = COMMAND_EXEC,
2008 .help = "configure hardware vectors to trigger debug entry",
2009 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2010 },
2011 COMMAND_REGISTRATION_DONE
2012 };
2013 static const struct command_registration cortex_m3_command_handlers[] = {
2014 {
2015 .chain = armv7m_command_handlers,
2016 },
2017 {
2018 .name = "cortex_m3",
2019 .mode = COMMAND_EXEC,
2020 .help = "Cortex-M3 command group",
2021 .chain = cortex_m3_exec_command_handlers,
2022 },
2023 COMMAND_REGISTRATION_DONE
2024 };
2025
2026 struct target_type cortexm3_target =
2027 {
2028 .name = "cortex_m3",
2029
2030 .poll = cortex_m3_poll,
2031 .arch_state = armv7m_arch_state,
2032
2033 .target_request_data = cortex_m3_target_request_data,
2034
2035 .halt = cortex_m3_halt,
2036 .resume = cortex_m3_resume,
2037 .step = cortex_m3_step,
2038
2039 .assert_reset = cortex_m3_assert_reset,
2040 .deassert_reset = cortex_m3_deassert_reset,
2041 .soft_reset_halt = cortex_m3_soft_reset_halt,
2042
2043 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2044
2045 .read_memory = cortex_m3_read_memory,
2046 .write_memory = cortex_m3_write_memory,
2047 .bulk_write_memory = cortex_m3_bulk_write_memory,
2048 .checksum_memory = armv7m_checksum_memory,
2049 .blank_check_memory = armv7m_blank_check_memory,
2050
2051 .run_algorithm = armv7m_run_algorithm,
2052
2053 .add_breakpoint = cortex_m3_add_breakpoint,
2054 .remove_breakpoint = cortex_m3_remove_breakpoint,
2055 .add_watchpoint = cortex_m3_add_watchpoint,
2056 .remove_watchpoint = cortex_m3_remove_watchpoint,
2057
2058 .commands = cortex_m3_command_handlers,
2059 .target_create = cortex_m3_target_create,
2060 .init_target = cortex_m3_init_target,
2061 .examine = cortex_m3_examine,
2062 };
Luca's development patches