1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
20 /* SPEAr Serial Memory Interface (SMI) controller is a SPI bus controller
21 * specifically designed for SPI memories.
22 * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
23 * Two working modes are available:
24 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
26 * - HW mode: the SPI but is under SMI control. Memory content is directly
27 * accessible in CPU memory space. CPU can read, write and execute memory
31 * To have flash memory mapped in CPU memory space, the SMI controller
32 * have to be in "HW mode". This requires following constraints:
33 * 1) The command "reset init" have to initialize SMI controller and put
35 * 2) every command in this file have to return to prompt in HW mode. */
42 #include <jtag/jtag.h>
43 #include <helper/time_support.h>
45 #define JTAG_ID_3XX_6XX (0x07926041)
47 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
48 #define _SMI_READ_REG(a) \
53 __a = target_read_u32(target, io_base + (a), &__v); \
54 if (__a != ERROR_OK) \
59 #define SMI_WRITE_REG(a,v) \
63 __r = target_write_u32(target, io_base + (a), (v)); \
64 if (__r != ERROR_OK) \
68 #define SMI_POLL_TFF(timeout) \
72 __r = poll_tff(target, io_base, timeout); \
73 if (__r != ERROR_OK) \
77 #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
78 SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
79 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
80 (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
81 #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
82 SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
83 #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
85 #define SMI_BANK_SIZE (0x01000000)
87 #define SMI_BASE_3XX_6XX (0xf8000000)
88 #define SMI_CFGREG_3XX_6XX (0xfc000000)
90 /* #define SMI_BASE_13XX (0xe6000000) */
91 /* #define SMI_CFGREG_13XX (0xea000000) */
93 #define SMI_CR1 (0x00) /* Control register 1 */
94 #define SMI_CR2 (0x04) /* Control register 2 */
95 #define SMI_SR (0x08) /* Status register */
96 #define SMI_TR (0x0c) /* TX */
97 #define SMI_RR (0x10) /* RX */
99 /* fields in SMI_CR1 */
100 #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
101 #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
103 /* fields in SMI_CR2 */
104 #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
105 #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
106 #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
107 #define SMI_SEND 0x00000080 /* Send data */
108 #define SMI_RSR 0x00000400 /* reads status reg */
109 #define SMI_WE 0x00000800 /* Write Enable */
110 #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
111 #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
112 #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
113 #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
115 /* fields in SMI_SR */
116 #define SMI_WIP_BIT 0x00000001 /* WIP Bit of SPI SR on SMI SR */
117 #define SMI_WEL_BIT 0x00000002 /* WEL Bit of SPI SR on SMI SR */
118 #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
121 #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
124 #define SMI_CMD_TIMEOUT (100)
125 #define SMI_PROBE_TIMEOUT (100)
126 #define SMI_MAX_TIMEOUT (3000)
128 struct spearsmi_flash_bank
133 struct flash_device
*dev
;
136 /* data structure to maintain flash ids from different vendors */
137 struct flash_device
{
142 unsigned long sectorsize
;
143 unsigned long size_in_bytes
;
146 #define FLASH_ID(n, es, id, psize, ssize, size) \
152 .sectorsize = ssize, \
153 .size_in_bytes = size \
156 /* List below is taken from Linux driver. It is not exhaustive of all the
157 * possible SPI memories, nor exclusive for SMI. Could be shared with
158 * other SPI drivers. */
159 static struct flash_device flash_devices
[] = {
160 /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
161 FLASH_ID("st m25p05", 0xd8, 0x00102020, 0x80, 0x8000, 0x10000),
162 FLASH_ID("st m25p10", 0xd8, 0x00112020, 0x80, 0x8000, 0x20000),
163 FLASH_ID("st m25p20", 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
164 FLASH_ID("st m25p40", 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
165 FLASH_ID("st m25p80", 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
166 FLASH_ID("st m25p16", 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
167 FLASH_ID("st m25p32", 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
168 FLASH_ID("st m25p64", 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
169 FLASH_ID("st m25p128", 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
170 FLASH_ID("st m45pe10", 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
171 FLASH_ID("st m45pe20", 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
172 FLASH_ID("st m45pe40", 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
173 FLASH_ID("st m45pe80", 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
174 FLASH_ID("sp s25fl004", 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
175 FLASH_ID("sp s25fl008", 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
176 FLASH_ID("sp s25fl016", 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
177 FLASH_ID("sp s25fl032", 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
178 FLASH_ID("sp s25fl064", 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
179 FLASH_ID("atmel 25f512", 0x52, 0x0065001f, 0x80, 0x8000, 0x10000),
180 FLASH_ID("atmel 25f1024", 0x52, 0x0060001f, 0x100, 0x8000, 0x20000),
181 FLASH_ID("atmel 25f2048", 0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
182 FLASH_ID("atmel 25f4096", 0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
183 FLASH_ID("atmel 25fs040", 0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
184 FLASH_ID("mac 25l512", 0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
185 FLASH_ID("mac 25l1005", 0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
186 FLASH_ID("mac 25l2005", 0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
187 FLASH_ID("mac 25l4005", 0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
188 FLASH_ID("mac 25l8005", 0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
189 FLASH_ID("mac 25l1605", 0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
190 FLASH_ID("mac 25l3205", 0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
191 FLASH_ID("mac 25l6405", 0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
192 FLASH_ID(NULL
, 0, 0, 0, 0, 0)
195 FLASH_BANK_COMMAND_HANDLER(spearsmi_flash_bank_command
)
197 struct spearsmi_flash_bank
*spearsmi_info
;
199 LOG_DEBUG(__FUNCTION__
);
203 LOG_WARNING("incomplete flash_bank spearsmi configuration");
204 return ERROR_FLASH_BANK_INVALID
;
207 spearsmi_info
= malloc(sizeof(struct spearsmi_flash_bank
));
208 if (spearsmi_info
== NULL
)
210 LOG_ERROR("not enough memory");
214 bank
->driver_priv
= spearsmi_info
;
215 spearsmi_info
->probed
= 0;
220 /* Poll transmit finished flag */
222 static int poll_tff(struct target
*target
, uint32_t io_base
, int timeout
)
226 if (SMI_READ_REG(SMI_SR
) & SMI_TFF
)
229 endtime
= timeval_ms() + timeout
;
232 if (SMI_READ_REG(SMI_SR
) & SMI_TFF
)
234 } while (timeval_ms() < endtime
);
236 LOG_ERROR("Timeout while polling TFF");
237 return ERROR_FLASH_OPERATION_FAILED
;
240 /* Read the status register of the external SPI flash chip.
241 * The operation is triggered by setting SMI_RSR bit.
242 * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
243 static int read_status_reg(struct flash_bank
*bank
, uint32_t *status
)
245 struct target
*target
= bank
->target
;
246 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
247 uint32_t io_base
= spearsmi_info
->io_base
;
249 /* clear transmit finished flag */
253 SMI_WRITE_REG(SMI_CR2
, spearsmi_info
->bank_num
| SMI_RSR
);
255 /* Poll transmit finished flag */
256 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
258 /* clear transmit finished flag */
261 *status
= SMI_READ_REG(SMI_SR
) & 0x0000ffff;
263 /* clean-up SMI_CR2 */
264 SMI_WRITE_REG(SMI_CR2
, 0); /* AB: Required ? */
269 /* check for WIP (write in progress) bit in status register */
271 static int wait_till_ready(struct flash_bank
*bank
, int timeout
)
277 endtime
= timeval_ms() + timeout
;
279 /* read flash status register */
280 retval
= read_status_reg(bank
, &status
);
281 if (retval
!= ERROR_OK
)
284 if ((status
& SMI_WIP_BIT
) == 0)
287 } while (timeval_ms() < endtime
);
289 LOG_ERROR("timeout");
293 /* Send "write enable" command to SPI flash chip.
294 * The operation is triggered by setting SMI_WE bit, and SMI sends
295 * the proper SPI command (0x06) */
296 static int smi_write_enable(struct flash_bank
*bank
)
298 struct target
*target
= bank
->target
;
299 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
300 uint32_t io_base
= spearsmi_info
->io_base
;
304 /* Enter in HW mode */
305 SMI_SET_HW_MODE(); /* AB: is this correct ?*/
307 /* clear transmit finished flag */
310 /* Send write enable command */
311 SMI_WRITE_REG(SMI_CR2
, spearsmi_info
->bank_num
| SMI_WE
);
313 /* Poll transmit finished flag */
314 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
316 /* read flash status register */
317 retval
= read_status_reg(bank
, &status
);
318 if (retval
!= ERROR_OK
)
321 /* Check write enabled */
322 if ((status
& SMI_WEL_BIT
) == 0)
324 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32
, status
);
331 static uint32_t erase_command(struct spearsmi_flash_bank
*spearsmi_info
,
339 cmd
.x
[0] = spearsmi_info
->dev
->erase_cmd
;
340 cmd
.x
[1] = offset
>> 16;
341 cmd
.x
[2] = offset
>> 8;
347 static int smi_erase_sector(struct flash_bank
*bank
, int sector
)
349 struct target
*target
= bank
->target
;
350 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
351 uint32_t io_base
= spearsmi_info
->io_base
;
355 retval
= smi_write_enable(bank
);
356 if (retval
!= ERROR_OK
)
359 /* Switch to SW mode to send sector erase command */
362 /* clear transmit finished flag */
365 /* send SPI command "block erase" */
366 cmd
= erase_command(spearsmi_info
, bank
->sectors
[sector
].offset
);
367 SMI_WRITE_REG(SMI_TR
, cmd
);
368 SMI_WRITE_REG(SMI_CR2
, spearsmi_info
->bank_num
| SMI_SEND
| SMI_TX_LEN_4
);
370 /* Poll transmit finished flag */
371 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
373 /* poll WIP for end of self timed Sector Erase cycle */
374 retval
= wait_till_ready(bank
, SMI_MAX_TIMEOUT
);
375 if (retval
!= ERROR_OK
)
381 static int spearsmi_erase(struct flash_bank
*bank
, int first
, int last
)
383 struct target
*target
= bank
->target
;
384 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
385 uint32_t io_base
= spearsmi_info
->io_base
;
386 int retval
= ERROR_OK
;
389 LOG_DEBUG("%s: from sector %d to sector %d", __FUNCTION__
, first
, last
);
391 if (target
->state
!= TARGET_HALTED
)
393 LOG_ERROR("Target not halted");
394 return ERROR_TARGET_NOT_HALTED
;
397 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
399 LOG_ERROR("Flash sector invalid");
400 return ERROR_FLASH_SECTOR_INVALID
;
403 if (!(spearsmi_info
->probed
))
405 LOG_ERROR("Flash bank not probed");
406 return ERROR_FLASH_BANK_NOT_PROBED
;
409 for (sector
= first
; sector
<= last
; sector
++)
411 if (bank
->sectors
[sector
].is_protected
)
413 LOG_ERROR("Flash sector %d protected", sector
);
418 for (sector
= first
; sector
<= last
; sector
++)
420 retval
= smi_erase_sector(bank
, sector
);
421 if (retval
!= ERROR_OK
)
426 /* Switch to HW mode before return to prompt */
431 static int spearsmi_protect(struct flash_bank
*bank
, int set
,
436 for (sector
= first
; sector
<= last
; sector
++)
437 bank
->sectors
[sector
].is_protected
= set
;
441 static int smi_write_buffer(struct flash_bank
*bank
, uint8_t *buffer
,
442 uint32_t address
, uint32_t len
)
444 struct target
*target
= bank
->target
;
445 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
446 uint32_t io_base
= spearsmi_info
->io_base
;
449 LOG_DEBUG("%s: address=0x%08" PRIx32
" len=0x%08" PRIx32
,
450 __FUNCTION__
, address
, len
);
452 retval
= smi_write_enable(bank
);
453 if (retval
!= ERROR_OK
)
456 /* HW mode, write burst mode */
459 retval
= target_write_buffer(target
, address
, len
, buffer
);
460 if (retval
!= ERROR_OK
)
466 static int spearsmi_write(struct flash_bank
*bank
, uint8_t *buffer
,
467 uint32_t offset
, uint32_t count
)
469 struct target
*target
= bank
->target
;
470 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
471 uint32_t io_base
= spearsmi_info
->io_base
;
472 uint32_t cur_count
, page_size
, page_offset
;
474 int retval
= ERROR_OK
;
476 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
477 __FUNCTION__
, offset
, count
);
479 if (target
->state
!= TARGET_HALTED
)
481 LOG_ERROR("Target not halted");
482 return ERROR_TARGET_NOT_HALTED
;
485 if (offset
+ count
> spearsmi_info
->dev
->size_in_bytes
)
487 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
488 count
= spearsmi_info
->dev
->size_in_bytes
- offset
;
491 /* Check sector protection */
492 for (sector
= 0; sector
< bank
->num_sectors
; sector
++)
494 /* Start offset in or before this sector? */
495 /* End offset in or behind this sector? */
497 (bank
->sectors
[sector
].offset
+ bank
->sectors
[sector
].size
))
498 && ((offset
+ count
- 1) >= bank
->sectors
[sector
].offset
)
499 && bank
->sectors
[sector
].is_protected
)
501 LOG_ERROR("Flash sector %d protected", sector
);
506 page_size
= spearsmi_info
->dev
->pagesize
;
508 /* unaligned buffer head */
509 if (count
> 0 && (offset
& 3) != 0)
511 cur_count
= 4 - (offset
& 3);
512 if (cur_count
> count
)
514 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
,
516 if (retval
!= ERROR_OK
)
523 page_offset
= offset
% page_size
;
524 /* central part, aligned words */
527 /* clip block at page boundary */
528 if (page_offset
+ count
> page_size
)
529 cur_count
= page_size
- page_offset
;
531 cur_count
= count
& ~3;
533 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
,
535 if (retval
!= ERROR_OK
)
548 retval
= smi_write_buffer(bank
, buffer
, bank
->base
+ offset
, count
);
551 /* Switch to HW mode before return to prompt */
556 /* Return ID of flash device */
557 /* On exit, SW mode is kept */
558 static int read_flash_id(struct flash_bank
*bank
, uint32_t *id
)
560 struct target
*target
= bank
->target
;
561 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
562 uint32_t io_base
= spearsmi_info
->io_base
;
565 if (target
->state
!= TARGET_HALTED
)
567 LOG_ERROR("Target not halted");
568 return ERROR_TARGET_NOT_HALTED
;
572 retval
= wait_till_ready(bank
, SMI_PROBE_TIMEOUT
);
573 if (retval
!= ERROR_OK
)
576 /* enter in SW mode */
579 /* clear transmit finished flag */
582 /* Send SPI command "read ID" */
583 SMI_WRITE_REG(SMI_TR
, SMI_READ_ID
);
584 SMI_WRITE_REG(SMI_CR2
,
585 spearsmi_info
->bank_num
| SMI_SEND
| SMI_RX_LEN_3
| SMI_TX_LEN_1
);
587 /* Poll transmit finished flag */
588 SMI_POLL_TFF(SMI_CMD_TIMEOUT
);
590 /* clear transmit finished flag */
593 /* read ID from Receive Register */
594 *id
= SMI_READ_REG(SMI_RR
) & 0x00ffffff;
598 static int spearsmi_probe(struct flash_bank
*bank
)
600 struct target
*target
= bank
->target
;
601 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
603 struct flash_sector
*sectors
;
604 uint32_t id
= 0; /* silence uninitialized warning */
607 if (spearsmi_info
->probed
)
609 spearsmi_info
->probed
= 0;
611 /* check for SPEAr device */
612 switch (target
->tap
->idcode
)
614 case JTAG_ID_3XX_6XX
:
616 spearsmi_info
->io_base
= SMI_CFGREG_3XX_6XX
;
619 case SMI_BASE_3XX_6XX
:
620 spearsmi_info
->bank_num
= SMI_SEL_BANK0
;
622 case SMI_BASE_3XX_6XX
+ SMI_BANK_SIZE
:
623 spearsmi_info
->bank_num
= SMI_SEL_BANK1
;
625 case SMI_BASE_3XX_6XX
+ 2*SMI_BANK_SIZE
:
626 spearsmi_info
->bank_num
= SMI_SEL_BANK2
;
628 case SMI_BASE_3XX_6XX
+ 3*SMI_BANK_SIZE
:
629 spearsmi_info
->bank_num
= SMI_SEL_BANK3
;
632 LOG_ERROR("Invalid base address 0x%" PRIx32
, bank
->base
);
638 LOG_ERROR("0x%" PRIx32
" is invalid id for SPEAr device",
639 target
->tap
->idcode
);
642 io_base
= spearsmi_info
->io_base
;
644 /* read and decode flash ID; returns in SW mode */
645 retval
= read_flash_id(bank
, &id
);
647 if (retval
!= ERROR_OK
)
650 for (struct flash_device
*p
= flash_devices
; p
->name
; p
++)
651 if (p
->device_id
== id
) {
652 spearsmi_info
->dev
= p
;
656 if (!spearsmi_info
->dev
)
658 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32
")", id
);
662 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32
")",
663 spearsmi_info
->dev
->name
, spearsmi_info
->dev
->device_id
);
665 /* Set correct size value */
666 bank
->size
= spearsmi_info
->dev
->size_in_bytes
;
668 /* create and fill sectors array */
670 spearsmi_info
->dev
->size_in_bytes
/ spearsmi_info
->dev
->sectorsize
;
671 sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
674 LOG_ERROR("not enough memory");
678 for (int sector
= 0; sector
< bank
->num_sectors
; sector
++)
680 sectors
[sector
].offset
= sector
* spearsmi_info
->dev
->sectorsize
;
681 sectors
[sector
].size
= spearsmi_info
->dev
->sectorsize
;
682 sectors
[sector
].is_erased
= -1;
683 sectors
[sector
].is_protected
= 1;
686 bank
->sectors
= sectors
;
687 spearsmi_info
->probed
= 1;
691 static int spearsmi_auto_probe(struct flash_bank
*bank
)
693 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
694 if (spearsmi_info
->probed
)
696 return spearsmi_probe(bank
);
699 static int spearsmi_protect_check(struct flash_bank
*bank
)
701 /* Nothing to do. Protection is only handled in SW. */
705 static int get_spearsmi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
707 struct spearsmi_flash_bank
*spearsmi_info
= bank
->driver_priv
;
710 if (!(spearsmi_info
->probed
))
712 printed
= snprintf(buf
, buf_size
,
713 "\nSPEAr SMI flash bank not probed yet\n");
717 printed
= snprintf(buf
, buf_size
, "\nSPEAr SMI flash information:\n"
718 " Device \'%s\' (ID 0x%08x)\n",
719 spearsmi_info
->dev
->name
, spearsmi_info
->dev
->device_id
);
726 struct flash_driver spearsmi_flash
= {
728 .flash_bank_command
= spearsmi_flash_bank_command
,
729 .erase
= spearsmi_erase
,
730 .protect
= spearsmi_protect
,
731 .write
= spearsmi_write
,
732 .read
= default_flash_read
,
733 .probe
= spearsmi_probe
,
734 .auto_probe
= spearsmi_auto_probe
,
735 .erase_check
= default_flash_blank_check
,
736 .protect_check
= spearsmi_protect_check
,
737 .info
= get_spearsmi_info
,