testing/results/v0.4.0-rc1/STR912.html

   1 <html>
   2 <head>
   3 <title>Test results for version 1.62</title>
   4 </head>
   5
   6 <body>
   7
   8 <H1>STR912</H1>
   9
  10 <H2>Connectivity</H2>
  11 <table border=1>
  12         <tr>
  13                 <td>ID</td>
  14                 <td>Target</td>
  15                 <td>Interface</td>
  16                 <td>Description</td>
  17                 <td>Initial state</td>
  18                 <td>Input</td>
  19                 <td>Expected output</td>
  20                 <td>Actual output</td>
  21                 <td>Pass/Fail</td>
  22         </tr>
  23         <tr>
  24                 <td><a name="CON001"/>CON001</td>
  25                 <td>STR912</td>
  26                 <td>ZY1000</td>
  27                 <td>Telnet connection</td>
  28                 <td>Power on, jtag target attached</td>
  29                 <td>On console, type<br><code>telnet ip port</code></td>
  30                 <td><code>Open On-Chip Debugger<br>></code></td>
  31                 <td><code>> telnet 10.0.0.142<br>
  32                                         Trying 10.0.0.142...<br>
  33                                         Connected to 10.0.0.142.<br>
  34                                         Escape character is '^]'.<br>
  35                                         Open On-Chip Debugger<br>
  36                                         >
  37 </code></td>
  38                 <td>PASS</td>
  39         </tr>
  40         <tr>
  41                 <td><a name="CON002"/>CON002</td>
  42                 <td>STR912</td>
  43                 <td>ZY1000</td>
  44                 <td>GDB server connection</td>
  45                 <td>Power on, jtag target attached</td>
  46                 <td>On GDB console, type<br><code>target remote ip:port</code></td>
  47                 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
  48                 <td><code>
  49                         (gdb) tar remo 10.0.0.142:3333<br>
  50                         Remote debugging using 10.0.0.142:3333<br>
  51                         0x00016434 in ?? ()<br>
  52                         (gdb)
  53                 </code></td>
  54                 <td>PASS</td>
  55         </tr>
  56 </table>
  57
  58 <H2>Reset</H2>
  59 <table border=1>
  60         <tr>
  61                 <td>ID</td>
  62                 <td>Target</td>
  63                 <td>Interface</td>
  64                 <td>Description</td>
  65                 <td>Initial state</td>
  66                 <td>Input</td>
  67                 <td>Expected output</td>
  68                 <td>Actual output</td>
  69                 <td>Pass/Fail</td>
  70         </tr>
  71         <tr>
  72                 <td><a name="RES001"/>RES001</td>
  73                 <td>STR912</td>
  74                 <td>ZY1000</td>
  75                 <td>Reset halt on a blank target</td>
  76                 <td>Erase all the content of the flash</td>
  77                 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  78                 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  79                 <td>
  80                         <code>
  81 > reset halt<br>
  82 RCLK - adaptive<br>
  83 SRST took 2ms to deassert<br>
  84 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
  85 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
  86 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
  87 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
  88 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
  89 Trying to use configured scan chain anyway...<br>
  90 Bypassing JTAG setup events due to errors<br>
  91 SRST took 2ms to deassert<br>
  92 target state: halted<br>
  93 target halted in ARM state due to debug-request, current mode: Supervisor<br>
  94 cpsr: 0x000000d3 pc: 0x00000000<br>
  95 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
  96 >
  97                         </code>
  98                 </td>
  99                 <td>PASS</td>
 100         </tr>
 101         <tr>
 102                 <td><a name="RES002"/>RES002</td>
 103                 <td>STR912</td>
 104                 <td>ZY1000</td>
 105                 <td>Reset init on a blank target</td>
 106                 <td>Erase all the content of the flash</td>
 107                 <td>Connect via the telnet interface and type <br><code>reset init</code></td>
 108                 <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
 109                 <td>
 110                         <code>
 111 > reset init<br>
 112 RCLK - adaptive<br>
 113 SRST took 2ms to deassert<br>
 114 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 115 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 116 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 117 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 118 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 119 Trying to use configured scan chain anyway...<br>
 120 Bypassing JTAG setup events due to errors<br>
 121 SRST took 2ms to deassert<br>
 122 target state: halted<br>
 123 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 124 cpsr: 0x000000d3 pc: 0x00000000<br>
 125 cleared protection for sectors 0 through 7 on flash bank 0<br>
 126 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 127 >
 128                         </code>
 129                 </td>
 130                 <td>PASS</td>
 131         </tr>
 132         <tr>
 133                 <td><a name="RES003"/>RES003</td>
 134                 <td>STR912</td>
 135                 <td>ZY1000</td>
 136                 <td>Reset after a power cycle of the target</td>
 137                 <td>Reset the target then power cycle the target</td>
 138                 <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
 139                 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
 140                 <td>
 141                         <code>
 142       nsed nSRST asserted.<br>
 143   nsed power dropout.<br>
 144   nsed power restore.<br>
 145 RCLK - adaptive<br>
 146 SRST took 85ms to deassert<br>
 147 SRST took 2ms to deassert<br>
 148 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 149 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 150 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 151 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 152 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 153 Trying to use configured scan chain anyway...<br>
 154 Bypassing JTAG setup events due to errors<br>
 155 SRST took 2ms to deassert<br>
 156 target state: halted<br>
 157 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 158 cpsr: 0x000000d3 pc: 0x00000000<br>
 159 cleared protection for sectors 0 through 7 on flash bank 0<br>
 160 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 161 > reset halt<br>
 162 RCLK - adaptive<br>
 163 SRST took 2ms to deassert<br>
 164 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 165 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 166 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 167 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 168 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 169 Trying to use configured scan chain anyway...<br>
 170 Bypassing JTAG setup events due to errors<br>
 171 SRST took 2ms to deassert<br>
 172 target state: halted<br>
 173 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 174 cpsr: 0x000000d3 pc: 0x00000000<br>
 175 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 176 >
 177                         </code>
 178                 </td>
 179                 <td>PASS</td>
 180         </tr>
 181         <tr>
 182                 <td><a name="RES004"/>RES004</td>
 183                 <td>STR912</td>
 184                 <td>ZY1000</td>
 185                 <td>Reset halt on a blank target where reset halt is supported</td>
 186                 <td>Erase all the content of the flash</td>
 187                 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
 188                 <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
 189                 <td>
 190                         <code>
 191 > reset halt<br>
 192  RCLK - adaptive<br>
 193 SRST took 2ms to deassert<br>
 194 JTAG tap: str912.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)<br>
 195 JTAG Tap/device matched<br>
 196 JTAG tap: str912.cpu tap/device found: 0x25966041 (Manufacturer: 0x020, Part: 0x5966, Version: 0x2)<br>
 197 JTAG Tap/device matched<br>
 198 JTAG tap: str912.bs tap/device found: 0x2457f041 (Manufacturer: 0x020, Part: 0x457f, Version: 0x2)<br>
 199 JTAG Tap/device matched<br>
 200 SRST took 2ms to deassert<br>
 201 target state: halted<br>
 202 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 203 cpsr: 0x000000d3 pc: 0x00000000<br>
 204 >
 205                 </td>
 206                 <td>PASS</td>
 207         </tr>
 208         <tr>
 209                 <td><a name="RES005"/>RES005</td>
 210                 <td>STR912</td>
 211                 <td>ZY1000</td>
 212                 <td>Reset halt on a blank target using return clock</td>
 213                 <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
 214                 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
 215                 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
 216                 <td>
 217                         <code>
 218                         > reset halt<br>
 219 RCLK - adaptive<br>
 220 SRST took 2ms to deassert<br>
 221 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 222 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 223 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 224 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 225 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 226 Trying to use configured scan chain anyway...<br>
 227 Bypassing JTAG setup events due to errors<br>
 228 SRST took 2ms to deassert<br>
 229 target state: halted<br>
 230 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 231 cpsr: 0x000000d3 pc: 0x00000000<br>
 232 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 233 >
 234                         </code>
 235                 </td>
 236                 <td>PASS</td>
 237         </tr>
 238 </table>
 239
 240 <H2>JTAG Speed</H2>
 241 <table border=1>
 242         <tr>
 243                 <td>ID</td>
 244                 <td>Target</td>
 245                 <td>ZY1000</td>
 246                 <td>Description</td>
 247                 <td>Initial state</td>
 248                 <td>Input</td>
 249                 <td>Expected output</td>
 250                 <td>Actual output</td>
 251                 <td>Pass/Fail</td>
 252         </tr>
 253         <tr>
 254                 <td><a name="SPD001"/>SPD001</td>
 255                 <td>STR912</td>
 256                 <td>ZY1000</td>
 257                 <td>16MHz on normal operation</td>
 258                 <td>Reset init the target according to RES002 </td>
 259                 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
 260                 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
 261                 <td>
 262                         <code>
 263 > jtag_khz 16000<br>
 264 jtag_speed 4 => JTAG clk=16.000000<br>
 265 16000 kHz<br>
 266 ThumbEE -- incomplete support<br>
 267 target state: halted<br>
 268 target halted in ThumbEE state due to debug-request, current mode: System<br>
 269 cpsr: 0xfdfdffff pc: 0xfdfdfff9<br>
 270 > mdw 0 32      <br>
 271 0x00000000: 00000000 00000000 ffffffff ffffffff 00000001 ffffffff 00000001 ffffffff<br>
 272 0x00000020: 00000001 00000001 00000001 00000001 00000001 fffffffe fffffffe 00000001<br>
 273 0x00000040: fffffffe 00000000 00000000 00000000 00000000 00000000 00000000 00000000<br>
 274 0x00000060: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000001 00000000<br>
 275 invalid mode value encountered 0<br>
 276 cpsr contains invalid mode value - communication failure<br>
 277 ThumbEE -- incomplete support<br>
 278 target state: halted<br>
 279 target halted in ThumbEE state due to debug-request, current mode: System<br>
 280 cpsr: 0xffffffff pc: 0xfffffff8<br>
 281 >
 282                         </code>
 283                 </td>
 284                 <td><font color=red><b>FAIL</b></font></td>
 285         </tr>
 286         <tr>
 287                 <td><a name="SPD002"/>SPD002</td>
 288                 <td>STR912</td>
 289                 <td>ZY1000</td>
 290                 <td>8MHz on normal operation</td>
 291                 <td>Reset init the target according to RES002 </td>
 292                 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
 293                 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
 294                 <td>
 295                         <code>
 296 > jtag_khz 8000<br>
 297 jtag_speed 8 => JTAG clk=8.000000<br>
 298 8000 kHz<br>
 299 > halt      <br>
 300 invalid mode value encountered 0<br>
 301 cpsr contains invalid mode value - communication failure<br>
 302 Command handler execution failed<br>
 303 in procedure 'halt' called at file "command.c", line 647<br>
 304 called at file "command.c", line 361<br>
 305 Halt timed out, wake up GDB.<br>
 306 >
 307                         </code>
 308                 </td>
 309                 <td><font color=red><b>FAIL</b></font></td>
 310         </tr>
 311         <tr>
 312                 <td><a name="SPD003"/>SPD003</td>
 313                 <td>STR912</td>
 314                 <td>ZY1000</td>
 315                 <td>4MHz on normal operation</td>
 316                 <td>Reset init the target according to RES002 </td>
 317                 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
 318                 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
 319                 <td>
 320                         <code>
 321 > jtag_khz 4000<br>
 322 jtag_speed 16 => JTAG clk=4.000000<br>
 323 4000 kHz<br>
 324 > halt      <br>
 325 > mdw 0 32     <br>
 326 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 327 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 328 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 329 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 330 >
 331                         </code>
 332                 </td>
 333                 <td>PASS</td>
 334         </tr>
 335         <tr>
 336                 <td><a name="SPD004"/>SPD004</td>
 337                 <td>STR912</td>
 338                 <td>ZY1000</td>
 339                 <td>2MHz on normal operation</td>
 340                 <td>Reset init the target according to RES002 </td>
 341                 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
 342                 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
 343                 <td>
 344                         <code>
 345 > jtag_khz 2000<br>
 346 jtag_speed 32 => JTAG clk=2.000000<br>
 347 2000 kHz<br>
 348 > halt<br>
 349 > mdw 0 32<br>
 350 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 351 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 352 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 353 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 354 >
 355                         </code>
 356                 </td>
 357                 <td>PASS</td>
 358         </tr>
 359         <tr>
 360                 <td><a name="SPD005"/>SPD005</td>
 361                 <td>STR912</td>
 362                 <td>ZY1000</td>
 363                 <td>RCLK on normal operation</td>
 364                 <td>Reset init the target according to RES002 </td>
 365                 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
 366                 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
 367                 <td>
 368                         <code>
 369 > jtag_khz 0<br>
 370 RCLK - adaptive<br>
 371 > halt      <br>
 372 > mdw 0 32  <br>
 373 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 374 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 375 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 376 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 377 >
 378                         </code>
 379                 </td>
 380                 <td>PASS</td>
 381         </tr>
 382 </table>
 383
 384 <H2>Debugging</H2>
 385 <table border=1>
 386         <tr>
 387                 <td>ID</td>
 388                 <td>Target</td>
 389                 <td>Interface</td>
 390                 <td>Description</td>
 391                 <td>Initial state</td>
 392                 <td>Input</td>
 393                 <td>Expected output</td>
 394                 <td>Actual output</td>
 395                 <td>Pass/Fail</td>
 396         </tr>
 397         <tr>
 398                 <td><a name="DBG001"/>DBG001</td>
 399                 <td>STR912</td>
 400                 <td>ZY1000</td>
 401                 <td>Load is working</td>
 402                 <td>Reset init is working, RAM is accesible, GDB server is started</td>
 403                 <td>On the console of the OS: <br>
 404                         <code>arm-elf-gdb test_ram.elf</code><br>
 405                         <code>(gdb) target remote ip:port</code><br>
 406                         <code>(gdb) load</load>
 407                 </td>
 408                 <td>Load should return without error, typical output looks like:<br>
 409                         <code>
 410                                 Loading section .text, size 0x14c lma 0x0<br>
 411                                 Start address 0x40, load size 332<br>
 412                                 Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
 413                         </code>
 414                 </td>
 415                 <td><code>
 416 (gdb) load<br>
 417 Loading section .text, size 0x1a0 lma 0x4000000<br>
 418 Loading section .rodata, size 0x4 lma 0x40001a0<br>
 419 Start address 0x4000000, load size 420<br>
 420 Transfer rate: 29 KB/sec, 210 bytes/write.<br>
 421 (gdb)
 422                 </code></td>
 423                 <td>PASS</td>
 424         </tr>
 425
 426         <tr>
 427                 <td><a name="DBG002"/>DBG002</td>
 428                 <td>STR912</td>
 429                 <td>ZY1000</td>
 430                 <td>Software breakpoint</td>
 431                 <td>Load the test_ram.elf application, use instructions from GDB001</td>
 432                 <td>In the GDB console:<br>
 433                         <code>
 434                                 (gdb) monitor gdb_breakpoint_override soft<br>
 435                                 force soft breakpoints<br>
 436                                 (gdb) break main<br>
 437                                 Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
 438                                 (gdb) continue<br>
 439                                 Continuing.
 440                         </code>
 441                 </td>
 442                 <td>The software breakpoint should be reached, a typical output looks like:<br>
 443                         <code>
 444                                 target state: halted<br>
 445                                 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
 446                                 cpsr: 0x000000d3 pc: 0x000000ec<br>
 447                                 <br>
 448                                 Breakpoint 1, main () at src/main.c:71<br>
 449                                 71        DWORD a = 1;
 450                         </code>
 451                 </td>
 452                 <td>
 453                         <code>
 454 (gdb) monitor gdb_breakpoint_override soft<br>
 455 force soft breakpoints<br>
 456 Current language:  auto<br>
 457 The current source language is "auto; currently asm".<br>
 458 (gdb) break main<br>
 459 Breakpoint 1 at 0x4000144: file src/main.c, line 69.<br>
 460 (gdb) c<br>
 461 Continuing.<br>
 462 <br>
 463 Breakpoint 1, main () at src/main.c:69<br>
 464 warning: Source file is more recent than executable.<br>
 465 69        DWORD a = 1;<br>
 466 Current language:  auto<br>
 467 The current source language is "auto; currently c".<br>
 468 (gdb)
 469                         </code>
 470                 </td>
 471                 <td>PASS</td>
 472         </tr>
 473         <tr>
 474                 <td><a name="DBG003"/>DBG003</td>
 475                 <td>STR912</td>
 476                 <td>ZY1000</td>
 477                 <td>Single step in a RAM application</td>
 478                 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
 479                 <td>In GDB, type <br><code>(gdb) step</code></td>
 480                 <td>The next instruction should be reached, typical output:<br>
 481                         <code>
 482                                 (gdb) step<br>
 483                                 target state: halted<br>
 484                                 target halted in ARM state due to single step, current mode: Abort<br>
 485                                 cpsr: 0x20000097 pc: 0x000000f0<br>
 486                                 target state: halted<br>
 487                                 target halted in ARM state due to single step, current mode: Abort<br>
 488                                 cpsr: 0x20000097 pc: 0x000000f4<br>
 489                                 72        DWORD b = 2;
 490                         </code>
 491                 </td>
 492                 <td>
 493                         <code>
 494                                 (gdb) step<br>
 495                                 70        DWORD b = 2;<br>
 496                                 (gdb)<br>
 497                         </code>
 498                 </td>
 499                 <td>PASS</td>
 500         </tr>
 501         <tr>
 502                 <td><a name="DBG004"/>DBG004</td>
 503                 <td>STR912</td>
 504                 <td>ZY1000</td>
 505                 <td>Software break points are working after a reset</td>
 506                 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
 507                 <td>In GDB, type <br><code>
 508                         (gdb) monitor reset init<br>
 509                         (gdb) load<br>
 510                         (gdb) continue<br>
 511                         </code></td>
 512                 <td>The breakpoint should be reached, typical output:<br>
 513                         <code>
 514                                 target state: halted<br>
 515                                 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
 516                                 cpsr: 0x000000d3 pc: 0x000000ec<br>
 517                                 <br>
 518                                 Breakpoint 1, main () at src/main.c:71<br>
 519                                 71        DWORD a = 1;
 520                         </code>
 521                 </td>
 522                 <td><code>
 523 (gdb) monitor reset init<br>
 524 RCLK - adaptive<br>
 525 SRST took 2ms to deassert<br>
 526 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 527 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 528 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 529 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 530 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 531 Trying to use configured scan chain anyway...<br>
 532 Bypassing JTAG setup events due to errors<br>
 533 SRST took 2ms to deassert<br>
 534 target state: halted<br>
 535 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 536 cpsr: 0x000000d3 pc: 0x00000000<br>
 537 cleared protection for sectors 0 through 7 on flash bank 0<br>
 538 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 539 (gdb) load<br>
 540 Loading section .text, size 0x1a0 lma 0x4000000<br>
 541 Loading section .rodata, size 0x4 lma 0x40001a0<br>
 542 Start address 0x4000000, load size 420<br>
 543 Transfer rate: 25 KB/sec, 210 bytes/write.<br>
 544 (gdb) c<br>
 545 Continuing.<br>
 546 <br>
 547 Breakpoint 1, main () at src/main.c:69<br>
 548 69        DWORD a = 1;<br>
 549 (gdb)
 550                 </code></td>
 551                 <td>PASS</td>
 552         </tr>
 553         <tr>
 554                 <td><a name="DBG005"/>DBG005</td>
 555                 <td>STR912</td>
 556                 <td>ZY1000</td>
 557                 <td>Hardware breakpoint</td>
 558                 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
 559                 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
 560                         <code>
 561                                 (gdb) monitor reset init<br>
 562                                 (gdb) load<br>
 563                                 Loading section .text, size 0x194 lma 0x100000<br>
 564                                 Start address 0x100040, load size 404<br>
 565                                 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
 566                                 (gdb) monitor gdb_breakpoint_override hard<br>
 567                                 force hard breakpoints<br>
 568                                 (gdb) break main<br>
 569                                 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
 570                                 (gdb) continue<br>
 571                         </code>
 572                 </td>
 573                 <td>The breakpoint should be reached, typical output:<br>
 574                         <code>
 575                                 Continuing.<br>
 576                                 <br>
 577                                 Breakpoint 1, main () at src/main.c:69<br>
 578                                 69        DWORD a = 1;<br>
 579                         </code>
 580                 </td>
 581                 <td>
 582                 <code>
 583 (gdb) monitor reset init<br>
 584 RCLK - adaptive<br>
 585 SRST took 2ms to deassert<br>
 586 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 587 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 588 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 589 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 590 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 591 Trying to use configured scan chain anyway...<br>
 592 Bypassing JTAG setup events due to errors<br>
 593 SRST took 2ms to deassert<br>
 594 target state: halted<br>
 595 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 596 cpsr: 0x000000d3 pc: 0x00000000<br>
 597 cleared protection for sectors 0 through 7 on flash bank 0<br>
 598 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 599 (gdb) load<br>
 600 Loading section .text, size 0x1a0 lma 0x0<br>
 601 Loading section .rodata, size 0x4 lma 0x1a0<br>
 602 Start address 0x0, load size 420<br>
 603 Transfer rate: 426 bytes/sec, 210 bytes/write.<br>
 604 (gdb) monitor gdb_breakpoint_override hard<br>
 605 force hard breakpoints<br>
 606 (gdb) break main<br>
 607 Breakpoint 1 at 0x144: file src/main.c, line 69.<br>
 608 (gdb) continue<br>
 609 Continuing.<br>
 610 Note: automatically using hardware breakpoints for read-only addresses.<br>
 611 <br>
 612 Breakpoint 1, main () at src/main.c:69<br>
 613 warning: Source file is more recent than executable.<br>
 614 69        DWORD a = 1;<br>
 615 Current language:  auto<br>
 616 The current source language is "auto; currently c".<br>
 617 (gdb)
 618                 </code>
 619                 </td>
 620                 <td>PASS</td>
 621         </tr>
 622         <tr>
 623                 <td><a name="DBG006"/>DBG006</td>
 624                 <td>STR912</td>
 625                 <td>ZY1000</td>
 626                 <td>Hardware breakpoint is set after a reset</td>
 627                 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
 628                 <td>In GDB, type <br>
 629                         <code>
 630                                 (gdb) monitor reset<br>
 631                                 (gdb) monitor reg pc 0x100000<br>
 632                                 pc (/32): 0x00100000<br>
 633                                 (gdb) continue
 634                         </code><br>
 635                         where the value inserted in PC is the start address of the application
 636                 </td>
 637                 <td>The breakpoint should be reached, typical output:<br>
 638                         <code>
 639                                 Continuing.<br>
 640                                 <br>
 641                                 Breakpoint 1, main () at src/main.c:69<br>
 642                                 69        DWORD a = 1;<br>
 643                         </code>
 644                 </td>
 645                 <td>
 646                 <code>
 647 (gdb) monitor reset init<br>
 648 RCLK - adaptive<br>
 649 SRST took 2ms to deassert<br>
 650 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
 651 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
 652 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 653 JTAG tap: str912.bs       UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
 654 JTAG tap: str912.bs  expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
 655 Trying to use configured scan chain anyway...<br>
 656 Bypassing JTAG setup events due to errors<br>
 657 SRST took 2ms to deassert<br>
 658 target state: halted<br>
 659 target halted in ARM state due to debug-request, current mode: Supervisor<br>
 660 cpsr: 0x000000d3 pc: 0x00000000<br>
 661 cleared protection for sectors 0 through 7 on flash bank 0<br>
 662 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
 663 (gdb) c<br>
 664 Continuing.<br>
 665 <br>
 666 Breakpoint 1, main () at src/main.c:69<br>
 667 69        DWORD a = 1;<br>
 668 (gdb)
 669                 </code>
 670                 </td>
 671                 <td>PASS</td>
 672         </tr>
 673         <tr>
 674                 <td><a name="DBG007"/>DBG007</td>
 675                 <td>STR912</td>
 676                 <td>ZY1000</td>
 677                 <td>Single step in ROM</td>
 678                 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
 679                 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
 680                         <code>
 681                                 (gdb) monitor reset<br>
 682                                 (gdb) load<br>
 683                                 Loading section .text, size 0x194 lma 0x100000<br>
 684                                 Start address 0x100040, load size 404<br>
 685                                 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
 686                                 (gdb) monitor arm7_9  force_hw_bkpts enable<br>
 687                                 force hardware breakpoints enabled<br>
 688                                 (gdb) break main<br>
 689                                 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
 690                                 (gdb) continue<br>
 691                                 Continuing.<br>
 692                                 <br>
 693                                 Breakpoint 1, main () at src/main.c:69<br>
 694                                 69        DWORD a = 1;<br>
 695                                 (gdb) step
 696                         </code>
 697                 </td>
 698                 <td>The breakpoint should be reached, typical output:<br>
 699                         <code>
 700                                 target state: halted<br>
 701                                 target halted in ARM state due to single step, current mode: Supervisor<br>
 702                                 cpsr: 0x60000013 pc: 0x0010013c<br>
 703                                 70        DWORD b = 2;<br>
 704                         </code>
 705                 </td>
 706                 <td><code>
 707                         (gdb) c<br>
 708 Continuing.<br>
 709 <br>
 710 Breakpoint 2, main () at src/main.c:69<br>
 711 69        DWORD a = 1;<br>
 712 Current language:  auto<br>
 713 The current source language is "auto; currently c".<br>
 714 (gdb) step<br>
 715 70        DWORD b = 2;<br>
 716 (gdb)
 717                 </code></td>
 718                 <td>PASS</td>
 719         </tr>
 720 </table>
 721
 722 <H2>RAM access</H2>
 723 Note: these tests are not designed to test/debug the target, but to test functionalities!
 724 <table border=1>
 725         <tr>
 726                 <td>ID</td>
 727                 <td>Target</td>
 728                 <td>Interface</td>
 729                 <td>Description</td>
 730                 <td>Initial state</td>
 731                 <td>Input</td>
 732                 <td>Expected output</td>
 733                 <td>Actual output</td>
 734                 <td>Pass/Fail</td>
 735         </tr>
 736         <tr>
 737                 <td><a name="RAM001"/>RAM001</td>
 738                 <td>STR912</td>
 739                 <td>ZY1000</td>
 740                 <td>32 bit Write/read RAM</td>
 741                 <td>Reset init is working</td>
 742                 <td>On the telnet interface<br>
 743                         <code>  > mww ram_address 0xdeadbeef 16<br>
 744                                         > mdw ram_address 32
 745                         </code>
 746                 </td>
 747                 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
 748                         <code>
 749                                 > mww 0x0 0xdeadbeef 16<br>
 750                                 > mdw 0x0 32<br>
 751                                 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 752                                 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 753                                 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
 754                                 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
 755                         </code>
 756                 </td>
 757                 <td><code>
 758 > mww 0x4000000 0xdeadbeef 16<br>
 759 > mdw 0x4000000 32            <br>
 760 0x04000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 761 0x04000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 762 0x04000040: e580100c e3a01802 e5801010 e3a01018 e5801018 e59f00a8 e59f10a8 e5801000<br>
 763 0x04000060: e3a00806 ee2f0f11 e321f0d7 e59fd098 e321f0db e59fd094 e321f0d3 e59fd090<br>
 764 >
 765 </code></td>
 766                 <td>PASS</td>
 767         </tr>
 768         <tr>
 769                 <td><a name="RAM002"/>RAM002</td>
 770                 <td>STR912</td>
 771                 <td>ZY1000</td>
 772                 <td>16 bit Write/read RAM</td>
 773                 <td>Reset init is working</td>
 774                 <td>On the telnet interface<br>
 775                         <code>  > mwh ram_address 0xbeef 16<br>
 776                                         > mdh ram_address 32
 777                         </code>
 778                 </td>
 779                 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
 780                         <code>
 781                                 > mwh 0x0 0xbeef 16<br>
 782                                 > mdh 0x0 32<br>
 783                                 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
 784                                 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
 785                                 >
 786                         </code>
 787                 </td>
 788                 <td><code>
 789 > mwh 0x4000000 0xbeef 16<br>
 790 > mdh 0x4000000 32<br>
 791 0x04000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
 792 0x04000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
 793 >
 794                 </code></td>
 795                 <td>PASS</td>
 796         </tr>
 797         <tr>
 798                 <td><a name="RAM003"/>RAM003</td>
 799                 <td>STR912</td>
 800                 <td>ZY1000</td>
 801                 <td>8 bit Write/read RAM</td>
 802                 <td>Reset init is working</td>
 803                 <td>On the telnet interface<br>
 804                         <code>  > mwb ram_address 0xab 16<br>
 805                                         > mdb ram_address 32
 806                         </code>
 807                 </td>
 808                 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
 809                         <code>
 810                                 > mwb ram_address 0xab 16<br>
 811                                 > mdb ram_address 32<br>
 812                                 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
 813                                 >
 814                         </code>
 815                 </td>
 816                 <td><code>
 817 > mwb 0x4000000 0xab 16<br>
 818 > mdb 0x4000000 32<br>
 819 0x04000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be<br>
 820 >
 821                 </code></td>
 822                 <td>PASS</td>
 823         </tr>
 824 </table>
 825
 826
 827
 828 <H2>Flash access</H2>
 829 <table border=1>
 830         <tr>
 831                 <td>ID</td>
 832                 <td>Target</td>
 833                 <td>Interface</td>
 834                 <td>Description</td>
 835                 <td>Initial state</td>
 836                 <td>Input</td>
 837                 <td>Expected output</td>
 838                 <td>Actual output</td>
 839                 <td>Pass/Fail</td>
 840         </tr>
 841         <tr>
 842                 <td><a name="FLA001"/>FLA001</td>
 843                 <td>STR912</td>
 844                 <td>ZY1000</td>
 845                 <td>Flash probe</td>
 846                 <td>Reset init is working</td>
 847                 <td>On the telnet interface:<br>
 848                         <code>  > flash probe 0</code>
 849                 </td>
 850                 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
 851                         <code>flash 'ecosflash' found at 0x01000000</code>
 852                 </td>
 853                 <td>
 854                 <code>
 855                         > flash probe 0<br>
 856                         flash 'str9x' found at 0x00000000<br>
 857                         >
 858                 </code>
 859                 </td>
 860                 <td>PASS</td>
 861         </tr>
 862         <tr>
 863                 <td><a name="FLA002"/>FLA002</td>
 864                 <td>STR912</td>
 865                 <td>ZY1000</td>
 866                 <td>flash fillw</td>
 867                 <td>Reset init is working, flash is probed</td>
 868                 <td>On the telnet interface<br>
 869                         <code>  > flash fillw 0x1000000 0xdeadbeef 16
 870                         </code>
 871                 </td>
 872                 <td>The commands should execute without error. The output looks like:<br>
 873                         <code>
 874                                 wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
 875                         </code><br>
 876                         To verify the contents of the flash:<br>
 877                         <code>
 878                                 > mdw 0x1000000 32<br>
 879                                 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 880                                 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 881                                 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 882                                 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
 883                         </code>
 884                 </td>
 885                 <td><code>
 886 > flash fillw 0x0 0xdeadbeef 16 <br>
 887 wrote 64 bytes to 0x00000000 in 0.020000s (3.125 kb/s)<br>
 888 > mdw 0 32<br>
 889 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 890 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
 891 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 892 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 893 >
 894                         </code></td>
 895                 <td>PASS</td>
 896         </tr>
 897         <tr>
 898                 <td><a name="FLA003"/>FLA003</td>
 899                 <td>STR912</td>
 900                 <td>ZY1000</td>
 901                 <td>Flash erase</td>
 902                 <td>Reset init is working, flash is probed</td>
 903                 <td>On the telnet interface<br>
 904                         <code>  >  flash erase_address 0x1000000 0x20000
 905                         </code>
 906                 </td>
 907                 <td>The commands should execute without error.<br>
 908                         <code>
 909                                 erased address 0x01000000 length 131072 in 4.970000s<br>
 910                         </code>
 911                         To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
 912                         <code>
 913                                 > mdw 0x1000000 32<br>
 914                                 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 915                                 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 916                                 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 917                                 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
 918                         </code>
 919                 </td>
 920                 <td><code>
 921 > flash erase_address 0 0x20000<br>
 922 erased address 0x00000000 (length 131072) in 1.970000s (64.975 kb/s)<br>
 923 > mdw 0 32<br>
 924 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 925 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 926 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 927 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 928 >
 929 </code></td>
 930                 <td>PASS</td>
 931         </tr>
 932                 <tr>
 933                 <td><a name="FLA004"/>FLA004</td>
 934                 <td>STR912</td>
 935                 <td>ZY1000</td>
 936                 <td>Entire flash erase</td>
 937                 <td>Reset init is working, flash is probed</td>
 938                 <td>On the telnet interface<br>
 939                         <code>  >  flash erase_address 0x0 0x80000
 940                         </code>
 941                 </td>
 942                 <td>The commands should execute without error.<br>
 943                         <code>
 944                                 erased address 0x01000000 length 8192 in 4.970000s<br>
 945                         </code>
 946                         To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
 947                         <code>
 948                                 > mdw 0x1000000 32<br>
 949                                 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 950                                 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 951                                 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 952                                 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
 953                         </code>
 954                 </td>
 955                 <td><code>
 956 > flash erase_address 0 0x80000<br>
 957  erased address 0x00000000 length 524288 in 1.020000s<br>
 958 <br>
 959 > mdw 0 32<br>
 960  0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 961 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 962 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
 963 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
 964 </code></td>
 965                 <td>PASS</td>
 966         </tr>
 967         <tr>
 968                 <td><a name="FLA005"/>FLA005</td>
 969                 <td>STR912</td>
 970                 <td>ZY1000</td>
 971                 <td>Loading to flash from GDB</td>
 972                 <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
 973                 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
 974                                 <code>
 975                                         (gdb) target remote ip:port<br>
 976                                         (gdb) monitor reset<br>
 977                                         (gdb) load<br>
 978                                         Loading section .text, size 0x194 lma 0x100000<br>
 979                                         Start address 0x100040, load size 404<br>
 980                                         Transfer rate: 179 bytes/sec, 404 bytes/write.
 981                                         (gdb) monitor verify_image path_to_elf_file
 982                                 </code>
 983                 </td>
 984                 <td>The output should look like:<br>
 985                         <code>
 986                                 verified 404 bytes in 5.060000s
 987                         </code><br>
 988                         The failure message is something like:<br>
 989                         <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
 990                 </td>
 991                 <td>
 992                         <code>
 993 (gdb) load<br>
 994 Loading section .text, size 0x1a0 lma 0x0<br>
 995 Loading section .rodata, size 0x4 lma 0x1a0<br>
 996 Start address 0x0, load size 420<br>
 997 Transfer rate: 425 bytes/sec, 210 bytes/write.<br>
 998 (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
 999 verified 420 bytes in 0.350000s (1.172 kb/s)<br>
1000 (gdb)
1001                         </code>
1002                 </td>
1003                 <td>PASS</td>
1004         </tr>
1005 </table>
1006
1007 </body>
1008 </html>