?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dsp5680xx - indent fix
[openocd/dsp568013.git] / testing / results / v0.4.0-rc1 / LPC2148.html
blob425b52484419c800a50a8794e6419cf3a1bb7d0d
1 <html>
2 <head>
3 <title>Test results for revision 1.62</title>
4 </head>
5
6 <body>
7
8 <H1>LPC2148</H1>
9
10 <H2>Connectivity</H2>
11 <table border=1>
12 <tr>
13 <td>ID</td>
14 <td>Target</td>
15 <td>Interface</td>
16 <td>Description</td>
17 <td>Initial state</td>
18 <td>Input</td>
19 <td>Expected output</td>
20 <td>Actual output</td>
21 <td>Pass/Fail</td>
22 </tr>
23 <tr>
24 <td><a name="CON001"/>CON001</td>
25 <td>LPC2148</td>
26 <td>ZY1000</td>
27 <td>Telnet connection</td>
28 <td>Power on, jtag target attached</td>
29 <td>On console, type<br><code>telnet ip port</code></td>
30 <td><code>Open On-Chip Debugger<br>></code></td>
31 <td><code>Open On-Chip Debugger<br>></code></td>
32 <td>PASS</td>
33 </tr>
34 <tr>
35 <td><a name="CON002"/>CON002</td>
36 <td>LPC2148</td>
37 <td>ZY1000</td>
38 <td>GDB server connection</td>
39 <td>Power on, jtag target attached</td>
40 <td>On GDB console, type<br><code>target remote ip:port</code></td>
41 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
42 <td><code>
43 (gdb) tar remo 10.0.0.73:3333<br>
44 Remote debugging using 10.0.0.73:3333<br>
45 0x00000000 in ?? ()<br>
46 </code></td>
47 <td>PASS</td>
48 </tr>
49 </table>
50
51 <H2>Reset</H2>
52 <table border=1>
53 <tr>
54 <td>ID</td>
55 <td>Target</td>
56 <td>Interface</td>
57 <td>Description</td>
58 <td>Initial state</td>
59 <td>Input</td>
60 <td>Expected output</td>
61 <td>Actual output</td>
62 <td>Pass/Fail</td>
63 </tr>
64 <tr>
65 <td><a name="RES001"/>RES001</td>
66 <td>LPC2148</td>
67 <td>ZY1000</td>
68 <td>Reset halt on a blank target</td>
69 <td>Erase all the content of the flash</td>
70 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
71 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
72 <td>
73 <code>
74 > mdw 0 32<br>
75 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
76 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
77 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
78 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
79 > reset halt<br>
80 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
81 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
82 target state: halted<br>
83 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
84 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
85 >
86 </code>
87 </td>
88 <td>PASS</td>
89 </tr>
90 <tr>
91 <td><a name="RES002"/>RES002</td>
92 <td>LPC2148</td>
93 <td>ZY1000</td>
94 <td>Reset init on a blank target</td>
95 <td>Erase all the content of the flash</td>
96 <td>Connect via the telnet interface and type <br><code>reset init</code></td>
97 <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
98 <td>
99 <code>
100 > reset init<br>
101 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
102 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
103 target state: halted<br>
104 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
105 cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
106 core state: ARM<br>
107 >
108 </code>
109 </td>
110 <td>PASS<br>
111 NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>
112 </tr>
113 <tr>
114 <td><a name="RES003"/>RES003</td>
115 <td>LPC2148</td>
116 <td>ZY1000</td>
117 <td>Reset after a power cycle of the target</td>
118 <td>Reset the target then power cycle the target</td>
119 <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
120 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
121 <td>
122 <code>
123 nsed nSRST asserted.<br>
124 nsed power dropout.<br>
125 nsed power restore.<br>
126 SRST took 186ms to deassert<br>
127 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
128 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
129 target state: halted<br>
130 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
131 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
132 core state: ARM<br>
133 > reset halt<br>
134 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
135 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
136 target state: halted<br>
137 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
138 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
139 >
140 </code>
141 </td>
142 <td>PASS</td>
143 </tr>
144 <tr>
145 <td><a name="RES004"/>RES004</td>
146 <td>LPC2148</td>
147 <td>ZY1000</td>
148 <td>Reset halt on a blank target where reset halt is supported</td>
149 <td>Erase all the content of the flash</td>
150 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
151 <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
152 <td>
153 <code>
154 > reset halt<br>
155 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
156 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
157 target state: halted<br>
158 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
159 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
160 >
161 </code>
162 </td>
163 <td>PASS</td>
164 </tr>
165 <tr>
166 <td><a name="RES005"/>RES005</td>
167 <td>LPC2148</td>
168 <td>ZY1000</td>
169 <td>Reset halt on a blank target using return clock</td>
170 <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
171 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
172 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
173 <td>
174 <code>
175 > jtag_khz 0<br>
176 RCLK - adaptive<br>
177 > reset init<br>
178 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
179 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
180 target state: halted<br>
181 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
182 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
183 core state: ARM<br>
184 >
185 </code>
186 </td>
187 <td>PASS</td>
188 </tr>
189 </table>
190
191 <H2>JTAG Speed</H2>
192 <table border=1>
193 <tr>
194 <td>ID</td>
195 <td>Target</td>
196 <td>ZY1000</td>
197 <td>Description</td>
198 <td>Initial state</td>
199 <td>Input</td>
200 <td>Expected output</td>
201 <td>Actual output</td>
202 <td>Pass/Fail</td>
203 </tr>
204 <tr>
205 <td><a name="SPD001"/>SPD001</td>
206 <td>LPC2148</td>
207 <td>ZY1000</td>
208 <td>16MHz on normal operation</td>
209 <td>Reset init the target according to RES002 </td>
210 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
211 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
212 <td>
213 <code>
214 > jtag_khz 16000<br>
215 jtag_speed 4 => JTAG clk=16.000000<br>
216 16000 kHz<br>
217 > reset halt<br>
218 JTAG scan chain interrogation failed: all zeroes<br>
219 Check JTAG interface, timings, target power, etc.<br>
220 error: -100<br>
221 Command handler execution failed<br>
222 in procedure 'reset' called at file "command.c", line 638<br>
223 called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
224 invalid mode value encountered 0<br>
225 cpsr contains invalid mode value - communication failure<br>
226 ThumbEE -- incomplete support<br>
227 target state: halted<br>
228 target halted in ThumbEE state due to debug-request, current mode: System<br>
229 cpsr: 0x1fffffff pc: 0xfffffffa<br>
230 invalid mode value encountered 0<br>
231 cpsr contains invalid mode value - communication failure<br>
232 target state: halted<br>
233 target halted in Thumb state due to debug-request, current mode: System<br>
234 cpsr: 0xc00003ff pc: 0xfffffff0<br>
235 invalid mode value encountered 0<br>
236 cpsr contains invalid mode value - communication failure<br>
237 invalid mode value encountered 0<br>
238 cpsr contains invalid mode value - communication failure<br>
239 invalid mode value encountered 0<br>
240 cpsr contains invalid mode value - communication failure<br>
241 invalid mode value encountered 0<br>
242 cpsr contains invalid mode value - communication failure<br>
243 ThumbEE -- incomplete support<br>
244 target state: halted<br>
245 target halted in ThumbEE state due to debug-request, current mode: System<br>
246 cpsr: 0xffffffff pc: 0xfffffffa<br>
247 >
248 </code>
249 </td>
250 <td><font color=red><b>FAIL</b></font></td>
251 </tr>
252 <tr>
253 <td><a name="SPD002"/>SPD002</td>
254 <td>LPC2148</td>
255 <td>ZY1000</td>
256 <td>8MHz on normal operation</td>
257 <td>Reset init the target according to RES002 </td>
258 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
259 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
260 <td>
261 <code>
262 > jtag_khz 8000<br>
263 jtag_speed 8 => JTAG clk=8.000000<br>
264 8000 kHz<br>
265 > reset halt<br>
266 JTAG scan chain interrogation failed: all zeroes<br>
267 Check JTAG interface, timings, target power, etc.<br>
268 error: -100<br>
269 Command handler execution failed<br>
270 in procedure 'reset' called at file "command.c", line 638<br>
271 called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
272 invalid mode value encountered 0<br>
273 cpsr contains invalid mode value - communication failure<br>
274 invalid mode value encountered 0<br>
275 cpsr contains invalid mode value - communication failure<br>
276 >
277 </code>
278 </td>
279 <td><font color=red><b>FAIL</b></font></td>
280 </tr>
281 <tr>
282 <td><a name="SPD003"/>SPD003</td>
283 <td>LPC2148</td>
284 <td>ZY1000</td>
285 <td>4MHz on normal operation</td>
286 <td>Reset init the target according to RES002 </td>
287 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
288 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
289 <td>
290 <code>
291 > jtag_khz 4000<br>
292 jtag_speed 16 => JTAG clk=4.000000<br>
293 4000 kHz<br>
294 > reset halt<br>
295 JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
296 JTAG tap: lpc2148.cpu UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
297 JTAG tap: lpc2148.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
298 Unexpected idcode after end of chain: 64 0x0000007f<br>
299 Unexpected idcode after end of chain: 160 0x0000007f<br>
300 Unexpected idcode after end of chain: 192 0x0000007f<br>
301 Unexpected idcode after end of chain: 320 0x0000007f<br>
302 Unexpected idcode after end of chain: 352 0x0000007f<br>
303 Unexpected idcode after end of chain: 384 0x0000007f<br>
304 Unexpected idcode after end of chain: 480 0x0000007f<br>
305 Unexpected idcode after end of chain: 512 0x0000007f<br>
306 Unexpected idcode after end of chain: 544 0x0000007f<br>
307 double-check your JTAG setup (interface, speed, missing TAPs, ...)<br>
308 error: -100<br>
309 Command handler execution failed<br>
310 in procedure 'reset' called at file "command.c", line 638<br>
311 called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
312 >
313 </code>
314 </td>
315 <td><font color=red><b>FAIL</b></font></td>
316 </tr>
317 <tr>
318 <td><a name="SPD004"/>SPD004</td>
319 <td>LPC2148</td>
320 <td>ZY1000</td>
321 <td>2MHz on normal operation</td>
322 <td>Reset init the target according to RES002 </td>
323 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
324 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
325 <td>
326 <code>
327 > jtag_khz 2000<br>
328 jtag_speed 32 => JTAG clk=2.000000<br>
329 2000 kHz<br>
330 > reset halt<br>
331 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
332 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
333 target state: halted<br>
334 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
335 cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
336 > mdw 0 32<br>
337 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
338 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
339 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
340 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
341 >
342 </code>
343 </td>
344 <td>PASS</td>
345 </tr>
346 <tr>
347 <td><a name="SPD005"/>SPD005</td>
348 <td>LPC2148</td>
349 <td>ZY1000</td>
350 <td>RCLK on normal operation</td>
351 <td>Reset init the target according to RES002 </td>
352 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
353 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
354 <td>
355 <code>
356 > jtag_khz 0<br>
357 RCLK - adaptive<br>
358 > mdw 0 32<br>
359 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
360 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
361 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
362 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
363 >
364 </code>
365 </td>
366 <td>PASS</td>
367 </tr>
368 </table>
369
370 <H2>Debugging</H2>
371 <table border=1>
372 <tr>
373 <td>ID</td>
374 <td>Target</td>
375 <td>Interface</td>
376 <td>Description</td>
377 <td>Initial state</td>
378 <td>Input</td>
379 <td>Expected output</td>
380 <td>Actual output</td>
381 <td>Pass/Fail</td>
382 </tr>
383 <tr>
384 <td><a name="DBG001"/>DBG001</td>
385 <td>LPC2148</td>
386 <td>ZY1000</td>
387 <td>Load is working</td>
388 <td>Reset init is working, RAM is accesible, GDB server is started</td>
389 <td>On the console of the OS: <br>
390 <code>arm-elf-gdb test_ram.elf</code><br>
391 <code>(gdb) target remote ip:port</code><br>
392 <code>(gdb) load</load>
393 </td>
394 <td>Load should return without error, typical output looks like:<br>
395 <code>
396 Loading section .text, size 0x14c lma 0x0<br>
397 Start address 0x40, load size 332<br>
398 Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
399 </code>
400 </td>
401 <td><code>
402 (gdb) load<br>
403 Loading section .text, size 0x16c lma 0x40000000<br>
404 Start address 0x40000040, load size 364<br>
405 Transfer rate: 32 KB/sec, 364 bytes/write.<br>
406 (gdb)
407 </code></td>
408 <td>PASS</td>
409 </tr>
410
411 <tr>
412 <td><a name="DBG002"/>DBG002</td>
413 <td>LPC2148</td>
414 <td>ZY1000</td>
415 <td>Software breakpoint</td>
416 <td>Load the test_ram.elf application, use instructions from GDB001</td>
417 <td>In the GDB console:<br>
418 <code>
419 (gdb) monitor gdb_breakpoint_override soft<br>
420 software breakpoints enabled<br>
421 (gdb) break main<br>
422 Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
423 (gdb) continue<br>
424 Continuing.
425 </code>
426 </td>
427 <td>The software breakpoint should be reached, a typical output looks like:<br>
428 <code>
429 target state: halted<br>
430 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
431 cpsr: 0x000000d3 pc: 0x000000ec<br>
432 <br>
433 Breakpoint 1, main () at src/main.c:71<br>
434 71 DWORD a = 1;
435 </code>
436 </td>
437 <td>
438 <code>
439 (gdb) monitor gdb_breakpoint_override soft<br>
440 force soft breakpoints<br>
441 Current language: auto<br>
442 The current source language is "auto; currently asm".<br>
443 (gdb) break main<br>
444 Breakpoint 1 at 0x4000010c: file src/main.c, line 71.<br>
445 (gdb) c<br>
446 Continuing.<br>
447 <br>
448 Breakpoint 1, main () at src/main.c:71<br>
449 71 DWORD a = 1;<br>
450 Current language: auto<br>
451 The current source language is "auto; currently c".<br>
452 (gdb)
453 </code>
454 </td>
455 <td>PASS</td>
456 </tr>
457 <tr>
458 <td><a name="DBG003"/>DBG003</td>
459 <td>LPC2148</td>
460 <td>ZY1000</td>
461 <td>Single step in a RAM application</td>
462 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
463 <td>In GDB, type <br><code>(gdb) step</code></td>
464 <td>The next instruction should be reached, typical output:<br>
465 <code>
466 (gdb) step<br>
467 target state: halted<br>
468 target halted in ARM state due to single step, current mode: Abort<br>
469 cpsr: 0x20000097 pc: 0x000000f0<br>
470 target state: halted<br>
471 target halted in ARM state due to single step, current mode: Abort<br>
472 cpsr: 0x20000097 pc: 0x000000f4<br>
473 72 DWORD b = 2;
474 </code>
475 </td>
476 <td>
477 <code>
478 (gdb) step<br>
479 72 DWORD b = 2;<br>
480 (gdb)
481 </code>
482 </td>
483 <td>PASS</td>
484 </tr>
485 <tr>
486 <td><a name="DBG004"/>DBG004</td>
487 <td>LPC2148</td>
488 <td>ZY1000</td>
489 <td>Software break points are working after a reset</td>
490 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
491 <td>In GDB, type <br><code>
492 (gdb) monitor reset init<br>
493 (gdb) load<br>
494 (gdb) continue<br>
495 </code></td>
496 <td>The breakpoint should be reached, typical output:<br>
497 <code>
498 target state: halted<br>
499 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
500 cpsr: 0x000000d3 pc: 0x000000ec<br>
501 <br>
502 Breakpoint 1, main () at src/main.c:71<br>
503 71 DWORD a = 1;
504 </code>
505 </td>
506 <td><code>
507 (gdb) moni reset init<br>
508 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
509 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
510 target state: halted<br>
511 target halted in Thumb state due to debug-request, current mode: Supervisor<br>
512 cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
513 core state: ARM<br>
514 (gdb) load<br>
515 Loading section .text, size 0x16c lma 0x40000000<br>
516 Start address 0x40000040, load size 364<br>
517 Transfer rate: 27 KB/sec, 364 bytes/write.<br>
518 (gdb) c<br>
519 Continuing.<br>
520 <br>
521 Breakpoint 1, main () at src/main.c:71<br>
522 71 DWORD a = 1;<br>
523 (gdb)
524 </code></td>
525 <td>PASS</td>
526 </tr>
527 <tr>
528 <td><a name="DBG005"/>DBG005</td>
529 <td>LPC2148</td>
530 <td>ZY1000</td>
531 <td>Hardware breakpoint</td>
532 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
533 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
534 <code>
535 (gdb) monitor reset init<br>
536 (gdb) load<br>
537 Loading section .text, size 0x194 lma 0x100000<br>
538 Start address 0x100040, load size 404<br>
539 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
540 (gdb) monitor gdb_breakpoint_override hard<br>
541 force hard breakpoints<br>
542 (gdb) break main<br>
543 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
544 (gdb) continue<br>
545 </code>
546 </td>
547 <td>The breakpoint should be reached, typical output:<br>
548 <code>
549 Continuing.<br>
550 <br>
551 Breakpoint 1, main () at src/main.c:69<br>
552 69 DWORD a = 1;<br>
553 </code>
554 </td>
555 <td>
556 <code>
557 (gdb) monitor gdb_breakpoint_override hard<br>
558 force hard breakpoints<br>
559 (gdb) break main<br>
560 Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
561 (gdb) continue<br>
562 Continuing.<br>
563 Note: automatically using hardware breakpoints for read-only addresses.<br>
564 <br>
565 Breakpoint 1, main () at src/main.c:71<br>
566 71 DWORD a = 1;<br>
567 Current language: auto<br>
568 The current source language is "auto; currently c".<br>
569 (gdb)
570 </code>
571 </td>
572 <td>PASS <font color=red>NOTE: This test is failing from time to time, not able to describe a cause</font></td>
573 </tr>
574 <tr>
575 <td><a name="DBG006"/>DBG006</td>
576 <td>LPC2148</td>
577 <td>ZY1000</td>
578 <td>Hardware breakpoint is set after a reset</td>
579 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
580 <td>In GDB, type <br>
581 <code>
582 (gdb) monitor reset<br>
583 (gdb) monitor reg pc 0x100000<br>
584 pc (/32): 0x00100000<br>
585 (gdb) continue
586 </code><br>
587 where the value inserted in PC is the start address of the application
588 </td>
589 <td>The breakpoint should be reached, typical output:<br>
590 <code>
591 Continuing.<br>
592 <br>
593 Breakpoint 1, main () at src/main.c:69<br>
594 69 DWORD a = 1;<br>
595 </code>
596 </td>
597 <td>
598 <code>
599 (gdb) monitor reset init<br>
600 JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
601 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
602 target state: halted<br>
603 target halted in ARM state due to debug-request, current mode: Supervisor<br>
604 cpsr: 0x60000013 pc: 0x00000160<br>
605 core state: ARM<br>
606 (gdb) monitor reg pc 0x40<br>
607 pc (/32): 0x00000040<br>
608 (gdb) continue<br>
609 Continuing.<br>
610 <br>
611 Breakpoint 1, main () at src/main.c:71<br>
612 71 DWORD a = 1;<br>
613 (gdb)
614 </code>
615 </td>
616 <td>PASS</td>
617 </tr>
618 <tr>
619 <td><a name="DBG007"/>DBG007</td>
620 <td>LPC2148</td>
621 <td>ZY1000</td>
622 <td>Single step in ROM</td>
623 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
624 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
625 <code>
626 (gdb) monitor reset<br>
627 (gdb) load<br>
628 Loading section .text, size 0x194 lma 0x100000<br>
629 Start address 0x100040, load size 404<br>
630 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
631 (gdb) monitor gdb_breakpoint_override hard<br>
632 force hard breakpoints<br>
633 (gdb) break main<br>
634 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
635 (gdb) continue<br>
636 Continuing.<br>
637 <br>
638 Breakpoint 1, main () at src/main.c:69<br>
639 69 DWORD a = 1;<br>
640 (gdb) step
641 </code>
642 </td>
643 <td>The breakpoint should be reached, typical output:<br>
644 <code>
645 target state: halted<br>
646 target halted in ARM state due to single step, current mode: Supervisor<br>
647 cpsr: 0x60000013 pc: 0x0010013c<br>
648 70 DWORD b = 2;<br>
649 </code>
650 </td>
651 <td><code>
652 (gdb) load<br>
653 Loading section .text, size 0x16c lma 0x0<br>
654 Start address 0x40, load size 364<br>
655 Transfer rate: 637 bytes/sec, 364 bytes/write.<br>
656 (gdb) monitor gdb_breakpoint_override hard<br>
657 force hard breakpoints<br>
658 Current language: auto<br>
659 The current source language is "auto; currently asm".<br>
660 (gdb) break main<br>
661 Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
662 (gdb) continue<br>
663 Continuing.<br>
664 Note: automatically using hardware breakpoints for read-only addresses.<br>
665 <br>
666 Breakpoint 1, main () at src/main.c:71<br>
667 71 DWORD a = 1;<br>
668 Current language: auto<br>
669 The current source language is "auto; currently c".<br>
670 (gdb) step<br>
671 72 DWORD b = 2;<br>
672 (gdb)
673
674 </code></td>
675 <td>PASS</td>
676 </tr>
677 </table>
678
679 <H2>RAM access</H2>
680 Note: these tests are not designed to test/debug the target, but to test functionalities!
681 <table border=1>
682 <tr>
683 <td>ID</td>
684 <td>Target</td>
685 <td>Interface</td>
686 <td>Description</td>
687 <td>Initial state</td>
688 <td>Input</td>
689 <td>Expected output</td>
690 <td>Actual output</td>
691 <td>Pass/Fail</td>
692 </tr>
693 <tr>
694 <td><a name="RAM001"/>RAM001</td>
695 <td>LPC2148</td>
696 <td>ZY1000</td>
697 <td>32 bit Write/read RAM</td>
698 <td>Reset init is working</td>
699 <td>On the telnet interface<br>
700 <code> > mww ram_address 0xdeadbeef 16<br>
701 > mdw ram_address 32
702 </code>
703 </td>
704 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
705 <code>
706 > mww 0x0 0xdeadbeef 16<br>
707 > mdw 0x0 32<br>
708 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
709 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
710 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
711 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
712 </code>
713 </td>
714 <td><code>
715 > mww 0x40000000 0xdeadbeef 16<br>
716 > mdw 0x40000000 32<br>
717 0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
718 0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
719 0x40000040: e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000<br>
720 0x40000060: e321f0db e59fd07c e321f0d7 e59fd078 e321f0d1 e59fd074 e321f0d2 e59fd070<br>
721 >
722 </code></td>
723 <td>PASS</td>
724 </tr>
725 <tr>
726 <td><a name="RAM002"/>RAM002</td>
727 <td>LPC2148</td>
728 <td>ZY1000</td>
729 <td>16 bit Write/read RAM</td>
730 <td>Reset init is working</td>
731 <td>On the telnet interface<br>
732 <code> > mwh ram_address 0xbeef 16<br>
733 > mdh ram_address 32
734 </code>
735 </td>
736 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
737 <code>
738 > mwh 0x0 0xbeef 16<br>
739 > mdh 0x0 32<br>
740 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
741 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
742 >
743 </code>
744 </td>
745 <td><code>
746 > mwh 0x40000000 0xbeef 16<br>
747 > mdh 0x40000000 32<br>
748 0x40000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
749 0x40000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
750 >
751 </code></td>
752 <td>PASS</td>
753 </tr>
754 <tr>
755 <td><a name="RAM003"/>RAM003</td>
756 <td>LPC2148</td>
757 <td>ZY1000</td>
758 <td>8 bit Write/read RAM</td>
759 <td>Reset init is working</td>
760 <td>On the telnet interface<br>
761 <code> > mwb ram_address 0xab 16<br>
762 > mdb ram_address 32
763 </code>
764 </td>
765 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
766 <code>
767 > mwb ram_address 0xab 16<br>
768 > mdb ram_address 32<br>
769 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
770 >
771 </code>
772 </td>
773 <td><code>
774 > mwb 0x40000000 0xab 16
775 > mdb 0x40000000 32
776 0x40000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
777 >
778
779 </code></td>
780 <td>PASS</td>
781 </tr>
782 </table>
783
784
785
786 <H2>Flash access</H2>
787 <table border=1>
788 <tr>
789 <td>ID</td>
790 <td>Target</td>
791 <td>Interface</td>
792 <td>Description</td>
793 <td>Initial state</td>
794 <td>Input</td>
795 <td>Expected output</td>
796 <td>Actual output</td>
797 <td>Pass/Fail</td>
798 </tr>
799 <tr>
800 <td><a name="FLA001"/>FLA001</td>
801 <td>LPC2148</td>
802 <td>ZY1000</td>
803 <td>Flash probe</td>
804 <td>Reset init is working</td>
805 <td>On the telnet interface:<br>
806 <code> > flash probe 0</code>
807 </td>
808 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
809 <code>flash 'ecosflash' found at 0x01000000</code>
810 </td>
811 <td>
812 <code>
813 > flash probe 0<br>
814 flash 'lpc2000' found at 0x00000000
815 </code>
816 </td>
817 <td>PASS</td>
818 </tr>
819 <tr>
820 <td><a name="FLA002"/>FLA002</td>
821 <td>LPC2148</td>
822 <td>ZY1000</td>
823 <td>flash fillw</td>
824 <td>Reset init is working, flash is probed</td>
825 <td>On the telnet interface<br>
826 <code> > flash fillw 0x1000000 0xdeadbeef 16
827 </code>
828 </td>
829 <td>The commands should execute without error. The output looks like:<br>
830 <code>
831 wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
832 </code><br>
833 To verify the contents of the flash:<br>
834 <code>
835 > mdw 0x1000000 32<br>
836 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
837 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
838 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
839 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
840 </code>
841 </td>
842 <td><code>
843 > flash fillw 0x0 0xdeadbeef 16<br>
844 Verification will fail since checksum in image (0xdeadbeef) to be written to flash is different from calculated vector checksum (0xe93fc777).<br>
845 To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.<br>
846 wrote 64 bytes to 0x00000000 in 0.040000s (1.563 kb/s)<br>
847 > mdw 0 32<br>
848 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef e93fc777 deadbeef deadbeef<br>
849 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
850 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
851 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
852 >
853 </code></td>
854 <td><font color=red>FAIL</font></td>
855 </tr>
856 <tr>
857 <td><a name="FLA003"/>FLA003</td>
858 <td>LPC2148</td>
859 <td>ZY1000</td>
860 <td>Flash erase</td>
861 <td>Reset init is working, flash is probed</td>
862 <td>On the telnet interface<br>
863 <code> > flash erase_address 0x1000000 0x2000
864 </code>
865 </td>
866 <td>The commands should execute without error.<br>
867 <code>
868 erased address 0x01000000 length 8192 in 4.970000s
869 </code>
870 To check that the flash has been erased, read at different addresses. The result should always be 0xff.
871 <code>
872 > mdw 0x1000000 32<br>
873 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
874 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
875 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
876 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
877 </code>
878 </td>
879 <td><code>
880 > flash erase_address 0 0x2000<br>
881 erased address 0x00000000 (length 8192) in 0.510000s (15.686 kb/s)<br>
882 > mdw 0 32<br>
883 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
884 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
885 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
886 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
887 >
888 </code></td>
889 <td>PASS</td>
890
891 </tr>
892 <tr>
893 <td><a name="FLA004"/>FLA004</td>
894 <td>LPC2148</td>
895 <td>ZY1000</td>
896 <td>Loading to flash from GDB</td>
897 <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
898 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
899 <code>
900 (gdb) target remote ip:port<br>
901 (gdb) monitor reset<br>
902 (gdb) load<br>
903 Loading section .text, size 0x194 lma 0x100000<br>
904 Start address 0x100040, load size 404<br>
905 Transfer rate: 179 bytes/sec, 404 bytes/write.
906 (gdb) monitor verify_image path_to_elf_file
907 </code>
908 </td>
909 <td>The output should look like:<br>
910 <code>
911 verified 404 bytes in 5.060000s
912 </code><br>
913 The failure message is something like:<br>
914 <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
915 </td>
916 <td>
917 <code>
918 (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
919 checksum mismatch - attempting binary compare<br>
920 Verify operation failed address 0x00000014. Was 0x58 instead of 0x60<br>
921 <br>
922 Command handler execution failed<br>
923 in procedure 'verify_image' called at file "command.c", line 647<br>
924 called at file "command.c", line 361<br>
925 (gdb)
926 </code>
927 </td>
928 <td><font color=red>FAIL</font></td>
929 </tr>
930 </table>
931
932 </body>
933 </html>