src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/log.h>
  25 #include "target.h"
  26 #include "armv4_5_mmu.h"
  27
  28
  29 int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, int *domain, uint32_t *ap, uint32_t *val)
  30 {
  31         uint32_t first_lvl_descriptor = 0x0;
  32         uint32_t second_lvl_descriptor = 0x0;
  33         uint32_t ttb = armv4_5_mmu->get_ttb(target);
  34         int retval;
  35
  36         retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  37                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  38                 4, 1, (uint8_t*)&first_lvl_descriptor);
  39         if (retval != ERROR_OK)
  40           return retval;
  41         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  42
  43         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  44
  45         if ((first_lvl_descriptor & 0x3) == 0)
  46         {
  47                 LOG_ERROR("Address translation failure");
  48                 return ERROR_TARGET_TRANSLATION_FAULT;
  49         }
  50
  51         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  52         {
  53                 LOG_ERROR("Address translation failure");
  54                 return ERROR_TARGET_TRANSLATION_FAULT;
  55         }
  56
  57         /* domain is always specified in bits 8-5 */
  58         *domain = (first_lvl_descriptor & 0x1e0) >> 5;
  59
  60         if ((first_lvl_descriptor & 0x3) == 2)
  61         {
  62                 /* section descriptor */
  63                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  64                 *ap = (first_lvl_descriptor & 0xc00) >> 10;
  65                 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  66                 return ERROR_OK;
  67         }
  68
  69         if ((first_lvl_descriptor & 0x3) == 1)
  70         {
  71                 /* coarse page table */
  72                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  73                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  74                         4, 1, (uint8_t*)&second_lvl_descriptor);
  75                 if (retval != ERROR_OK)
  76                         return retval;
  77         }
  78         else if ((first_lvl_descriptor & 0x3) == 3)
  79         {
  80                 /* fine page table */
  81                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  82                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  83                         4, 1, (uint8_t*)&second_lvl_descriptor);
  84                 if (retval != ERROR_OK)
  85                         return retval;
  86         }
  87
  88         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  89
  90         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  91
  92         if ((second_lvl_descriptor & 0x3) == 0)
  93         {
  94                 LOG_ERROR("Address translation failure");
  95                 return ERROR_TARGET_TRANSLATION_FAULT;
  96         }
  97
  98         /* cacheable/bufferable is always specified in bits 3-2 */
  99         *cb = (second_lvl_descriptor & 0xc) >> 2;
 100
 101         if ((second_lvl_descriptor & 0x3) == 1)
 102         {
 103                 /* large page descriptor */
 104                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 105                 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 106                 return ERROR_OK;
 107         }
 108
 109         if ((second_lvl_descriptor & 0x3) == 2)
 110         {
 111                 /* small page descriptor */
 112                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 113                 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 114                 return ERROR_OK;
 115         }
 116
 117         if ((second_lvl_descriptor & 0x3) == 3)
 118         {
 119                 /* tiny page descriptor */
 120                 *ap = (second_lvl_descriptor & 0x30) >> 4;
 121                 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 122                 return ERROR_OK;
 123         }
 124
 125         /* should not happen */
 126         LOG_ERROR("Address translation failure");
 127         return ERROR_TARGET_TRANSLATION_FAULT;
 128 }
 129
 130 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 131 {
 132         int retval;
 133
 134         if (target->state != TARGET_HALTED)
 135                 return ERROR_TARGET_NOT_HALTED;
 136
 137         /* disable MMU and data (or unified) cache */
 138         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 139
 140         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 141
 142         /* reenable MMU / cache */
 143         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 144                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 145                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 146
 147         return retval;
 148 }
 149
 150 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 151 {
 152         int retval;
 153
 154         if (target->state != TARGET_HALTED)
 155                 return ERROR_TARGET_NOT_HALTED;
 156
 157         /* disable MMU and data (or unified) cache */
 158         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 159
 160         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 161
 162         /* reenable MMU / cache */
 163         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 164                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 165                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 166
 167         return retval;
 168 }