1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007-2009 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * Copyright (C) 2009 by David Brownell *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
30 ***************************************************************************/
35 #include "breakpoints.h"
36 #include "embeddedice.h"
37 #include "target_request.h"
39 #include <helper/time_support.h>
40 #include "arm_simulator.h"
41 #include "arm_semihosting.h"
42 #include "algorithm.h"
49 * Hold common code supporting the ARM7 and ARM9 core generations.
51 * While the ARM core implementations evolved substantially during these
52 * two generations, they look quite similar from the JTAG perspective.
53 * Both have similar debug facilities, based on the same two scan chains
54 * providing access to the core and to an EmbeddedICE module. Both can
55 * support similar ETM and ETB modules, for tracing. And both expose
56 * what could be viewed as "ARM Classic", with multiple processor modes,
57 * shadowed registers, and support for the Thumb instruction set.
59 * Processor differences include things like presence or absence of MMU
60 * and cache, pipeline sizes, use of a modified Harvard Architecure
61 * (with separate instruction and data busses from the CPU), support
62 * for cpu clock gating during idle, and more.
65 static int arm7_9_debug_entry(struct target
*target
);
68 * Clear watchpoints for an ARM7/9 target.
70 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
71 * @return JTAG error status after executing queue
73 static int arm7_9_clear_watchpoints(struct arm7_9_common
*arm7_9
)
76 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
77 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
78 arm7_9
->sw_breakpoint_count
= 0;
79 arm7_9
->sw_breakpoints_added
= 0;
81 arm7_9
->wp1_used
= arm7_9
->wp1_used_default
;
82 arm7_9
->wp_available
= arm7_9
->wp_available_max
;
84 return jtag_execute_queue();
88 * Assign a watchpoint to one of the two available hardware comparators in an
89 * ARM7 or ARM9 target.
91 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
92 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
94 static void arm7_9_assign_wp(struct arm7_9_common
*arm7_9
, struct breakpoint
*breakpoint
)
96 if (!arm7_9
->wp0_used
)
100 arm7_9
->wp_available
--;
102 else if (!arm7_9
->wp1_used
)
104 arm7_9
->wp1_used
= 1;
106 arm7_9
->wp_available
--;
110 LOG_ERROR("BUG: no hardware comparator available");
112 LOG_DEBUG("BPID: %d (0x%08" PRIx32
") using hw wp: %d",
113 breakpoint
->unique_id
,
119 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
121 * @param arm7_9 Pointer to common struct for ARM7/9 targets
122 * @return Error codes if there is a problem finding a watchpoint or the result
123 * of executing the JTAG queue
125 static int arm7_9_set_software_breakpoints(struct arm7_9_common
*arm7_9
)
127 if (arm7_9
->sw_breakpoints_added
)
131 if (arm7_9
->wp_available
< 1)
133 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
136 arm7_9
->wp_available
--;
138 /* pick a breakpoint unit */
139 if (!arm7_9
->wp0_used
)
141 arm7_9
->sw_breakpoints_added
= 1;
142 arm7_9
->wp0_used
= 3;
143 } else if (!arm7_9
->wp1_used
)
145 arm7_9
->sw_breakpoints_added
= 2;
146 arm7_9
->wp1_used
= 3;
150 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
154 if (arm7_9
->sw_breakpoints_added
== 1)
156 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
162 else if (arm7_9
->sw_breakpoints_added
== 2)
164 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
165 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
166 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
167 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
168 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
172 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
175 LOG_DEBUG("SW BP using hw wp: %d",
176 arm7_9
->sw_breakpoints_added
);
178 return jtag_execute_queue();
182 * Setup the common pieces for an ARM7/9 target after reset or on startup.
184 * @param target Pointer to an ARM7/9 target to setup
185 * @return Result of clearing the watchpoints on the target
187 int arm7_9_setup(struct target
*target
)
189 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
191 return arm7_9_clear_watchpoints(arm7_9
);
195 * Set either a hardware or software breakpoint on an ARM7/9 target. The
196 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
197 * might have erased the values in Embedded ICE.
199 * @param target Pointer to the target device to set the breakpoints on
200 * @param breakpoint Pointer to the breakpoint to be set
201 * @return For hardware breakpoints, this is the result of executing the JTAG
202 * queue. For software breakpoints, this will be the status of the
203 * required memory reads and writes
205 int arm7_9_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
207 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
208 int retval
= ERROR_OK
;
210 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
", Type: %d" ,
211 breakpoint
->unique_id
,
215 if (target
->state
!= TARGET_HALTED
)
217 LOG_WARNING("target not halted");
218 return ERROR_TARGET_NOT_HALTED
;
221 if (breakpoint
->type
== BKPT_HARD
)
223 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
224 uint32_t mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
226 /* reassign a hw breakpoint */
227 if (breakpoint
->set
== 0)
229 arm7_9_assign_wp(arm7_9
, breakpoint
);
232 if (breakpoint
->set
== 1)
234 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
235 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
236 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
237 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
238 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
240 else if (breakpoint
->set
== 2)
242 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
243 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
244 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
245 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
246 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
250 LOG_ERROR("BUG: no hardware comparator available");
254 retval
= jtag_execute_queue();
256 else if (breakpoint
->type
== BKPT_SOFT
)
258 /* did we already set this breakpoint? */
262 if (breakpoint
->length
== 4)
264 uint32_t verify
= 0xffffffff;
265 /* keep the original instruction in target endianness */
266 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
270 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
271 if ((retval
= target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
)) != ERROR_OK
)
276 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
280 if (verify
!= arm7_9
->arm_bkpt
)
282 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
288 uint16_t verify
= 0xffff;
289 /* keep the original instruction in target endianness */
290 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
294 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
295 if ((retval
= target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
)) != ERROR_OK
)
300 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
304 if (verify
!= arm7_9
->thumb_bkpt
)
306 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
311 if ((retval
= arm7_9_set_software_breakpoints(arm7_9
)) != ERROR_OK
)
314 arm7_9
->sw_breakpoint_count
++;
323 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
324 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
325 * will be updated. Otherwise, the software breakpoint will be restored to its
326 * original instruction if it hasn't already been modified.
328 * @param target Pointer to ARM7/9 target to unset the breakpoint from
329 * @param breakpoint Pointer to breakpoint to be unset
330 * @return For hardware breakpoints, this is the result of executing the JTAG
331 * queue. For software breakpoints, this will be the status of the
332 * required memory reads and writes
334 int arm7_9_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
336 int retval
= ERROR_OK
;
337 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
339 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
,
340 breakpoint
->unique_id
,
341 breakpoint
->address
);
343 if (!breakpoint
->set
)
345 LOG_WARNING("breakpoint not set");
349 if (breakpoint
->type
== BKPT_HARD
)
351 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
352 breakpoint
->unique_id
,
354 if (breakpoint
->set
== 1)
356 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
357 arm7_9
->wp0_used
= 0;
358 arm7_9
->wp_available
++;
360 else if (breakpoint
->set
== 2)
362 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
363 arm7_9
->wp1_used
= 0;
364 arm7_9
->wp_available
++;
366 retval
= jtag_execute_queue();
371 /* restore original instruction (kept in target endianness) */
372 if (breakpoint
->length
== 4)
374 uint32_t current_instr
;
375 /* check that user program as not modified breakpoint instruction */
376 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
380 if (current_instr
== arm7_9
->arm_bkpt
)
381 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
388 uint16_t current_instr
;
389 /* check that user program as not modified breakpoint instruction */
390 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
394 if (current_instr
== arm7_9
->thumb_bkpt
)
395 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
401 if (--arm7_9
->sw_breakpoint_count
==0)
403 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
404 if (arm7_9
->sw_breakpoints_added
== 1)
406 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0);
408 else if (arm7_9
->sw_breakpoints_added
== 2)
410 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0);
421 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
422 * dangling breakpoints and that the desired breakpoint can be added.
424 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
425 * @param breakpoint Pointer to the breakpoint to be added
426 * @return An error status if there is a problem adding the breakpoint or the
427 * result of setting the breakpoint
429 int arm7_9_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
431 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
433 if (arm7_9
->breakpoint_count
== 0)
435 /* make sure we don't have any dangling breakpoints. This is vital upon
436 * GDB connect/disconnect
438 arm7_9_clear_watchpoints(arm7_9
);
441 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
443 LOG_INFO("no watchpoint unit available for hardware breakpoint");
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
447 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
449 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
450 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
453 if (breakpoint
->type
== BKPT_HARD
)
455 arm7_9_assign_wp(arm7_9
, breakpoint
);
458 arm7_9
->breakpoint_count
++;
460 return arm7_9_set_breakpoint(target
, breakpoint
);
464 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
465 * dangling breakpoints and updates available watchpoints if it is a hardware
468 * @param target Pointer to the target to have a breakpoint removed
469 * @param breakpoint Pointer to the breakpoint to be removed
470 * @return Error status if there was a problem unsetting the breakpoint or the
471 * watchpoints could not be cleared
473 int arm7_9_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
475 int retval
= ERROR_OK
;
476 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
478 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
483 if (breakpoint
->type
== BKPT_HARD
)
484 arm7_9
->wp_available
++;
486 arm7_9
->breakpoint_count
--;
487 if (arm7_9
->breakpoint_count
== 0)
489 /* make sure we don't have any dangling breakpoints */
490 if ((retval
= arm7_9_clear_watchpoints(arm7_9
)) != ERROR_OK
)
500 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
501 * considered a bug to call this function when there are no available watchpoint
504 * @param target Pointer to an ARM7/9 target to set a watchpoint on
505 * @param watchpoint Pointer to the watchpoint to be set
506 * @return Error status if watchpoint set fails or the result of executing the
509 int arm7_9_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
511 int retval
= ERROR_OK
;
512 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
516 mask
= watchpoint
->length
- 1;
518 if (target
->state
!= TARGET_HALTED
)
520 LOG_WARNING("target not halted");
521 return ERROR_TARGET_NOT_HALTED
;
524 if (watchpoint
->rw
== WPT_ACCESS
)
529 if (!arm7_9
->wp0_used
)
531 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
532 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
533 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
534 if (watchpoint
->mask
!= 0xffffffffu
)
535 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
536 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
537 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
539 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
544 arm7_9
->wp0_used
= 2;
546 else if (!arm7_9
->wp1_used
)
548 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
549 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
550 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
551 if (watchpoint
->mask
!= 0xffffffffu
)
552 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
553 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
554 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
556 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
561 arm7_9
->wp1_used
= 2;
565 LOG_ERROR("BUG: no hardware comparator available");
573 * Unset an existing watchpoint and clear the used watchpoint unit.
575 * @param target Pointer to the target to have the watchpoint removed
576 * @param watchpoint Pointer to the watchpoint to be removed
577 * @return Error status while trying to unset the watchpoint or the result of
578 * executing the JTAG queue
580 int arm7_9_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
582 int retval
= ERROR_OK
;
583 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
585 if (target
->state
!= TARGET_HALTED
)
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED
;
591 if (!watchpoint
->set
)
593 LOG_WARNING("breakpoint not set");
597 if (watchpoint
->set
== 1)
599 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
600 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
604 arm7_9
->wp0_used
= 0;
606 else if (watchpoint
->set
== 2)
608 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
609 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
613 arm7_9
->wp1_used
= 0;
621 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
622 * available, an error response is returned.
624 * @param target Pointer to the ARM7/9 target to add a watchpoint to
625 * @param watchpoint Pointer to the watchpoint to be added
626 * @return Error status while trying to add the watchpoint
628 int arm7_9_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
630 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
632 if (arm7_9
->wp_available
< 1)
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
637 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
639 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
642 arm7_9
->wp_available
--;
648 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
649 * the used watchpoint unit will be reopened.
651 * @param target Pointer to the target to remove a watchpoint from
652 * @param watchpoint Pointer to the watchpoint to be removed
653 * @return Result of trying to unset the watchpoint
655 int arm7_9_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
657 int retval
= ERROR_OK
;
658 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
662 if ((retval
= arm7_9_unset_watchpoint(target
, watchpoint
)) != ERROR_OK
)
668 arm7_9
->wp_available
++;
674 * Restarts the target by sending a RESTART instruction and moving the JTAG
675 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
676 * asserted by the processor.
678 * @param target Pointer to target to issue commands to
679 * @return Error status if there is a timeout or a problem while executing the
682 int arm7_9_execute_sys_speed(struct target
*target
)
685 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
686 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
687 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
689 /* set RESTART instruction */
690 jtag_set_end_state(TAP_IDLE
);
691 if (arm7_9
->need_bypass_before_restart
) {
692 arm7_9
->need_bypass_before_restart
= 0;
693 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
695 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
697 long long then
= timeval_ms();
699 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
701 /* read debug status register */
702 embeddedice_read_reg(dbg_stat
);
703 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
705 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
706 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
708 if (debug_level
>= 3)
718 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32
"", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
719 return ERROR_TARGET_TIMEOUT
;
726 * Restarts the target by sending a RESTART instruction and moving the JTAG
727 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
728 * waiting until they are.
730 * @param target Pointer to the target to issue commands to
731 * @return Always ERROR_OK
733 int arm7_9_execute_fast_sys_speed(struct target
*target
)
736 static uint8_t check_value
[4], check_mask
[4];
738 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
739 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
740 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
742 /* set RESTART instruction */
743 jtag_set_end_state(TAP_IDLE
);
744 if (arm7_9
->need_bypass_before_restart
) {
745 arm7_9
->need_bypass_before_restart
= 0;
746 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
748 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
752 /* check for DBGACK and SYSCOMP set (others don't care) */
754 /* NB! These are constants that must be available until after next jtag_execute() and
755 * we evaluate the values upon first execution in lieu of setting up these constants
756 * during early setup.
758 buf_set_u32(check_value
, 0, 32, 0x9);
759 buf_set_u32(check_mask
, 0, 32, 0x9);
763 /* read debug status register */
764 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_mask
);
770 * Get some data from the ARM7/9 target.
772 * @param target Pointer to the ARM7/9 target to read data from
773 * @param size The number of 32bit words to be read
774 * @param buffer Pointer to the buffer that will hold the data
775 * @return The result of receiving data from the Embedded ICE unit
777 int arm7_9_target_request_data(struct target
*target
, uint32_t size
, uint8_t *buffer
)
779 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
780 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
782 int retval
= ERROR_OK
;
785 data
= malloc(size
* (sizeof(uint32_t)));
787 retval
= embeddedice_receive(jtag_info
, data
, size
);
789 /* return the 32-bit ints in the 8-bit array */
790 for (i
= 0; i
< size
; i
++)
792 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
801 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
802 * target is running and the DCC control register has the W bit high, this will
803 * execute the request on the target.
805 * @param priv Void pointer expected to be a struct target pointer
806 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
807 * from the Embedded ICE unit
809 int arm7_9_handle_target_request(void *priv
)
811 int retval
= ERROR_OK
;
812 struct target
*target
= priv
;
813 if (!target_was_examined(target
))
815 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
816 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
817 struct reg
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
819 if (!target
->dbg_msg_enabled
)
822 if (target
->state
== TARGET_RUNNING
)
824 /* read DCC control register */
825 embeddedice_read_reg(dcc_control
);
826 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
832 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
836 if ((retval
= embeddedice_receive(jtag_info
, &request
, 1)) != ERROR_OK
)
840 if ((retval
= target_request(target
, request
)) != ERROR_OK
)
851 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
852 * is manipulated to the right halted state based on its current state. This is
856 * <tr><th > State</th><th > Action</th></tr>
857 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
858 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
859 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
860 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
863 * If the target does not end up in the halted state, a warning is produced. If
864 * DBGACK is cleared, then the target is expected to either be running or
867 * @param target Pointer to the ARM7/9 target to poll
868 * @return ERROR_OK or an error status if a command fails
870 int arm7_9_poll(struct target
*target
)
873 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
874 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
876 /* read debug status register */
877 embeddedice_read_reg(dbg_stat
);
878 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
883 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
885 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
886 if (target
->state
== TARGET_UNKNOWN
)
888 /* Starting OpenOCD with target in debug-halt */
889 target
->state
= TARGET_RUNNING
;
890 LOG_DEBUG("DBGACK already set during server startup.");
892 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
894 target
->state
= TARGET_HALTED
;
896 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
899 if (arm_semihosting(target
, &retval
) != 0)
902 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
907 if (target
->state
== TARGET_DEBUG_RUNNING
)
909 target
->state
= TARGET_HALTED
;
910 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
913 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
)) != ERROR_OK
)
918 if (target
->state
!= TARGET_HALTED
)
920 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target
->state
);
925 if (target
->state
!= TARGET_DEBUG_RUNNING
)
926 target
->state
= TARGET_RUNNING
;
933 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
934 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
935 * affected) completely stop the JTAG clock while the core is held in reset
936 * (SRST). It isn't possible to program the halt condition once reset is
937 * asserted, hence a hook that allows the target to set up its reset-halt
938 * condition is setup prior to asserting reset.
940 * @param target Pointer to an ARM7/9 target to assert reset on
941 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
943 int arm7_9_assert_reset(struct target
*target
)
945 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
946 enum reset_types jtag_reset_config
= jtag_get_reset_config();
947 bool use_event
= false;
949 LOG_DEBUG("target->state: %s",
950 target_state_name(target
));
952 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
954 else if (!(jtag_reset_config
& RESET_HAS_SRST
)) {
955 LOG_ERROR("%s: how to reset?", target_name(target
));
959 /* At this point trst has been asserted/deasserted once. We would
960 * like to program EmbeddedICE while SRST is asserted, instead of
961 * depending on SRST to leave that module alone. However, many CPUs
962 * gate the JTAG clock while SRST is asserted; or JTAG may need
963 * clock stability guarantees (adaptive clocking might help).
965 * So we assume JTAG access during SRST is off the menu unless it's
966 * been specifically enabled.
968 bool srst_asserted
= false;
971 && !(jtag_reset_config
& RESET_SRST_PULLS_TRST
)
972 && (jtag_reset_config
& RESET_SRST_NO_GATING
))
974 jtag_add_reset(0, 1);
975 srst_asserted
= true;
978 if (target
->reset_halt
)
981 * For targets that don't support communication while SRST is
982 * asserted, we need to set up the reset vector catch first.
984 * When we use TRST+SRST and that's equivalent to a power-up
985 * reset, these settings may well be reset anyway; so setting
986 * them here won't matter.
988 if (arm7_9
->has_vector_catch
)
990 /* program vector catch register to catch reset */
991 embeddedice_write_reg(&arm7_9
->eice_cache
992 ->reg_list
[EICE_VEC_CATCH
], 0x1);
994 /* extra runtest added as issues were found with
995 * certain ARM9 cores (maybe more) - AT91SAM9260
998 jtag_add_runtest(1, jtag_get_end_state());
1002 /* program watchpoint unit to match on reset vector
1005 embeddedice_write_reg(&arm7_9
->eice_cache
1006 ->reg_list
[EICE_W0_ADDR_VALUE
], 0x0);
1007 embeddedice_write_reg(&arm7_9
->eice_cache
1008 ->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
1009 embeddedice_write_reg(&arm7_9
->eice_cache
1010 ->reg_list
[EICE_W0_DATA_MASK
],
1012 embeddedice_write_reg(&arm7_9
->eice_cache
1013 ->reg_list
[EICE_W0_CONTROL_VALUE
],
1014 EICE_W_CTRL_ENABLE
);
1015 embeddedice_write_reg(&arm7_9
->eice_cache
1016 ->reg_list
[EICE_W0_CONTROL_MASK
],
1017 ~EICE_W_CTRL_nOPC
& 0xff);
1022 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1024 /* If we use SRST ... we'd like to issue just SRST, but the
1025 * board or chip may be set up so we have to assert TRST as
1026 * well. On some chips that combination is equivalent to a
1027 * power-up reset, and generally clobbers EICE state.
1029 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1030 jtag_add_reset(1, 1);
1031 else if (!srst_asserted
)
1032 jtag_add_reset(0, 1);
1033 jtag_add_sleep(50000);
1036 target
->state
= TARGET_RESET
;
1037 register_cache_invalidate(arm7_9
->armv4_5_common
.core_cache
);
1039 /* REVISIT why isn't standard debug entry logic sufficient?? */
1040 if (target
->reset_halt
1041 && (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1044 /* debug entry was prepared above */
1045 target
->debug_reason
= DBG_REASON_DBGRQ
;
1052 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1053 * and the target is being reset into a halt, a warning will be triggered
1054 * because it is not possible to reset into a halted mode in this case. The
1055 * target is halted using the target's functions.
1057 * @param target Pointer to the target to have the reset deasserted
1058 * @return ERROR_OK or an error from polling or halting the target
1060 int arm7_9_deassert_reset(struct target
*target
)
1062 int retval
= ERROR_OK
;
1063 LOG_DEBUG("target->state: %s",
1064 target_state_name(target
));
1066 /* deassert reset lines */
1067 jtag_add_reset(0, 0);
1069 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1070 if (target
->reset_halt
&& (jtag_reset_config
& RESET_SRST_PULLS_TRST
) != 0)
1072 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1073 /* set up embedded ice registers again */
1074 if ((retval
= target_examine_one(target
)) != ERROR_OK
)
1077 if ((retval
= target_poll(target
)) != ERROR_OK
)
1082 if ((retval
= target_halt(target
)) != ERROR_OK
)
1092 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1093 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1094 * vector catch was used, it is restored. Otherwise, the control value is
1095 * restored and the watchpoint unit is restored if it was in use.
1097 * @param target Pointer to the ARM7/9 target to have halt cleared
1098 * @return Always ERROR_OK
1100 int arm7_9_clear_halt(struct target
*target
)
1102 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1103 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1105 /* we used DBGRQ only if we didn't come out of reset */
1106 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
1108 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1110 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1111 embeddedice_store_reg(dbg_ctrl
);
1115 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
1117 /* if we came out of reset, and vector catch is supported, we used
1118 * vector catch to enter debug state
1119 * restore the register in that case
1121 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
1125 /* restore registers if watchpoint unit 0 was in use
1127 if (arm7_9
->wp0_used
)
1129 if (arm7_9
->debug_entry_from_reset
)
1131 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
]);
1133 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1134 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1135 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1137 /* control value always has to be restored, as it was either disabled,
1138 * or enabled with possibly different bits
1140 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1148 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1149 * and then there is a wait until the processor shows the halt. This wait can
1150 * timeout and results in an error being returned. The software reset involves
1151 * clearing the halt, updating the debug control register, changing to ARM mode,
1152 * reset of the program counter, and reset of all of the registers.
1154 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1155 * @return Error status if any of the commands fail, otherwise ERROR_OK
1157 int arm7_9_soft_reset_halt(struct target
*target
)
1159 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1160 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1161 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1162 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1166 /* FIX!!! replace some of this code with tcl commands
1168 * halt # the halt command is synchronous
1169 * armv4_5 core_state arm
1173 if ((retval
= target_halt(target
)) != ERROR_OK
)
1176 long long then
= timeval_ms();
1178 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
1180 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) != 0)
1182 embeddedice_read_reg(dbg_stat
);
1183 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1185 if (debug_level
>= 3)
1195 LOG_ERROR("Failed to halt CPU after 1 sec");
1196 return ERROR_TARGET_TIMEOUT
;
1198 target
->state
= TARGET_HALTED
;
1200 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1201 * ensure that DBGRQ is cleared
1203 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1204 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1205 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1206 embeddedice_store_reg(dbg_ctrl
);
1208 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1213 /* if the target is in Thumb state, change to ARM state */
1214 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1216 uint32_t r0_thumb
, pc_thumb
;
1217 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1218 /* Entered debug from Thumb mode */
1219 armv4_5
->core_state
= ARM_STATE_THUMB
;
1220 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1223 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1225 /* all register content is now invalid */
1226 register_cache_invalidate(armv4_5
->core_cache
);
1228 /* SVC, ARM state, IRQ and FIQ disabled */
1231 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
1234 arm_set_cpsr(armv4_5
, cpsr
);
1235 armv4_5
->cpsr
->dirty
= 1;
1237 /* start fetching from 0x0 */
1238 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
1239 armv4_5
->pc
->dirty
= 1;
1240 armv4_5
->pc
->valid
= 1;
1242 /* reset registers */
1243 for (i
= 0; i
<= 14; i
++)
1245 struct reg
*r
= arm_reg_current(armv4_5
, i
);
1247 buf_set_u32(r
->value
, 0, 32, 0xffffffff);
1252 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
1261 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1262 * line or by programming a watchpoint to trigger on any address. It is
1263 * considered a bug to call this function while the target is in the
1264 * TARGET_RESET state.
1266 * @param target Pointer to the ARM7/9 target to be halted
1267 * @return Always ERROR_OK
1269 int arm7_9_halt(struct target
*target
)
1271 if (target
->state
== TARGET_RESET
)
1273 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1277 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1278 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1280 LOG_DEBUG("target->state: %s",
1281 target_state_name(target
));
1283 if (target
->state
== TARGET_HALTED
)
1285 LOG_DEBUG("target was already halted");
1289 if (target
->state
== TARGET_UNKNOWN
)
1291 LOG_WARNING("target was in unknown state when halt was requested");
1294 if (arm7_9
->use_dbgrq
)
1296 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1298 if (arm7_9
->set_special_dbgrq
) {
1299 arm7_9
->set_special_dbgrq(target
);
1301 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
1302 embeddedice_store_reg(dbg_ctrl
);
1307 /* program watchpoint unit to match on any address
1309 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1310 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1311 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1312 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1315 target
->debug_reason
= DBG_REASON_DBGRQ
;
1321 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1322 * ARM. The JTAG queue is then executed and the reason for debug entry is
1323 * examined. Once done, the target is verified to be halted and the processor
1324 * is forced into ARM mode. The core registers are saved for the current core
1325 * mode and the program counter (register 15) is updated as needed. The core
1326 * registers and CPSR and SPSR are saved for restoration later.
1328 * @param target Pointer to target that is entering debug mode
1329 * @return Error code if anything fails, otherwise ERROR_OK
1331 static int arm7_9_debug_entry(struct target
*target
)
1334 uint32_t context
[16];
1335 uint32_t* context_p
[16];
1336 uint32_t r0_thumb
, pc_thumb
;
1337 uint32_t cpsr
, cpsr_mask
= 0;
1339 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1340 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1341 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1342 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1344 #ifdef _DEBUG_ARM7_9_
1348 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1349 * ensure that DBGRQ is cleared
1351 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1352 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1353 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1354 embeddedice_store_reg(dbg_ctrl
);
1356 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1361 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1366 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1370 if (target
->state
!= TARGET_HALTED
)
1372 LOG_WARNING("target not halted");
1373 return ERROR_TARGET_NOT_HALTED
;
1376 /* if the target is in Thumb state, change to ARM state */
1377 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1379 LOG_DEBUG("target entered debug from Thumb state");
1380 /* Entered debug from Thumb mode */
1381 armv4_5
->core_state
= ARM_STATE_THUMB
;
1383 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1384 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1385 ", pc_thumb: 0x%8.8" PRIx32
, r0_thumb
, pc_thumb
);
1386 } else if (buf_get_u32(dbg_stat
->value
, 5, 1)) {
1387 /* \todo Get some vaguely correct handling of Jazelle, if
1388 * anyone ever uses it and full info becomes available.
1389 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1390 * B.7.3 for the reverse. That'd be the bare minimum...
1392 LOG_DEBUG("target entered debug from Jazelle state");
1393 armv4_5
->core_state
= ARM_STATE_JAZELLE
;
1394 cpsr_mask
= 1 << 24;
1395 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1397 LOG_DEBUG("target entered debug from ARM state");
1398 /* Entered debug from ARM mode */
1399 armv4_5
->core_state
= ARM_STATE_ARM
;
1402 for (i
= 0; i
< 16; i
++)
1403 context_p
[i
] = &context
[i
];
1404 /* save core registers (r0 - r15 of current core mode) */
1405 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1407 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1409 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1412 /* Sync our CPSR copy with J or T bits EICE reported, but
1413 * which we then erased by putting the core into ARM mode.
1415 arm_set_cpsr(armv4_5
, cpsr
| cpsr_mask
);
1417 if (!is_arm_mode(armv4_5
->core_mode
))
1419 target
->state
= TARGET_UNKNOWN
;
1420 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1421 return ERROR_TARGET_FAILURE
;
1424 LOG_DEBUG("target entered debug state in %s mode",
1425 arm_mode_name(armv4_5
->core_mode
));
1427 if (armv4_5
->core_state
== ARM_STATE_THUMB
)
1429 LOG_DEBUG("thumb state, applying fixups");
1430 context
[0] = r0_thumb
;
1431 context
[15] = pc_thumb
;
1432 } else if (armv4_5
->core_state
== ARM_STATE_ARM
)
1434 /* adjust value stored by STM */
1435 context
[15] -= 3 * 4;
1438 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
) || (!arm7_9
->use_dbgrq
))
1439 context
[15] -= 3 * ((armv4_5
->core_state
== ARM_STATE_ARM
) ? 4 : 2);
1441 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARM_STATE_ARM
) ? 4 : 2);
1443 for (i
= 0; i
<= 15; i
++)
1445 struct reg
*r
= arm_reg_current(armv4_5
, i
);
1447 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, context
[i
]);
1449 buf_set_u32(r
->value
, 0, 32, context
[i
]);
1450 /* r0 and r15 (pc) have to be restored later */
1451 r
->dirty
= (i
== 0) || (i
== 15);
1455 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
"", context
[15]);
1457 /* exceptions other than USR & SYS have a saved program status register */
1458 if (armv4_5
->spsr
) {
1460 arm7_9
->read_xpsr(target
, &spsr
, 1);
1461 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1465 buf_set_u32(armv4_5
->spsr
->value
, 0, 32, spsr
);
1466 armv4_5
->spsr
->dirty
= 0;
1467 armv4_5
->spsr
->valid
= 1;
1470 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1473 if (arm7_9
->post_debug_entry
)
1474 arm7_9
->post_debug_entry(target
);
1480 * Validate the full context for an ARM7/9 target in all processor modes. If
1481 * there are any invalid registers for the target, they will all be read. This
1484 * @param target Pointer to the ARM7/9 target to capture the full context from
1485 * @return Error if the target is not halted, has an invalid core mode, or if
1486 * the JTAG queue fails to execute
1488 int arm7_9_full_context(struct target
*target
)
1492 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1493 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1497 if (target
->state
!= TARGET_HALTED
)
1499 LOG_WARNING("target not halted");
1500 return ERROR_TARGET_NOT_HALTED
;
1503 if (!is_arm_mode(armv4_5
->core_mode
))
1506 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1507 * SYS shares registers with User, so we don't touch SYS
1509 for (i
= 0; i
< 6; i
++)
1512 uint32_t* reg_p
[16];
1516 /* check if there are invalid registers in the current mode
1518 for (j
= 0; j
<= 16; j
++)
1520 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1528 /* change processor mode (and mask T bit) */
1529 tmp_cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 8)
1531 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1533 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1535 for (j
= 0; j
< 15; j
++)
1537 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1539 reg_p
[j
] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1541 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1542 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1546 /* if only the PSR is invalid, mask is all zeroes */
1548 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1550 /* check if the PSR has to be read */
1551 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1553 arm7_9
->read_xpsr(target
, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1554 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1555 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1560 /* restore processor mode (mask T bit) */
1561 arm7_9
->write_xpsr_im8(target
,
1562 buf_get_u32(armv4_5
->cpsr
->value
, 0, 8) & ~0x20,
1565 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1573 * Restore the processor context on an ARM7/9 target. The full processor
1574 * context is analyzed to see if any of the registers are dirty on this end, but
1575 * have a valid new value. If this is the case, the processor is changed to the
1576 * appropriate mode and the new register values are written out to the
1577 * processor. If there happens to be a dirty register with an invalid value, an
1578 * error will be logged.
1580 * @param target Pointer to the ARM7/9 target to have its context restored
1581 * @return Error status if the target is not halted or the core mode in the
1582 * armv4_5 struct is invalid.
1584 int arm7_9_restore_context(struct target
*target
)
1586 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1587 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1589 struct arm_reg
*reg_arch_info
;
1590 enum arm_mode current_mode
= armv4_5
->core_mode
;
1597 if (target
->state
!= TARGET_HALTED
)
1599 LOG_WARNING("target not halted");
1600 return ERROR_TARGET_NOT_HALTED
;
1603 if (arm7_9
->pre_restore_context
)
1604 arm7_9
->pre_restore_context(target
);
1606 if (!is_arm_mode(armv4_5
->core_mode
))
1609 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1610 * SYS shares registers with User, so we don't touch SYS
1612 for (i
= 0; i
< 6; i
++)
1614 LOG_DEBUG("examining %s mode",
1615 arm_mode_name(armv4_5
->core_mode
));
1618 /* check if there are dirty registers in the current mode
1620 for (j
= 0; j
<= 16; j
++)
1622 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1623 reg_arch_info
= reg
->arch_info
;
1624 if (reg
->dirty
== 1)
1626 if (reg
->valid
== 1)
1629 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1630 if ((reg_arch_info
->mode
!= ARM_MODE_ANY
)
1631 && (reg_arch_info
->mode
!= current_mode
)
1632 && !((reg_arch_info
->mode
== ARM_MODE_USR
) && (armv4_5
->core_mode
== ARM_MODE_SYS
))
1633 && !((reg_arch_info
->mode
== ARM_MODE_SYS
) && (armv4_5
->core_mode
== ARM_MODE_USR
)))
1636 LOG_DEBUG("require mode change");
1641 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1648 uint32_t mask
= 0x0;
1656 /* change processor mode (mask T bit) */
1657 tmp_cpsr
= buf_get_u32(armv4_5
->cpsr
->value
,
1659 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1661 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1662 current_mode
= armv4_5_number_to_mode(i
);
1665 for (j
= 0; j
<= 14; j
++)
1667 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1668 reg_arch_info
= reg
->arch_info
;
1671 if (reg
->dirty
== 1)
1673 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1678 LOG_DEBUG("writing register %i mode %s "
1679 "with value 0x%8.8" PRIx32
, j
,
1680 arm_mode_name(armv4_5
->core_mode
),
1687 arm7_9
->write_core_regs(target
, mask
, regs
);
1690 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1691 reg_arch_info
= reg
->arch_info
;
1692 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARM_MODE_ANY
))
1694 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(reg
->value
, 0, 32));
1695 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1700 if (!armv4_5
->cpsr
->dirty
&& (armv4_5
->core_mode
!= current_mode
))
1702 /* restore processor mode (mask T bit) */
1705 tmp_cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 8) & 0xE0;
1706 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1708 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr
));
1709 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1711 else if (armv4_5
->cpsr
->dirty
)
1713 /* CPSR has been changed, full restore necessary (mask T bit) */
1714 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1715 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1716 arm7_9
->write_xpsr(target
,
1717 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32)
1719 armv4_5
->cpsr
->dirty
= 0;
1720 armv4_5
->cpsr
->valid
= 1;
1724 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
,
1725 buf_get_u32(armv4_5
->pc
->value
, 0, 32));
1726 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->pc
->value
, 0, 32));
1727 armv4_5
->pc
->dirty
= 0;
1729 if (arm7_9
->post_restore_context
)
1730 arm7_9
->post_restore_context(target
);
1736 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1737 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1740 * @param target Pointer to the ARM7/9 target to be restarted
1741 * @return Result of executing the JTAG queue
1743 int arm7_9_restart_core(struct target
*target
)
1745 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1746 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
1748 /* set RESTART instruction */
1749 jtag_set_end_state(TAP_IDLE
);
1750 if (arm7_9
->need_bypass_before_restart
) {
1751 arm7_9
->need_bypass_before_restart
= 0;
1752 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
1754 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1756 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE
));
1757 return jtag_execute_queue();
1761 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1762 * iterated through and are set on the target if they aren't already set.
1764 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1766 void arm7_9_enable_watchpoints(struct target
*target
)
1768 struct watchpoint
*watchpoint
= target
->watchpoints
;
1772 if (watchpoint
->set
== 0)
1773 arm7_9_set_watchpoint(target
, watchpoint
);
1774 watchpoint
= watchpoint
->next
;
1779 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1780 * iterated through and are set on the target.
1782 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1784 void arm7_9_enable_breakpoints(struct target
*target
)
1786 struct breakpoint
*breakpoint
= target
->breakpoints
;
1788 /* set any pending breakpoints */
1791 arm7_9_set_breakpoint(target
, breakpoint
);
1792 breakpoint
= breakpoint
->next
;
1796 int arm7_9_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1798 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1799 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1800 struct breakpoint
*breakpoint
= target
->breakpoints
;
1801 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1802 int err
, retval
= ERROR_OK
;
1806 if (target
->state
!= TARGET_HALTED
)
1808 LOG_WARNING("target not halted");
1809 return ERROR_TARGET_NOT_HALTED
;
1812 if (!debug_execution
)
1814 target_free_all_working_areas(target
);
1817 /* current = 1: continue on current pc, otherwise continue at <address> */
1819 buf_set_u32(armv4_5
->pc
->value
, 0, 32, address
);
1821 uint32_t current_pc
;
1822 current_pc
= buf_get_u32(armv4_5
->pc
->value
, 0, 32);
1824 /* the front-end may request us not to handle breakpoints */
1825 if (handle_breakpoints
)
1827 breakpoint
= breakpoint_find(target
,
1828 buf_get_u32(armv4_5
->pc
->value
, 0, 32));
1829 if (breakpoint
!= NULL
)
1831 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (id: %d)", breakpoint
->address
, breakpoint
->unique_id
);
1832 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1837 /* calculate PC of next instruction */
1839 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1841 uint32_t current_opcode
;
1842 target_read_u32(target
, current_pc
, ¤t_opcode
);
1843 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1847 LOG_DEBUG("enable single-step");
1848 arm7_9
->enable_single_step(target
, next_pc
);
1850 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1852 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1857 if (armv4_5
->core_state
== ARM_STATE_ARM
)
1858 arm7_9
->branch_resume(target
);
1859 else if (armv4_5
->core_state
== ARM_STATE_THUMB
)
1861 arm7_9
->branch_resume_thumb(target
);
1865 LOG_ERROR("unhandled core state");
1869 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1870 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1871 err
= arm7_9_execute_sys_speed(target
);
1873 LOG_DEBUG("disable single-step");
1874 arm7_9
->disable_single_step(target
);
1876 if (err
!= ERROR_OK
)
1878 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1882 target
->state
= TARGET_UNKNOWN
;
1886 arm7_9_debug_entry(target
);
1887 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32
,
1888 buf_get_u32(armv4_5
->pc
->value
, 0, 32));
1890 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1891 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1898 /* enable any pending breakpoints and watchpoints */
1899 arm7_9_enable_breakpoints(target
);
1900 arm7_9_enable_watchpoints(target
);
1902 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1907 if (armv4_5
->core_state
== ARM_STATE_ARM
)
1909 arm7_9
->branch_resume(target
);
1911 else if (armv4_5
->core_state
== ARM_STATE_THUMB
)
1913 arm7_9
->branch_resume_thumb(target
);
1917 LOG_ERROR("unhandled core state");
1921 /* deassert DBGACK and INTDIS */
1922 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1923 /* INTDIS only when we really resume, not during debug execution */
1924 if (!debug_execution
)
1925 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1926 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1928 if ((retval
= arm7_9_restart_core(target
)) != ERROR_OK
)
1933 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1935 if (!debug_execution
)
1937 /* registers are now invalid */
1938 register_cache_invalidate(armv4_5
->core_cache
);
1939 target
->state
= TARGET_RUNNING
;
1940 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
1947 target
->state
= TARGET_DEBUG_RUNNING
;
1948 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
)) != ERROR_OK
)
1954 LOG_DEBUG("target resumed");
1959 void arm7_9_enable_eice_step(struct target
*target
, uint32_t next_pc
)
1961 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1962 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1963 uint32_t current_pc
;
1964 current_pc
= buf_get_u32(armv4_5
->pc
->value
, 0, 32);
1966 if (next_pc
!= current_pc
)
1968 /* setup an inverse breakpoint on the current PC
1969 * - comparator 1 matches the current address
1970 * - rangeout from comparator 1 is connected to comparator 0 rangein
1971 * - comparator 0 matches any address, as long as rangein is low */
1972 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1974 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1975 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~(EICE_W_CTRL_RANGE
| EICE_W_CTRL_nOPC
) & 0xff);
1976 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], current_pc
);
1977 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1978 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1979 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1980 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1984 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1985 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1986 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
1987 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff);
1988 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], next_pc
);
1989 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1990 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1991 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1992 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1996 void arm7_9_disable_eice_step(struct target
*target
)
1998 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2000 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
2001 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
2002 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
2003 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
2004 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
2005 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
2006 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
2007 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
2008 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
2011 int arm7_9_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
2013 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2014 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2015 struct breakpoint
*breakpoint
= NULL
;
2018 if (target
->state
!= TARGET_HALTED
)
2020 LOG_WARNING("target not halted");
2021 return ERROR_TARGET_NOT_HALTED
;
2024 /* current = 1: continue on current pc, otherwise continue at <address> */
2026 buf_set_u32(armv4_5
->pc
->value
, 0, 32, address
);
2028 uint32_t current_pc
= buf_get_u32(armv4_5
->pc
->value
, 0, 32);
2030 /* the front-end may request us not to handle breakpoints */
2031 if (handle_breakpoints
)
2032 breakpoint
= breakpoint_find(target
, current_pc
);
2033 if (breakpoint
!= NULL
) {
2034 retval
= arm7_9_unset_breakpoint(target
, breakpoint
);
2035 if (retval
!= ERROR_OK
)
2039 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2041 /* calculate PC of next instruction */
2043 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
2045 uint32_t current_opcode
;
2046 target_read_u32(target
, current_pc
, ¤t_opcode
);
2047 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
2051 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
2056 arm7_9
->enable_single_step(target
, next_pc
);
2058 if (armv4_5
->core_state
== ARM_STATE_ARM
)
2060 arm7_9
->branch_resume(target
);
2062 else if (armv4_5
->core_state
== ARM_STATE_THUMB
)
2064 arm7_9
->branch_resume_thumb(target
);
2068 LOG_ERROR("unhandled core state");
2072 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
2077 err
= arm7_9_execute_sys_speed(target
);
2078 arm7_9
->disable_single_step(target
);
2080 /* registers are now invalid */
2081 register_cache_invalidate(armv4_5
->core_cache
);
2083 if (err
!= ERROR_OK
)
2085 target
->state
= TARGET_UNKNOWN
;
2087 arm7_9_debug_entry(target
);
2088 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
2092 LOG_DEBUG("target stepped");
2096 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2104 static int arm7_9_read_core_reg(struct target
*target
, struct reg
*r
,
2105 int num
, enum arm_mode mode
)
2107 uint32_t* reg_p
[16];
2110 struct arm_reg
*areg
= r
->arch_info
;
2111 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2112 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2114 if (!is_arm_mode(armv4_5
->core_mode
))
2116 if ((num
< 0) || (num
> 16))
2117 return ERROR_INVALID_ARGUMENTS
;
2119 if ((mode
!= ARM_MODE_ANY
)
2120 && (mode
!= armv4_5
->core_mode
)
2121 && (areg
->mode
!= ARM_MODE_ANY
))
2125 /* change processor mode (mask T bit) */
2126 tmp_cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 8) & 0xE0;
2129 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2132 if ((num
>= 0) && (num
<= 15))
2134 /* read a normal core register */
2135 reg_p
[num
] = &value
;
2137 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
2141 /* read a program status register
2142 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2144 arm7_9
->read_xpsr(target
, &value
, areg
->mode
!= ARM_MODE_ANY
);
2147 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2154 buf_set_u32(r
->value
, 0, 32, value
);
2156 if ((mode
!= ARM_MODE_ANY
)
2157 && (mode
!= armv4_5
->core_mode
)
2158 && (areg
->mode
!= ARM_MODE_ANY
)) {
2159 /* restore processor mode (mask T bit) */
2160 arm7_9
->write_xpsr_im8(target
,
2161 buf_get_u32(armv4_5
->cpsr
->value
, 0, 8)
2168 static int arm7_9_write_core_reg(struct target
*target
, struct reg
*r
,
2169 int num
, enum arm_mode mode
, uint32_t value
)
2172 struct arm_reg
*areg
= r
->arch_info
;
2173 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2174 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2176 if (!is_arm_mode(armv4_5
->core_mode
))
2178 if ((num
< 0) || (num
> 16))
2179 return ERROR_INVALID_ARGUMENTS
;
2181 if ((mode
!= ARM_MODE_ANY
)
2182 && (mode
!= armv4_5
->core_mode
)
2183 && (areg
->mode
!= ARM_MODE_ANY
)) {
2186 /* change processor mode (mask T bit) */
2187 tmp_cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 8) & 0xE0;
2190 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2193 if ((num
>= 0) && (num
<= 15))
2195 /* write a normal core register */
2198 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
2202 /* write a program status register
2203 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2205 int spsr
= (areg
->mode
!= ARM_MODE_ANY
);
2207 /* if we're writing the CPSR, mask the T bit */
2211 arm7_9
->write_xpsr(target
, value
, spsr
);
2217 if ((mode
!= ARM_MODE_ANY
)
2218 && (mode
!= armv4_5
->core_mode
)
2219 && (areg
->mode
!= ARM_MODE_ANY
)) {
2220 /* restore processor mode (mask T bit) */
2221 arm7_9
->write_xpsr_im8(target
,
2222 buf_get_u32(armv4_5
->cpsr
->value
, 0, 8)
2226 return jtag_execute_queue();
2229 int arm7_9_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2231 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2232 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2234 uint32_t num_accesses
= 0;
2235 int thisrun_accesses
;
2241 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
2243 if (target
->state
!= TARGET_HALTED
)
2245 LOG_WARNING("target not halted");
2246 return ERROR_TARGET_NOT_HALTED
;
2249 /* sanitize arguments */
2250 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2251 return ERROR_INVALID_ARGUMENTS
;
2253 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2254 return ERROR_TARGET_UNALIGNED_ACCESS
;
2256 /* load the base register with the address of the first word */
2258 arm7_9
->write_core_regs(target
, 0x1, reg
);
2265 while (num_accesses
< count
)
2268 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2269 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2271 if (last_reg
<= thisrun_accesses
)
2272 last_reg
= thisrun_accesses
;
2274 arm7_9
->load_word_regs(target
, reg_list
);
2276 /* fast memory reads are only safe when the target is running
2277 * from a sufficiently high clock (32 kHz is usually too slow)
2279 if (arm7_9
->fast_memory_access
)
2280 retval
= arm7_9_execute_fast_sys_speed(target
);
2282 retval
= arm7_9_execute_sys_speed(target
);
2283 if (retval
!= ERROR_OK
)
2286 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
2288 /* advance buffer, count number of accesses */
2289 buffer
+= thisrun_accesses
* 4;
2290 num_accesses
+= thisrun_accesses
;
2292 if ((j
++%1024) == 0)
2299 while (num_accesses
< count
)
2302 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2303 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2305 for (i
= 1; i
<= thisrun_accesses
; i
++)
2309 arm7_9
->load_hword_reg(target
, i
);
2310 /* fast memory reads are only safe when the target is running
2311 * from a sufficiently high clock (32 kHz is usually too slow)
2313 if (arm7_9
->fast_memory_access
)
2314 retval
= arm7_9_execute_fast_sys_speed(target
);
2316 retval
= arm7_9_execute_sys_speed(target
);
2317 if (retval
!= ERROR_OK
)
2324 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
2326 /* advance buffer, count number of accesses */
2327 buffer
+= thisrun_accesses
* 2;
2328 num_accesses
+= thisrun_accesses
;
2330 if ((j
++%1024) == 0)
2337 while (num_accesses
< count
)
2340 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2341 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2343 for (i
= 1; i
<= thisrun_accesses
; i
++)
2347 arm7_9
->load_byte_reg(target
, i
);
2348 /* fast memory reads are only safe when the target is running
2349 * from a sufficiently high clock (32 kHz is usually too slow)
2351 if (arm7_9
->fast_memory_access
)
2352 retval
= arm7_9_execute_fast_sys_speed(target
);
2354 retval
= arm7_9_execute_sys_speed(target
);
2355 if (retval
!= ERROR_OK
)
2361 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
2363 /* advance buffer, count number of accesses */
2364 buffer
+= thisrun_accesses
* 1;
2365 num_accesses
+= thisrun_accesses
;
2367 if ((j
++%1024) == 0)
2375 if (!is_arm_mode(armv4_5
->core_mode
))
2378 for (i
= 0; i
<= last_reg
; i
++) {
2379 struct reg
*r
= arm_reg_current(armv4_5
, i
);
2381 r
->dirty
= r
->valid
;
2384 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2385 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2387 LOG_ERROR("JTAG error while reading cpsr");
2388 return ERROR_TARGET_DATA_ABORT
;
2391 if (((cpsr
& 0x1f) == ARM_MODE_ABT
) && (armv4_5
->core_mode
!= ARM_MODE_ABT
))
2393 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2395 arm7_9
->write_xpsr_im8(target
,
2396 buf_get_u32(armv4_5
->cpsr
->value
, 0, 8)
2399 return ERROR_TARGET_DATA_ABORT
;
2405 int arm7_9_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2407 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2408 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2409 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
2412 uint32_t num_accesses
= 0;
2413 int thisrun_accesses
;
2419 #ifdef _DEBUG_ARM7_9_
2420 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2423 if (target
->state
!= TARGET_HALTED
)
2425 LOG_WARNING("target not halted");
2426 return ERROR_TARGET_NOT_HALTED
;
2429 /* sanitize arguments */
2430 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2431 return ERROR_INVALID_ARGUMENTS
;
2433 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2434 return ERROR_TARGET_UNALIGNED_ACCESS
;
2436 /* load the base register with the address of the first word */
2438 arm7_9
->write_core_regs(target
, 0x1, reg
);
2440 /* Clear DBGACK, to make sure memory fetches work as expected */
2441 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
2442 embeddedice_store_reg(dbg_ctrl
);
2447 while (num_accesses
< count
)
2450 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2451 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2453 for (i
= 1; i
<= thisrun_accesses
; i
++)
2457 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2461 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2463 arm7_9
->store_word_regs(target
, reg_list
);
2465 /* fast memory writes are only safe when the target is running
2466 * from a sufficiently high clock (32 kHz is usually too slow)
2468 if (arm7_9
->fast_memory_access
)
2469 retval
= arm7_9_execute_fast_sys_speed(target
);
2471 retval
= arm7_9_execute_sys_speed(target
);
2472 if (retval
!= ERROR_OK
)
2477 num_accesses
+= thisrun_accesses
;
2481 while (num_accesses
< count
)
2484 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2485 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2487 for (i
= 1; i
<= thisrun_accesses
; i
++)
2491 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2495 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2497 for (i
= 1; i
<= thisrun_accesses
; i
++)
2499 arm7_9
->store_hword_reg(target
, i
);
2501 /* fast memory writes are only safe when the target is running
2502 * from a sufficiently high clock (32 kHz is usually too slow)
2504 if (arm7_9
->fast_memory_access
)
2505 retval
= arm7_9_execute_fast_sys_speed(target
);
2507 retval
= arm7_9_execute_sys_speed(target
);
2508 if (retval
!= ERROR_OK
)
2514 num_accesses
+= thisrun_accesses
;
2518 while (num_accesses
< count
)
2521 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2522 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2524 for (i
= 1; i
<= thisrun_accesses
; i
++)
2528 reg
[i
] = *buffer
++ & 0xff;
2531 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2533 for (i
= 1; i
<= thisrun_accesses
; i
++)
2535 arm7_9
->store_byte_reg(target
, i
);
2536 /* fast memory writes are only safe when the target is running
2537 * from a sufficiently high clock (32 kHz is usually too slow)
2539 if (arm7_9
->fast_memory_access
)
2540 retval
= arm7_9_execute_fast_sys_speed(target
);
2542 retval
= arm7_9_execute_sys_speed(target
);
2543 if (retval
!= ERROR_OK
)
2550 num_accesses
+= thisrun_accesses
;
2556 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2557 embeddedice_store_reg(dbg_ctrl
);
2559 if (!is_arm_mode(armv4_5
->core_mode
))
2562 for (i
= 0; i
<= last_reg
; i
++) {
2563 struct reg
*r
= arm_reg_current(armv4_5
, i
);
2565 r
->dirty
= r
->valid
;
2568 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2569 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2571 LOG_ERROR("JTAG error while reading cpsr");
2572 return ERROR_TARGET_DATA_ABORT
;
2575 if (((cpsr
& 0x1f) == ARM_MODE_ABT
) && (armv4_5
->core_mode
!= ARM_MODE_ABT
))
2577 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2579 arm7_9
->write_xpsr_im8(target
,
2580 buf_get_u32(armv4_5
->cpsr
->value
, 0, 8)
2583 return ERROR_TARGET_DATA_ABORT
;
2589 static int dcc_count
;
2590 static uint8_t *dcc_buffer
;
2592 static int arm7_9_dcc_completion(struct target
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
2594 int retval
= ERROR_OK
;
2595 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2597 if ((retval
= target_wait_state(target
, TARGET_DEBUG_RUNNING
, 500)) != ERROR_OK
)
2600 int little
= target
->endianness
== TARGET_LITTLE_ENDIAN
;
2601 int count
= dcc_count
;
2602 uint8_t *buffer
= dcc_buffer
;
2605 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2606 * core function repeated. */
2607 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2610 struct embeddedice_reg
*ice_reg
= arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
].arch_info
;
2611 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
2612 struct jtag_tap
*tap
;
2613 tap
= ice_reg
->jtag_info
->tap
;
2615 embeddedice_write_dcc(tap
, reg_addr
, buffer
, little
, count
-2);
2616 buffer
+= (count
-2)*4;
2618 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2622 for (i
= 0; i
< count
; i
++)
2624 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2629 if ((retval
= target_halt(target
))!= ERROR_OK
)
2633 return target_wait_state(target
, TARGET_HALTED
, 500);
2636 static const uint32_t dcc_code
[] =
2638 /* r0 == input, points to memory buffer
2642 /* spin until DCC control (c0) reports data arrived */
2643 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2644 0xe3110001, /* tst r1, #1 */
2645 0x0afffffc, /* bne w */
2647 /* read word from DCC (c1), write to memory */
2648 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2649 0xe4801004, /* str r1, [r0], #4 */
2652 0xeafffff9 /* b w */
2655 int arm7_9_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
2658 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2661 if (!arm7_9
->dcc_downloads
)
2662 return target_write_memory(target
, address
, 4, count
, buffer
);
2664 /* regrab previously allocated working_area, or allocate a new one */
2665 if (!arm7_9
->dcc_working_area
)
2667 uint8_t dcc_code_buf
[6 * 4];
2669 /* make sure we have a working area */
2670 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2672 LOG_INFO("no working area available, falling back to memory writes");
2673 return target_write_memory(target
, address
, 4, count
, buffer
);
2676 /* copy target instructions to target endianness */
2677 for (i
= 0; i
< 6; i
++)
2679 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2682 /* write DCC code to working area */
2683 if ((retval
= target_write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
)) != ERROR_OK
)
2689 struct arm_algorithm armv4_5_info
;
2690 struct reg_param reg_params
[1];
2692 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
2693 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
2694 armv4_5_info
.core_state
= ARM_STATE_ARM
;
2696 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2698 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2701 dcc_buffer
= buffer
;
2702 retval
= armv4_5_run_algorithm_inner(target
, 0, NULL
, 1, reg_params
,
2703 arm7_9
->dcc_working_area
->address
,
2704 arm7_9
->dcc_working_area
->address
+ 6*4,
2705 20*1000, &armv4_5_info
, arm7_9_dcc_completion
);
2707 if (retval
== ERROR_OK
)
2709 uint32_t endaddress
= buf_get_u32(reg_params
[0].value
, 0, 32);
2710 if (endaddress
!= (address
+ count
*4))
2712 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32
" got 0x%0" PRIx32
"", (address
+ count
*4), endaddress
);
2713 retval
= ERROR_FAIL
;
2717 destroy_reg_param(®_params
[0]);
2723 * Perform per-target setup that requires JTAG access.
2725 int arm7_9_examine(struct target
*target
)
2727 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2730 if (!target_was_examined(target
)) {
2731 struct reg_cache
*t
, **cache_p
;
2733 t
= embeddedice_build_reg_cache(target
, arm7_9
);
2737 cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2739 arm7_9
->eice_cache
= (*cache_p
);
2741 if (arm7_9
->armv4_5_common
.etm
)
2742 (*cache_p
)->next
= etm_build_reg_cache(target
,
2744 arm7_9
->armv4_5_common
.etm
);
2746 target_set_examined(target
);
2749 retval
= embeddedice_setup(target
);
2750 if (retval
== ERROR_OK
)
2751 retval
= arm7_9_setup(target
);
2752 if (retval
== ERROR_OK
&& arm7_9
->armv4_5_common
.etm
)
2753 retval
= etm_setup(target
);
2758 int arm7_9_check_reset(struct target
*target
)
2760 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2762 if (get_target_reset_nag() && !arm7_9
->dcc_downloads
)
2764 LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
2767 if (get_target_reset_nag() && (target
->working_area_size
== 0))
2769 LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
2772 if (get_target_reset_nag() && !arm7_9
->fast_memory_access
)
2774 LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
2780 COMMAND_HANDLER(handle_arm7_9_dbgrq_command
)
2782 struct target
*target
= get_current_target(CMD_CTX
);
2783 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2785 if (!is_arm7_9(arm7_9
))
2787 command_print(CMD_CTX
, "current target isn't an ARM7/ARM9 target");
2788 return ERROR_TARGET_INVALID
;
2792 COMMAND_PARSE_ENABLE(CMD_ARGV
[0],arm7_9
->use_dbgrq
);
2794 command_print(CMD_CTX
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2799 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command
)
2801 struct target
*target
= get_current_target(CMD_CTX
);
2802 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2804 if (!is_arm7_9(arm7_9
))
2806 command_print(CMD_CTX
, "current target isn't an ARM7/ARM9 target");
2807 return ERROR_TARGET_INVALID
;
2811 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], arm7_9
->fast_memory_access
);
2813 command_print(CMD_CTX
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2818 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command
)
2820 struct target
*target
= get_current_target(CMD_CTX
);
2821 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2823 if (!is_arm7_9(arm7_9
))
2825 command_print(CMD_CTX
, "current target isn't an ARM7/ARM9 target");
2826 return ERROR_TARGET_INVALID
;
2830 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], arm7_9
->dcc_downloads
);
2832 command_print(CMD_CTX
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2837 int arm7_9_setup_semihosting(struct target
*target
, int enable
)
2839 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2841 if (!is_arm7_9(arm7_9
))
2843 LOG_USER("current target isn't an ARM7/ARM9 target");
2844 return ERROR_TARGET_INVALID
;
2847 if (arm7_9
->has_vector_catch
) {
2848 struct reg
*vector_catch
= &arm7_9
->eice_cache
2849 ->reg_list
[EICE_VEC_CATCH
];
2851 if (!vector_catch
->valid
)
2852 embeddedice_read_reg(vector_catch
);
2853 buf_set_u32(vector_catch
->value
, 2, 1, enable
);
2854 embeddedice_store_reg(vector_catch
);
2856 /* TODO: allow optional high vectors and/or BKPT_HARD */
2858 breakpoint_add(target
, 8, 4, BKPT_SOFT
);
2860 breakpoint_remove(target
, 8);
2866 int arm7_9_init_arch_info(struct target
*target
, struct arm7_9_common
*arm7_9
)
2868 int retval
= ERROR_OK
;
2869 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2871 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2873 if ((retval
= arm_jtag_setup_connection(&arm7_9
->jtag_info
)) != ERROR_OK
)
2876 /* caller must have allocated via calloc(), so everything's zeroed */
2878 arm7_9
->wp_available_max
= 2;
2880 arm7_9
->fast_memory_access
= false;
2881 arm7_9
->dcc_downloads
= false;
2883 armv4_5
->arch_info
= arm7_9
;
2884 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2885 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2886 armv4_5
->full_context
= arm7_9_full_context
;
2887 armv4_5
->setup_semihosting
= arm7_9_setup_semihosting
;
2889 retval
= arm_init_arch_info(target
, armv4_5
);
2890 if (retval
!= ERROR_OK
)
2893 return target_register_timer_callback(arm7_9_handle_target_request
,
2897 static const struct command_registration arm7_9_any_command_handlers
[] = {
2900 .handler
= handle_arm7_9_dbgrq_command
,
2901 .mode
= COMMAND_ANY
,
2902 .usage
= "['enable'|'disable']",
2903 .help
= "use EmbeddedICE dbgrq instead of breakpoint "
2904 "for target halt requests",
2907 "fast_memory_access",
2908 .handler
= handle_arm7_9_fast_memory_access_command
,
2909 .mode
= COMMAND_ANY
,
2910 .usage
= "['enable'|'disable']",
2911 .help
= "use fast memory accesses instead of slower "
2912 "but potentially safer accesses",
2916 .handler
= handle_arm7_9_dcc_downloads_command
,
2917 .mode
= COMMAND_ANY
,
2918 .usage
= "['enable'|'disable']",
2919 .help
= "use DCC downloads for larger memory writes",
2921 COMMAND_REGISTRATION_DONE
2923 const struct command_registration arm7_9_command_handlers
[] = {
2925 .chain
= arm_command_handlers
,
2928 .chain
= etm_command_handlers
,
2932 .mode
= COMMAND_ANY
,
2933 .help
= "arm7/9 specific commands",
2934 .chain
= arm7_9_any_command_handlers
,
2936 COMMAND_REGISTRATION_DONE