1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FBP remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
56 * Returns the type of a break point required by address location
58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
63 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
64 static void cortex_m3_enable_watchpoints(struct target
*target
);
65 static int cortex_m3_store_core_reg_u32(struct target
*target
,
66 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
68 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
69 uint32_t *value
, int regnum
)
74 /* because the DCB_DCRDR is used for the emulated dcc channel
75 * we have to save/restore the DCB_DCRDR when used */
77 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
78 if (retval
!= ERROR_OK
)
81 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
82 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
83 if (retval
!= ERROR_OK
)
85 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
86 if (retval
!= ERROR_OK
)
89 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
90 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
91 if (retval
!= ERROR_OK
)
93 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
94 if (retval
!= ERROR_OK
)
97 retval
= dap_run(swjdp
);
98 if (retval
!= ERROR_OK
)
101 /* restore DCB_DCRDR - this needs to be in a seperate
102 * transaction otherwise the emulated DCC channel breaks */
103 if (retval
== ERROR_OK
)
104 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
109 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
110 uint32_t value
, int regnum
)
115 /* because the DCB_DCRDR is used for the emulated dcc channel
116 * we have to save/restore the DCB_DCRDR when used */
118 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
119 if (retval
!= ERROR_OK
)
122 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
123 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
124 if (retval
!= ERROR_OK
)
126 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
127 if (retval
!= ERROR_OK
)
130 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
131 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
132 if (retval
!= ERROR_OK
)
134 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
135 if (retval
!= ERROR_OK
)
138 retval
= dap_run(swjdp
);
139 if (retval
!= ERROR_OK
)
142 /* restore DCB_DCRDR - this needs to be in a seperate
143 * transaction otherwise the emulated DCC channel breaks */
144 if (retval
== ERROR_OK
)
145 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
150 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
151 uint32_t mask_on
, uint32_t mask_off
)
153 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
154 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
156 /* mask off status bits */
157 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
158 /* create new register mask */
159 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
161 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
164 static int cortex_m3_clear_halt(struct target
*target
)
166 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
167 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
170 /* clear step if any */
171 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
173 /* Read Debug Fault Status Register */
174 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
175 if (retval
!= ERROR_OK
)
178 /* Clear Debug Fault Status */
179 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
180 if (retval
!= ERROR_OK
)
182 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
187 static int cortex_m3_single_step_core(struct target
*target
)
189 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
190 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
194 /* backup dhcsr reg */
195 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
197 /* Mask interrupts before clearing halt, if done already. This avoids
198 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
199 * HALT can put the core into an unknown state.
201 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
203 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
204 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
205 if (retval
!= ERROR_OK
)
208 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
209 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
210 if (retval
!= ERROR_OK
)
214 /* restore dhcsr reg */
215 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
216 cortex_m3_clear_halt(target
);
221 static int cortex_m3_endreset_event(struct target
*target
)
226 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
227 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
228 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
229 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
230 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
232 /* REVISIT The four debug monitor bits are currently ignored... */
233 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
234 if (retval
!= ERROR_OK
)
236 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
238 /* this register is used for emulated dcc channel */
239 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
240 if (retval
!= ERROR_OK
)
243 /* Enable debug requests */
244 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
245 if (retval
!= ERROR_OK
)
247 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
249 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
250 if (retval
!= ERROR_OK
)
254 /* clear any interrupt masking */
255 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
257 /* Enable features controlled by ITM and DWT blocks, and catch only
258 * the vectors we were told to pay attention to.
260 * Target firmware is responsible for all fault handling policy
261 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
262 * or manual updates to the NVIC SHCSR and CCR registers.
264 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
265 if (retval
!= ERROR_OK
)
268 /* Paranoia: evidently some (early?) chips don't preserve all the
269 * debug state (including FBP, DWT, etc) across reset...
273 retval
= target_write_u32(target
, FP_CTRL
, 3);
274 if (retval
!= ERROR_OK
)
277 cortex_m3
->fpb_enabled
= 1;
279 /* Restore FPB registers */
280 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
282 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
283 if (retval
!= ERROR_OK
)
287 /* Restore DWT registers */
288 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
290 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
292 if (retval
!= ERROR_OK
)
294 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
296 if (retval
!= ERROR_OK
)
298 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
299 dwt_list
[i
].function
);
300 if (retval
!= ERROR_OK
)
303 retval
= dap_run(swjdp
);
304 if (retval
!= ERROR_OK
)
307 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
309 /* make sure we have latest dhcsr flags */
310 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
315 static int cortex_m3_examine_debug_reason(struct target
*target
)
317 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
319 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
320 /* only check the debug reason if we don't know it already */
322 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
323 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
325 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
327 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
328 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
329 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
331 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
332 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
333 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
334 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
335 else /* EXTERNAL, HALTED */
336 target
->debug_reason
= DBG_REASON_UNDEFINED
;
342 static int cortex_m3_examine_exception_reason(struct target
*target
)
344 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
345 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
346 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
349 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
350 if (retval
!= ERROR_OK
)
352 switch (armv7m
->exception_number
)
356 case 3: /* Hard Fault */
357 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
358 if (retval
!= ERROR_OK
)
360 if (except_sr
& 0x40000000)
362 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
363 if (retval
!= ERROR_OK
)
367 case 4: /* Memory Management */
368 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
369 if (retval
!= ERROR_OK
)
371 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
372 if (retval
!= ERROR_OK
)
375 case 5: /* Bus Fault */
376 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
377 if (retval
!= ERROR_OK
)
379 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
380 if (retval
!= ERROR_OK
)
383 case 6: /* Usage Fault */
384 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
385 if (retval
!= ERROR_OK
)
388 case 11: /* SVCall */
390 case 12: /* Debug Monitor */
391 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
392 if (retval
!= ERROR_OK
)
395 case 14: /* PendSV */
397 case 15: /* SysTick */
403 retval
= dap_run(swjdp
);
404 if (retval
== ERROR_OK
)
405 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
406 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
407 armv7m_exception_string(armv7m
->exception_number
),
408 shcsr
, except_sr
, cfsr
, except_ar
);
412 /* PSP is used in some thread modes */
413 static const int armv7m_psp_reg_map
[17] = {
414 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
415 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
416 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
417 ARMV7M_R12
, ARMV7M_PSP
, ARMV7M_R14
, ARMV7M_PC
,
421 /* MSP is used in handler and some thread modes */
422 static const int armv7m_msp_reg_map
[17] = {
423 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
424 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
425 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
426 ARMV7M_R12
, ARMV7M_MSP
, ARMV7M_R14
, ARMV7M_PC
,
430 static int cortex_m3_debug_entry(struct target
*target
)
435 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
436 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
437 struct arm
*arm
= &armv7m
->arm
;
438 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
443 cortex_m3_clear_halt(target
);
444 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
445 if (retval
!= ERROR_OK
)
448 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
451 /* Examine target state and mode */
452 /* First load register acessible through core debug port*/
453 int num_regs
= armv7m
->core_cache
->num_regs
;
455 for (i
= 0; i
< num_regs
; i
++)
457 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
458 armv7m
->read_core_reg(target
, i
);
461 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
462 xPSR
= buf_get_u32(r
->value
, 0, 32);
464 #ifdef ARMV7_GDB_HACKS
465 /* FIXME this breaks on scan chains with more than one Cortex-M3.
466 * Instead, each CM3 should have its own dummy value...
468 /* copy real xpsr reg for gdb, setting thumb bit */
469 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
470 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
471 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
472 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
475 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
479 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
482 /* Are we in an exception handler */
485 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
486 armv7m
->exception_number
= (xPSR
& 0x1FF);
488 arm
->core_mode
= ARM_MODE_HANDLER
;
489 arm
->map
= armv7m_msp_reg_map
;
493 unsigned control
= buf_get_u32(armv7m
->core_cache
494 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
496 /* is this thread privileged? */
497 armv7m
->core_mode
= control
& 1;
498 arm
->core_mode
= armv7m
->core_mode
499 ? ARM_MODE_USER_THREAD
502 /* which stack is it using? */
504 arm
->map
= armv7m_psp_reg_map
;
506 arm
->map
= armv7m_msp_reg_map
;
508 armv7m
->exception_number
= 0;
511 if (armv7m
->exception_number
)
513 cortex_m3_examine_exception_reason(target
);
516 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
517 armv7m_mode_strings
[armv7m
->core_mode
],
518 *(uint32_t*)(arm
->pc
->value
),
519 target_state_name(target
));
521 if (armv7m
->post_debug_entry
)
523 retval
= armv7m
->post_debug_entry(target
);
524 if (retval
!= ERROR_OK
)
531 static int cortex_m3_poll(struct target
*target
)
533 int detected_failure
= ERROR_OK
;
534 int retval
= ERROR_OK
;
535 enum target_state prev_target_state
= target
->state
;
536 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
537 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
539 /* Read from Debug Halting Control and Status Register */
540 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
541 if (retval
!= ERROR_OK
)
543 target
->state
= TARGET_UNKNOWN
;
547 /* Recover from lockup. See ARMv7-M architecture spec,
548 * section B1.5.15 "Unrecoverable exception cases".
550 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
551 LOG_ERROR("%s -- clearing lockup after double fault",
552 target_name(target
));
553 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
554 target
->debug_reason
= DBG_REASON_DBGRQ
;
556 /* We have to execute the rest (the "finally" equivalent, but
557 * still throw this exception again).
559 detected_failure
= ERROR_FAIL
;
561 /* refresh status bits */
562 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
563 if (retval
!= ERROR_OK
)
567 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
569 /* check if still in reset */
570 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
571 if (retval
!= ERROR_OK
)
574 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
576 target
->state
= TARGET_RESET
;
581 if (target
->state
== TARGET_RESET
)
583 /* Cannot switch context while running so endreset is
584 * called with target->state == TARGET_RESET
586 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
587 cortex_m3
->dcb_dhcsr
);
588 cortex_m3_endreset_event(target
);
589 target
->state
= TARGET_RUNNING
;
590 prev_target_state
= TARGET_RUNNING
;
593 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
595 target
->state
= TARGET_HALTED
;
597 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
599 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
602 if (arm_semihosting(target
, &retval
) != 0)
605 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
607 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
610 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
613 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
617 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
618 * How best to model low power modes?
621 if (target
->state
== TARGET_UNKNOWN
)
623 /* check if processor is retiring instructions */
624 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
626 target
->state
= TARGET_RUNNING
;
631 /* Did we detect a failure condition that we cleared? */
632 if (detected_failure
!= ERROR_OK
)
633 retval
= detected_failure
;
637 static int cortex_m3_halt(struct target
*target
)
639 LOG_DEBUG("target->state: %s",
640 target_state_name(target
));
642 if (target
->state
== TARGET_HALTED
)
644 LOG_DEBUG("target was already halted");
648 if (target
->state
== TARGET_UNKNOWN
)
650 LOG_WARNING("target was in unknown state when halt was requested");
653 if (target
->state
== TARGET_RESET
)
655 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
657 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
658 return ERROR_TARGET_FAILURE
;
662 /* we came here in a reset_halt or reset_init sequence
663 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
665 target
->debug_reason
= DBG_REASON_DBGRQ
;
671 /* Write to Debug Halting Control and Status Register */
672 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
674 target
->debug_reason
= DBG_REASON_DBGRQ
;
679 static int cortex_m3_soft_reset_halt(struct target
*target
)
681 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
682 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
683 uint32_t dcb_dhcsr
= 0;
684 int retval
, timeout
= 0;
686 /* Enter debug state on reset; restore DEMCR in endreset_event() */
687 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
688 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
689 if (retval
!= ERROR_OK
)
692 /* Request a core-only reset */
693 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
694 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
695 if (retval
!= ERROR_OK
)
697 target
->state
= TARGET_RESET
;
699 /* registers are now invalid */
700 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
702 while (timeout
< 100)
704 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
705 if (retval
== ERROR_OK
)
707 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
708 &cortex_m3
->nvic_dfsr
);
709 if (retval
!= ERROR_OK
)
711 if ((dcb_dhcsr
& S_HALT
)
712 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
714 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
716 (unsigned) dcb_dhcsr
,
717 (unsigned) cortex_m3
->nvic_dfsr
);
718 cortex_m3_poll(target
);
719 /* FIXME restore user's vector catch config */
723 LOG_DEBUG("waiting for system reset-halt, "
724 "DHCSR 0x%08x, %d ms",
725 (unsigned) dcb_dhcsr
, timeout
);
734 static void cortex_m3_enable_breakpoints(struct target
*target
)
736 struct breakpoint
*breakpoint
= target
->breakpoints
;
738 /* set any pending breakpoints */
741 if (!breakpoint
->set
)
742 cortex_m3_set_breakpoint(target
, breakpoint
);
743 breakpoint
= breakpoint
->next
;
747 static int cortex_m3_resume(struct target
*target
, int current
,
748 uint32_t address
, int handle_breakpoints
, int debug_execution
)
750 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
751 struct breakpoint
*breakpoint
= NULL
;
755 if (target
->state
!= TARGET_HALTED
)
757 LOG_WARNING("target not halted");
758 return ERROR_TARGET_NOT_HALTED
;
761 if (!debug_execution
)
763 target_free_all_working_areas(target
);
764 cortex_m3_enable_breakpoints(target
);
765 cortex_m3_enable_watchpoints(target
);
770 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
772 /* Disable interrupts */
773 /* We disable interrupts in the PRIMASK register instead of
774 * masking with C_MASKINTS. This is probably the same issue
775 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
776 * in parallel with disabled interrupts can cause local faults
779 * REVISIT this clearly breaks non-debug execution, since the
780 * PRIMASK register state isn't saved/restored... workaround
781 * by never resuming app code after debug execution.
783 buf_set_u32(r
->value
, 0, 1, 1);
787 /* Make sure we are in Thumb mode */
788 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
789 buf_set_u32(r
->value
, 24, 1, 1);
794 /* current = 1: continue on current pc, otherwise continue at <address> */
798 buf_set_u32(r
->value
, 0, 32, address
);
803 /* if we halted last time due to a bkpt instruction
804 * then we have to manually step over it, otherwise
805 * the core will break again */
807 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
810 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
813 resume_pc
= buf_get_u32(r
->value
, 0, 32);
815 armv7m_restore_context(target
);
817 /* the front-end may request us not to handle breakpoints */
818 if (handle_breakpoints
)
820 /* Single step past breakpoint at current address */
821 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
823 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
825 breakpoint
->unique_id
);
826 cortex_m3_unset_breakpoint(target
, breakpoint
);
827 cortex_m3_single_step_core(target
);
828 cortex_m3_set_breakpoint(target
, breakpoint
);
833 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
835 target
->debug_reason
= DBG_REASON_NOTHALTED
;
837 /* registers are now invalid */
838 register_cache_invalidate(armv7m
->core_cache
);
840 if (!debug_execution
)
842 target
->state
= TARGET_RUNNING
;
843 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
844 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
848 target
->state
= TARGET_DEBUG_RUNNING
;
849 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
850 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
856 /* int irqstepcount = 0; */
857 static int cortex_m3_step(struct target
*target
, int current
,
858 uint32_t address
, int handle_breakpoints
)
860 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
861 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
862 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
863 struct breakpoint
*breakpoint
= NULL
;
864 struct reg
*pc
= armv7m
->arm
.pc
;
865 bool bkpt_inst_found
= false;
867 bool isr_timed_out
= false;
869 if (target
->state
!= TARGET_HALTED
)
871 LOG_WARNING("target not halted");
872 return ERROR_TARGET_NOT_HALTED
;
875 /* current = 1: continue on current pc, otherwise continue at <address> */
877 buf_set_u32(pc
->value
, 0, 32, address
);
879 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
881 /* the front-end may request us not to handle breakpoints */
882 if (handle_breakpoints
) {
883 breakpoint
= breakpoint_find(target
, pc_value
);
885 cortex_m3_unset_breakpoint(target
, breakpoint
);
888 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
890 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
892 armv7m_restore_context(target
);
894 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
896 /* if no bkpt instruction is found at pc then we can perform
897 * a normal step, otherwise we have to manually step over the bkpt
898 * instruction - as such simulate a step */
899 if (bkpt_inst_found
== false)
901 /* Automatic ISR masking mode off: Just step over the next instruction */
902 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
904 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
908 /* Process interrupts during stepping in a way they don't interfere
913 * Set a temporary break point at the current pc and let the core run
914 * with interrupts enabled. Pending interrupts get served and we run
915 * into the breakpoint again afterwards. Then we step over the next
916 * instruction with interrupts disabled.
918 * If the pending interrupts don't complete within time, we leave the
919 * core running. This may happen if the interrupts trigger faster
920 * than the core can process them or the handler doesn't return.
922 * If no more breakpoints are available we simply do a step with
923 * interrupts enabled.
927 /* Set a temporary break point */
928 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
929 bool tmp_bp_set
= (retval
== ERROR_OK
);
931 /* No more breakpoints left, just do a step */
934 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
939 LOG_DEBUG("Starting core to serve pending interrupts");
940 int64_t t_start
= timeval_ms();
941 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
943 /* Wait for pending handlers to complete or timeout */
945 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
946 if (retval
!= ERROR_OK
)
948 target
->state
= TARGET_UNKNOWN
;
951 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
952 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
954 /* Remove the temporary breakpoint */
955 breakpoint_remove(target
, pc_value
);
959 LOG_DEBUG("Interrupt handlers didn't complete within time, "
960 "leaving target running");
964 /* Step over next instruction with interrupts disabled */
965 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
966 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
967 /* Re-enable interrupts */
968 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
974 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
975 if (retval
!= ERROR_OK
)
978 /* registers are now invalid */
979 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
982 cortex_m3_set_breakpoint(target
, breakpoint
);
985 /* Leave the core running. The user has to stop execution manually. */
986 target
->debug_reason
= DBG_REASON_NOTHALTED
;
987 target
->state
= TARGET_RUNNING
;
991 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
992 " nvic_icsr = 0x%" PRIx32
,
993 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
995 retval
= cortex_m3_debug_entry(target
);
996 if (retval
!= ERROR_OK
)
998 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1000 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1001 " nvic_icsr = 0x%" PRIx32
,
1002 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
1007 static int cortex_m3_assert_reset(struct target
*target
)
1009 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1010 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1011 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
1013 LOG_DEBUG("target->state: %s",
1014 target_state_name(target
));
1016 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1018 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1019 /* allow scripts to override the reset event */
1021 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1022 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1023 target
->state
= TARGET_RESET
;
1028 /* Enable debug requests */
1030 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
1031 if (retval
!= ERROR_OK
)
1033 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
1035 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1036 if (retval
!= ERROR_OK
)
1040 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1041 if (retval
!= ERROR_OK
)
1044 if (!target
->reset_halt
)
1046 /* Set/Clear C_MASKINTS in a separate operation */
1047 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
1049 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1050 DBGKEY
| C_DEBUGEN
| C_HALT
);
1051 if (retval
!= ERROR_OK
)
1055 /* clear any debug flags before resuming */
1056 cortex_m3_clear_halt(target
);
1058 /* clear C_HALT in dhcsr reg */
1059 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
1063 /* Halt in debug on reset; endreset_event() restores DEMCR.
1065 * REVISIT catching BUSERR presumably helps to defend against
1066 * bad vector table entries. Should this include MMERR or
1069 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1070 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1071 if (retval
!= ERROR_OK
)
1075 if (jtag_reset_config
& RESET_HAS_SRST
)
1077 /* default to asserting srst */
1078 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1080 jtag_add_reset(1, 1);
1084 jtag_add_reset(0, 1);
1089 /* Use a standard Cortex-M3 software reset mechanism.
1090 * We default to using VECRESET as it is supported on all current cores.
1091 * This has the disadvantage of not resetting the peripherals, so a
1092 * reset-init event handler is needed to perform any peripheral resets.
1094 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1095 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1096 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1097 if (retval
!= ERROR_OK
)
1100 LOG_DEBUG("Using Cortex-M3 %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1101 ? "SYSRESETREQ" : "VECTRESET");
1103 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1104 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1105 "handler to reset any peripherals");
1109 /* I do not know why this is necessary, but it
1110 * fixes strange effects (step/resume cause NMI
1111 * after reset) on LM3S6918 -- Michael Schwingen
1114 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1115 if (retval
!= ERROR_OK
)
1120 target
->state
= TARGET_RESET
;
1121 jtag_add_sleep(50000);
1123 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1125 if (target
->reset_halt
)
1127 if ((retval
= target_halt(target
)) != ERROR_OK
)
1134 static int cortex_m3_deassert_reset(struct target
*target
)
1136 LOG_DEBUG("target->state: %s",
1137 target_state_name(target
));
1139 /* deassert reset lines */
1140 jtag_add_reset(0, 0);
1146 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1151 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1152 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1154 if (breakpoint
->set
)
1156 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1160 if (cortex_m3
->auto_bp_type
)
1162 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1165 if (breakpoint
->type
== BKPT_HARD
)
1167 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1169 if (fp_num
>= cortex_m3
->fp_num_code
)
1171 LOG_ERROR("Can not find free FPB Comparator!");
1174 breakpoint
->set
= fp_num
+ 1;
1175 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1176 comparator_list
[fp_num
].used
= 1;
1177 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1178 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1179 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
1180 if (!cortex_m3
->fpb_enabled
)
1182 LOG_DEBUG("FPB wasn't enabled, do it now");
1183 target_write_u32(target
, FP_CTRL
, 3);
1186 else if (breakpoint
->type
== BKPT_SOFT
)
1190 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1191 * semihosting; don't use that. Otherwise the BKPT
1192 * parameter is arbitrary.
1194 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1195 retval
= target_read_memory(target
,
1196 breakpoint
->address
& 0xFFFFFFFE,
1197 breakpoint
->length
, 1,
1198 breakpoint
->orig_instr
);
1199 if (retval
!= ERROR_OK
)
1201 retval
= target_write_memory(target
,
1202 breakpoint
->address
& 0xFFFFFFFE,
1203 breakpoint
->length
, 1,
1205 if (retval
!= ERROR_OK
)
1207 breakpoint
->set
= true;
1210 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1211 breakpoint
->unique_id
,
1212 (int)(breakpoint
->type
),
1213 breakpoint
->address
,
1221 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1224 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1225 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
1227 if (!breakpoint
->set
)
1229 LOG_WARNING("breakpoint not set");
1233 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1234 breakpoint
->unique_id
,
1235 (int)(breakpoint
->type
),
1236 breakpoint
->address
,
1240 if (breakpoint
->type
== BKPT_HARD
)
1242 int fp_num
= breakpoint
->set
- 1;
1243 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
1245 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1248 comparator_list
[fp_num
].used
= 0;
1249 comparator_list
[fp_num
].fpcr_value
= 0;
1250 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1254 /* restore original instruction (kept in target endianness) */
1255 if (breakpoint
->length
== 4)
1257 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1264 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1270 breakpoint
->set
= false;
1276 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1278 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1280 if (cortex_m3
->auto_bp_type
)
1282 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1283 #ifdef ARMV7_GDB_HACKS
1284 if (breakpoint
->length
!= 2) {
1285 /* XXX Hack: Replace all breakpoints with length != 2 with
1286 * a hardware breakpoint. */
1287 breakpoint
->type
= BKPT_HARD
;
1288 breakpoint
->length
= 2;
1293 if(breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1294 if (breakpoint
->type
== BKPT_HARD
)
1296 LOG_INFO("flash patch comparator requested outside code memory region");
1297 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1300 if (breakpoint
->type
== BKPT_SOFT
)
1302 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1303 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1307 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1309 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1310 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1313 if ((breakpoint
->length
!= 2))
1315 LOG_INFO("only breakpoints of two bytes length supported");
1316 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1319 if (breakpoint
->type
== BKPT_HARD
)
1320 cortex_m3
->fp_code_available
--;
1322 return cortex_m3_set_breakpoint(target
, breakpoint
);
1326 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1328 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1330 /* REVISIT why check? FBP can be updated with core running ... */
1331 if (target
->state
!= TARGET_HALTED
)
1333 LOG_WARNING("target not halted");
1334 return ERROR_TARGET_NOT_HALTED
;
1337 if (cortex_m3
->auto_bp_type
)
1339 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1342 if (breakpoint
->set
)
1344 cortex_m3_unset_breakpoint(target
, breakpoint
);
1347 if (breakpoint
->type
== BKPT_HARD
)
1348 cortex_m3
->fp_code_available
++;
1354 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1357 uint32_t mask
, temp
;
1358 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1360 /* watchpoint params were validated earlier */
1362 temp
= watchpoint
->length
;
1369 /* REVISIT Don't fully trust these "not used" records ... users
1370 * may set up breakpoints by hand, e.g. dual-address data value
1371 * watchpoint using comparator #1; comparator #0 matching cycle
1372 * count; send data trace info through ITM and TPIU; etc
1374 struct cortex_m3_dwt_comparator
*comparator
;
1376 for (comparator
= cortex_m3
->dwt_comparator_list
;
1377 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1378 comparator
++, dwt_num
++)
1380 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1382 LOG_ERROR("Can not find free DWT Comparator");
1385 comparator
->used
= 1;
1386 watchpoint
->set
= dwt_num
+ 1;
1388 comparator
->comp
= watchpoint
->address
;
1389 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1392 comparator
->mask
= mask
;
1393 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1396 switch (watchpoint
->rw
) {
1398 comparator
->function
= 5;
1401 comparator
->function
= 6;
1404 comparator
->function
= 7;
1407 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1408 comparator
->function
);
1410 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1411 watchpoint
->unique_id
, dwt_num
,
1412 (unsigned) comparator
->comp
,
1413 (unsigned) comparator
->mask
,
1414 (unsigned) comparator
->function
);
1419 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1421 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1422 struct cortex_m3_dwt_comparator
*comparator
;
1425 if (!watchpoint
->set
)
1427 LOG_WARNING("watchpoint (wpid: %d) not set",
1428 watchpoint
->unique_id
);
1432 dwt_num
= watchpoint
->set
- 1;
1434 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1435 watchpoint
->unique_id
, dwt_num
,
1436 (unsigned) watchpoint
->address
);
1438 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1440 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1444 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1445 comparator
->used
= 0;
1446 comparator
->function
= 0;
1447 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1448 comparator
->function
);
1450 watchpoint
->set
= false;
1456 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1458 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1460 if (cortex_m3
->dwt_comp_available
< 1)
1462 LOG_DEBUG("no comparators?");
1463 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1466 /* hardware doesn't support data value masking */
1467 if (watchpoint
->mask
!= ~(uint32_t)0) {
1468 LOG_DEBUG("watchpoint value masks not supported");
1469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1472 /* hardware allows address masks of up to 32K */
1475 for (mask
= 0; mask
< 16; mask
++) {
1476 if ((1u << mask
) == watchpoint
->length
)
1480 LOG_DEBUG("unsupported watchpoint length");
1481 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1483 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1484 LOG_DEBUG("watchpoint address is unaligned");
1485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1488 /* Caller doesn't seem to be able to describe watching for data
1489 * values of zero; that flags "no value".
1491 * REVISIT This DWT may well be able to watch for specific data
1492 * values. Requires comparator #1 to set DATAVMATCH and match
1493 * the data, and another comparator (DATAVADDR0) matching addr.
1495 if (watchpoint
->value
) {
1496 LOG_DEBUG("data value watchpoint not YET supported");
1497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1500 cortex_m3
->dwt_comp_available
--;
1501 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1507 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1509 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1511 /* REVISIT why check? DWT can be updated with core running ... */
1512 if (target
->state
!= TARGET_HALTED
)
1514 LOG_WARNING("target not halted");
1515 return ERROR_TARGET_NOT_HALTED
;
1518 if (watchpoint
->set
)
1520 cortex_m3_unset_watchpoint(target
, watchpoint
);
1523 cortex_m3
->dwt_comp_available
++;
1524 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1529 static void cortex_m3_enable_watchpoints(struct target
*target
)
1531 struct watchpoint
*watchpoint
= target
->watchpoints
;
1533 /* set any pending watchpoints */
1536 if (!watchpoint
->set
)
1537 cortex_m3_set_watchpoint(target
, watchpoint
);
1538 watchpoint
= watchpoint
->next
;
1542 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1543 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1546 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1547 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1549 /* NOTE: we "know" here that the register identifiers used
1550 * in the v7m header match the Cortex-M3 Debug Core Register
1551 * Selector values for R0..R15, xPSR, MSP, and PSP.
1555 /* read a normal core register */
1556 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1558 if (retval
!= ERROR_OK
)
1560 LOG_ERROR("JTAG failure %i",retval
);
1561 return ERROR_JTAG_DEVICE_ERROR
;
1563 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1566 case ARMV7M_PRIMASK
:
1567 case ARMV7M_BASEPRI
:
1568 case ARMV7M_FAULTMASK
:
1569 case ARMV7M_CONTROL
:
1570 /* Cortex-M3 packages these four registers as bitfields
1571 * in one Debug Core register. So say r0 and r2 docs;
1572 * it was removed from r1 docs, but still works.
1574 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1578 case ARMV7M_PRIMASK
:
1579 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1582 case ARMV7M_BASEPRI
:
1583 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1586 case ARMV7M_FAULTMASK
:
1587 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1590 case ARMV7M_CONTROL
:
1591 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1595 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1599 return ERROR_INVALID_ARGUMENTS
;
1605 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1606 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1610 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1611 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1613 #ifdef ARMV7_GDB_HACKS
1614 /* If the LR register is being modified, make sure it will put us
1615 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1616 * hack to deal with the fact that gdb will sometimes "forge"
1617 * return addresses, and doesn't set the LSB correctly (i.e., when
1618 * printing expressions containing function calls, it sets LR = 0.)
1619 * Valid exception return codes have bit 0 set too.
1621 if (num
== ARMV7M_R14
)
1625 /* NOTE: we "know" here that the register identifiers used
1626 * in the v7m header match the Cortex-M3 Debug Core Register
1627 * Selector values for R0..R15, xPSR, MSP, and PSP.
1631 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1632 if (retval
!= ERROR_OK
)
1636 LOG_ERROR("JTAG failure");
1637 r
= armv7m
->core_cache
->reg_list
+ num
;
1638 r
->dirty
= r
->valid
;
1639 return ERROR_JTAG_DEVICE_ERROR
;
1641 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1644 case ARMV7M_PRIMASK
:
1645 case ARMV7M_BASEPRI
:
1646 case ARMV7M_FAULTMASK
:
1647 case ARMV7M_CONTROL
:
1648 /* Cortex-M3 packages these four registers as bitfields
1649 * in one Debug Core register. So say r0 and r2 docs;
1650 * it was removed from r1 docs, but still works.
1652 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1656 case ARMV7M_PRIMASK
:
1657 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1660 case ARMV7M_BASEPRI
:
1661 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1664 case ARMV7M_FAULTMASK
:
1665 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1668 case ARMV7M_CONTROL
:
1669 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1673 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1675 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1679 return ERROR_INVALID_ARGUMENTS
;
1685 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1686 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1688 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1689 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1690 int retval
= ERROR_INVALID_ARGUMENTS
;
1692 /* cortex_m3 handles unaligned memory access */
1693 if (count
&& buffer
) {
1696 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1699 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1702 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1710 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1711 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1713 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1714 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1715 int retval
= ERROR_INVALID_ARGUMENTS
;
1717 if (count
&& buffer
) {
1720 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1723 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1726 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1734 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1735 uint32_t count
, const uint8_t *buffer
)
1737 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1740 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1741 struct target
*target
)
1743 armv7m_build_reg_cache(target
);
1747 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1748 * on r/w if the core is not running, and clear on resume or reset ... or
1749 * at least, in a post_restore_context() method.
1752 struct dwt_reg_state
{
1753 struct target
*target
;
1755 uint32_t value
; /* scratch/cache */
1758 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1760 struct dwt_reg_state
*state
= reg
->arch_info
;
1762 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1765 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1767 struct dwt_reg_state
*state
= reg
->arch_info
;
1769 return target_write_u32(state
->target
, state
->addr
,
1770 buf_get_u32(buf
, 0, reg
->size
));
1779 static struct dwt_reg dwt_base_regs
[] = {
1780 { DWT_CTRL
, "dwt_ctrl", 32, },
1781 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1782 * increments while the core is asleep.
1784 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1785 /* plus some 8 bit counters, useful for profiling with TPIU */
1788 static struct dwt_reg dwt_comp
[] = {
1789 #define DWT_COMPARATOR(i) \
1790 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1791 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1792 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1797 #undef DWT_COMPARATOR
1800 static const struct reg_arch_type dwt_reg_type
= {
1801 .get
= cortex_m3_dwt_get_reg
,
1802 .set
= cortex_m3_dwt_set_reg
,
1806 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1808 struct dwt_reg_state
*state
;
1810 state
= calloc(1, sizeof *state
);
1813 state
->addr
= d
->addr
;
1818 r
->value
= &state
->value
;
1819 r
->arch_info
= state
;
1820 r
->type
= &dwt_reg_type
;
1824 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1827 struct reg_cache
*cache
;
1828 struct cortex_m3_dwt_comparator
*comparator
;
1831 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1833 LOG_DEBUG("no DWT");
1837 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1838 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1839 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1840 sizeof(struct cortex_m3_dwt_comparator
));
1841 if (!cm3
->dwt_comparator_list
) {
1843 cm3
->dwt_num_comp
= 0;
1844 LOG_ERROR("out of mem");
1848 cache
= calloc(1, sizeof *cache
);
1851 free(cm3
->dwt_comparator_list
);
1854 cache
->name
= "cortex-m3 dwt registers";
1855 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1856 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1857 if (!cache
->reg_list
) {
1862 for (reg
= 0; reg
< 2; reg
++)
1863 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1864 dwt_base_regs
+ reg
);
1866 comparator
= cm3
->dwt_comparator_list
;
1867 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1870 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1871 for (j
= 0; j
< 3; j
++, reg
++)
1872 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1873 dwt_comp
+ 3 * i
+ j
);
1876 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1877 cm3
->dwt_cache
= cache
;
1879 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1880 dwtcr
, cm3
->dwt_num_comp
,
1881 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1883 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1884 * implement single-address data value watchpoints ... so we
1885 * won't need to check it later, when asked to set one up.
1889 static int cortex_m3_examine(struct target
*target
)
1892 uint32_t cpuid
, fpcr
;
1894 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1895 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1897 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1900 if (!target_was_examined(target
))
1902 target_set_examined(target
);
1904 /* Read from Device Identification Registers */
1905 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1906 if (retval
!= ERROR_OK
)
1909 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1910 LOG_DEBUG("Cortex-M3 r%" PRId8
"p%" PRId8
" processor detected",
1911 (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1912 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1914 /* NOTE: FPB and DWT are both optional. */
1917 target_read_u32(target
, FP_CTRL
, &fpcr
);
1918 cortex_m3
->auto_bp_type
= 1;
1919 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1920 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1921 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1922 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1923 cortex_m3
->fpb_enabled
= fpcr
& 1;
1924 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1926 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1927 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1929 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1932 cortex_m3_dwt_setup(cortex_m3
, target
);
1934 /* These hardware breakpoints only work for code in flash! */
1935 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1936 target_name(target
),
1937 cortex_m3
->fp_num_code
,
1938 cortex_m3
->dwt_num_comp
);
1944 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1949 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1950 *ctrl
= (uint8_t)dcrdr
;
1951 *value
= (uint8_t)(dcrdr
>> 8);
1953 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1955 /* write ack back to software dcc register
1956 * signify we have read data */
1957 if (dcrdr
& (1 << 0))
1960 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1961 if (retval
!= ERROR_OK
)
1968 static int cortex_m3_target_request_data(struct target
*target
,
1969 uint32_t size
, uint8_t *buffer
)
1971 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1972 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1977 for (i
= 0; i
< (size
* 4); i
++)
1979 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1986 static int cortex_m3_handle_target_request(void *priv
)
1988 struct target
*target
= priv
;
1989 if (!target_was_examined(target
))
1991 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1992 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1994 if (!target
->dbg_msg_enabled
)
1997 if (target
->state
== TARGET_RUNNING
)
2002 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2004 /* check if we have data */
2005 if (ctrl
& (1 << 0))
2009 /* we assume target is quick enough */
2011 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2012 request
|= (data
<< 8);
2013 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2014 request
|= (data
<< 16);
2015 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
2016 request
|= (data
<< 24);
2017 target_request(target
, request
);
2024 static int cortex_m3_init_arch_info(struct target
*target
,
2025 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
2028 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2030 armv7m_init_arch_info(target
, armv7m
);
2032 /* prepare JTAG information for the new target */
2033 cortex_m3
->jtag_info
.tap
= tap
;
2034 cortex_m3
->jtag_info
.scann_size
= 4;
2036 /* default reset mode is to use srst if fitted
2037 * if not it will use CORTEX_M3_RESET_VECTRESET */
2038 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2040 armv7m
->arm
.dap
= &armv7m
->dap
;
2042 /* Leave (only) generic DAP stuff for debugport_init(); */
2043 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
2044 armv7m
->dap
.memaccess_tck
= 8;
2045 /* Cortex-M3 has 4096 bytes autoincrement range */
2046 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
2048 /* register arch-specific functions */
2049 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
2051 armv7m
->post_debug_entry
= NULL
;
2053 armv7m
->pre_restore_context
= NULL
;
2055 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
2056 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
2058 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
2060 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
2068 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
2070 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
2072 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
2073 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
2078 /*--------------------------------------------------------------------------*/
2080 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2081 struct cortex_m3_common
*cm3
)
2083 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2084 command_print(cmd_ctx
, "target is not a Cortex-M3");
2085 return ERROR_TARGET_INVALID
;
2091 * Only stuff below this line should need to verify that its target
2092 * is a Cortex-M3. Everything else should have indirected through the
2093 * cortexm3_target structure, which is only used with CM3 targets.
2096 static const struct {
2100 { "hard_err", VC_HARDERR
, },
2101 { "int_err", VC_INTERR
, },
2102 { "bus_err", VC_BUSERR
, },
2103 { "state_err", VC_STATERR
, },
2104 { "chk_err", VC_CHKERR
, },
2105 { "nocp_err", VC_NOCPERR
, },
2106 { "mm_err", VC_MMERR
, },
2107 { "reset", VC_CORERESET
, },
2110 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2112 struct target
*target
= get_current_target(CMD_CTX
);
2113 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2114 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2115 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
2119 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2120 if (retval
!= ERROR_OK
)
2123 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2124 if (retval
!= ERROR_OK
)
2130 if (CMD_ARGC
== 1) {
2131 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2132 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2133 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2134 | VC_MMERR
| VC_CORERESET
;
2136 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
2140 while (CMD_ARGC
-- > 0) {
2142 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2143 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2145 catch |= vec_ids
[i
].mask
;
2148 if (i
== ARRAY_SIZE(vec_ids
)) {
2149 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2150 return ERROR_INVALID_ARGUMENTS
;
2154 /* For now, armv7m->demcr only stores vector catch flags. */
2155 armv7m
->demcr
= catch;
2160 /* write, but don't assume it stuck (why not??) */
2161 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2162 if (retval
!= ERROR_OK
)
2164 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2165 if (retval
!= ERROR_OK
)
2168 /* FIXME be sure to clear DEMCR on clean server shutdown.
2169 * Otherwise the vector catch hardware could fire when there's
2170 * no debugger hooked up, causing much confusion...
2174 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
2176 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2177 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2183 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2185 struct target
*target
= get_current_target(CMD_CTX
);
2186 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2189 static const Jim_Nvp nvp_maskisr_modes
[] = {
2190 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2191 { .name
= "off" , .value
= CORTEX_M3_ISRMASK_OFF
},
2192 { .name
= "on" , .value
= CORTEX_M3_ISRMASK_ON
},
2193 { .name
= NULL
, .value
= -1 },
2198 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2199 if (retval
!= ERROR_OK
)
2202 if (target
->state
!= TARGET_HALTED
)
2204 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2210 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2211 if (n
->name
== NULL
)
2213 return ERROR_COMMAND_SYNTAX_ERROR
;
2215 cortex_m3
->isrmasking_mode
= n
->value
;
2218 if(cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2220 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2224 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2228 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2229 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s", n
->name
);
2234 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2236 struct target
*target
= get_current_target(CMD_CTX
);
2237 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2241 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2242 if (retval
!= ERROR_OK
)
2247 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2248 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2249 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2250 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2253 switch (cortex_m3
->soft_reset_config
)
2255 case CORTEX_M3_RESET_SYSRESETREQ
:
2256 reset_config
= "sysresetreq";
2259 case CORTEX_M3_RESET_VECTRESET
:
2260 reset_config
= "vectreset";
2264 reset_config
= "unknown";
2268 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2273 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2276 .handler
= handle_cortex_m3_mask_interrupts_command
,
2277 .mode
= COMMAND_EXEC
,
2278 .help
= "mask cortex_m3 interrupts",
2279 .usage
= "['auto'|'on'|'off']",
2282 .name
= "vector_catch",
2283 .handler
= handle_cortex_m3_vector_catch_command
,
2284 .mode
= COMMAND_EXEC
,
2285 .help
= "configure hardware vectors to trigger debug entry",
2286 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2289 .name
= "reset_config",
2290 .handler
= handle_cortex_m3_reset_config_command
,
2291 .mode
= COMMAND_ANY
,
2292 .help
= "configure software reset handling",
2293 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2295 COMMAND_REGISTRATION_DONE
2297 static const struct command_registration cortex_m3_command_handlers
[] = {
2299 .chain
= armv7m_command_handlers
,
2302 .name
= "cortex_m3",
2303 .mode
= COMMAND_EXEC
,
2304 .help
= "Cortex-M3 command group",
2305 .chain
= cortex_m3_exec_command_handlers
,
2307 COMMAND_REGISTRATION_DONE
2310 struct target_type cortexm3_target
=
2312 .name
= "cortex_m3",
2314 .poll
= cortex_m3_poll
,
2315 .arch_state
= armv7m_arch_state
,
2317 .target_request_data
= cortex_m3_target_request_data
,
2319 .halt
= cortex_m3_halt
,
2320 .resume
= cortex_m3_resume
,
2321 .step
= cortex_m3_step
,
2323 .assert_reset
= cortex_m3_assert_reset
,
2324 .deassert_reset
= cortex_m3_deassert_reset
,
2325 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2327 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2329 .read_memory
= cortex_m3_read_memory
,
2330 .write_memory
= cortex_m3_write_memory
,
2331 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2332 .checksum_memory
= armv7m_checksum_memory
,
2333 .blank_check_memory
= armv7m_blank_check_memory
,
2335 .run_algorithm
= armv7m_run_algorithm
,
2336 .start_algorithm
= armv7m_start_algorithm
,
2337 .wait_algorithm
= armv7m_wait_algorithm
,
2339 .add_breakpoint
= cortex_m3_add_breakpoint
,
2340 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2341 .add_watchpoint
= cortex_m3_add_watchpoint
,
2342 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2344 .commands
= cortex_m3_command_handlers
,
2345 .target_create
= cortex_m3_target_create
,
2346 .init_target
= cortex_m3_init_target
,
2347 .examine
= cortex_m3_examine
,