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Clarify LPC32XX address cycles message
[openocd/dsp568013.git] / src / flash / nand / lpc32xx.c
blob963dd13120a19f0735b99c29a3aef2b324cca7c6
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com> *
6 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
7 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
8 * *
9 * Based on a combination of the lpc3180 driver and code from *
10 * uboot-2009.03-lpc32xx by Kevin Wells. *
11 * Any bugs are mine. --BSt *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "imp.h"
33 #include "lpc32xx.h"
34 #include <target/target.h>
35
36 static int lpc32xx_reset(struct nand_device *nand);
37 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
38 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
39 extern int nand_correct_data(struct nand_device *nand, u_char *dat,
40 u_char *read_ecc, u_char *calc_ecc);
41
42 /* These are offset with the working area in IRAM when using DMA to
43 * read/write data to the SLC controller.
44 * - DMA descriptors will be put at start of working area,
45 * - Hardware generated ECC will be stored at ECC_OFFS
46 * - OOB wil be read/written from/to SPARE_OFFS
47 * - Actual page data will be read from/to DATA_OFFS
48 * There are unused holes between the used areas.
49 */
50 #define ECC_OFFS 0x120
51 #define SPARE_OFFS 0x140
52 #define DATA_OFFS 0x200
53
54 static int sp_ooblayout[] = {
55 10, 11, 12, 13, 14, 15
56 };
57 static int lp_ooblayout[] = {
58 40, 41, 42, 43, 44, 45,
59 46, 47, 48, 49, 50, 51,
60 52, 53, 54, 55, 56, 57,
61 58, 59, 60, 61, 62, 63
62 };
63
64 typedef struct {
65 volatile uint32_t dma_src;
66 volatile uint32_t dma_dest;
67 volatile uint32_t next_lli;
68 volatile uint32_t next_ctrl;
69 } dmac_ll_t;
70
71 static dmac_ll_t dmalist[(2048/256) * 2 + 1];
72
73 /* nand device lpc32xx <target#> <oscillator_frequency>
74 */
75 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
76 {
77 if (CMD_ARGC < 3) {
78 LOG_WARNING("incomplete 'lpc32xx' nand flash configuration");
79 return ERROR_FLASH_BANK_INVALID;
80 }
81
82 uint32_t osc_freq;
83 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
84
85 struct lpc32xx_nand_controller *lpc32xx_info;
86 lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
87 nand->controller_priv = lpc32xx_info;
88
89 lpc32xx_info->osc_freq = osc_freq;
90
91 if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
92 LOG_WARNING("LPC32xx oscillator frequency should be between "
93 "1000 and 20000 kHz, was %i",
94 lpc32xx_info->osc_freq);
95
96 lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
97 lpc32xx_info->sw_write_protection = 0;
98 lpc32xx_info->sw_wp_lower_bound = 0x0;
99 lpc32xx_info->sw_wp_upper_bound = 0x0;
100
101 return ERROR_OK;
102 }
103
104 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
105 {
106 int bypass = (pll_ctrl & 0x8000) >> 15;
107 int direct = (pll_ctrl & 0x4000) >> 14;
108 int feedback = (pll_ctrl & 0x2000) >> 13;
109 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
110 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
111 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
112 int lock = (pll_ctrl & 0x1);
113
114 if (!lock)
115 LOG_WARNING("PLL is not locked");
116
117 if (!bypass && direct) /* direct mode */
118 return (m * fclkin) / n;
119
120 if (bypass && !direct) /* bypass mode */
121 return fclkin / (2 * p);
122
123 if (bypass & direct) /* direct bypass mode */
124 return fclkin;
125
126 if (feedback) /* integer mode */
127 return m * (fclkin / n);
128 else /* non-integer mode */
129 return (m / (2 * p)) * (fclkin / n);
130 }
131
132 static float lpc32xx_cycle_time(struct nand_device *nand)
133 {
134 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
135 struct target *target = nand->target;
136 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
137 int sysclk;
138 int hclk;
139 int hclk_pll;
140 float cycle;
141 int retval;
142
143 /* calculate timings */
144
145 /* determine current SYSCLK (13'MHz or main oscillator) */
146 retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
147 if (ERROR_OK != retval) {
148 LOG_ERROR("could not read SYSCLK_CTRL");
149 return ERROR_NAND_OPERATION_FAILED;
150 }
151
152 if ((sysclk_ctrl & 1) == 0)
153 sysclk = lpc32xx_info->osc_freq;
154 else
155 sysclk = 13000;
156
157 /* determine selected HCLK source */
158 retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
159 if (ERROR_OK != retval) {
160 LOG_ERROR("could not read HCLK_CTRL");
161 return ERROR_NAND_OPERATION_FAILED;
162 }
163
164 if ((pwr_ctrl & (1 << 2)) == 0) { /* DIRECT RUN mode */
165 hclk = sysclk;
166 } else {
167 retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
168 if (ERROR_OK != retval) {
169 LOG_ERROR("could not read HCLKPLL_CTRL");
170 return ERROR_NAND_OPERATION_FAILED;
171 }
172 hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
173
174 retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
175 if (ERROR_OK != retval) {
176 LOG_ERROR("could not read CLKDIV_CTRL");
177 return ERROR_NAND_OPERATION_FAILED;
178 }
179
180 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
181 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
182 else /* HCLK uses HCLK_PLL */
183 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
184 }
185
186 LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
187
188 cycle = (1.0 / hclk) * 1000000.0;
189
190 return cycle;
191 }
192
193 static int lpc32xx_init(struct nand_device *nand)
194 {
195 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
196 struct target *target = nand->target;
197 int bus_width = nand->bus_width ? : 8;
198 int address_cycles = nand->address_cycles ? : 3;
199 int page_size = nand->page_size ? : 512;
200 int retval;
201
202 if (target->state != TARGET_HALTED) {
203 LOG_ERROR("target must be halted to use LPC32xx "
204 "NAND flash controller");
205 return ERROR_NAND_OPERATION_FAILED;
206 }
207
208 /* sanitize arguments */
209 if (bus_width != 8) {
210 LOG_ERROR("LPC32xx doesn't support %i", bus_width);
211 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
212 }
213
214 /* inform calling code about selected bus width */
215 nand->bus_width = bus_width;
216
217 if ((address_cycles != 3) && (address_cycles != 4)) {
218 LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
219 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
220 }
221
222 if ((page_size != 512) && (page_size != 2048)) {
223 LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
224 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
225 }
226
227 /* select MLC controller if none is currently selected */
228 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
229 LOG_DEBUG("no LPC32xx NAND flash controller selected, "
230 "using default 'mlc'");
231 lpc32xx_info->selected_controller = LPC32xx_MLC_CONTROLLER;
232 }
233
234 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
235 uint32_t mlc_icr_value = 0x0;
236 float cycle;
237 int twp, twh, trp, treh, trhz, trbwb, tcea;
238
239 /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
240 retval = target_write_u32(target, 0x400040c8, 0x22);
241 if (ERROR_OK != retval) {
242 LOG_ERROR("could not set FLASHCLK_CTRL");
243 return ERROR_NAND_OPERATION_FAILED;
244 }
245
246 /* MLC_CEH = 0x0 (Force nCE assert) */
247 retval = target_write_u32(target, 0x200b804c, 0x0);
248 if (ERROR_OK != retval) {
249 LOG_ERROR("could not set MLC_CEH");
250 return ERROR_NAND_OPERATION_FAILED;
251 }
252
253 /* MLC_LOCK = 0xa25e (unlock protected registers) */
254 retval = target_write_u32(target, 0x200b8044, 0xa25e);
255 if (ERROR_OK != retval) {
256 LOG_ERROR("could not set MLC_LOCK");
257 return ERROR_NAND_OPERATION_FAILED;
258 }
259
260 /* MLC_ICR = configuration */
261 if (lpc32xx_info->sw_write_protection)
262 mlc_icr_value |= 0x8;
263 if (page_size == 2048)
264 mlc_icr_value |= 0x4;
265 if (address_cycles == 4)
266 mlc_icr_value |= 0x2;
267 if (bus_width == 16)
268 mlc_icr_value |= 0x1;
269 retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
270 if (ERROR_OK != retval) {
271 LOG_ERROR("could not set MLC_ICR");
272 return ERROR_NAND_OPERATION_FAILED;
273 }
274
275 /* calculate NAND controller timings */
276 cycle = lpc32xx_cycle_time(nand);
277
278 twp = ((40 / cycle) + 1);
279 twh = ((20 / cycle) + 1);
280 trp = ((30 / cycle) + 1);
281 treh = ((15 / cycle) + 1);
282 trhz = ((30 / cycle) + 1);
283 trbwb = ((100 / cycle) + 1);
284 tcea = ((45 / cycle) + 1);
285
286 /* MLC_LOCK = 0xa25e (unlock protected registers) */
287 retval = target_write_u32(target, 0x200b8044, 0xa25e);
288 if (ERROR_OK != retval) {
289 LOG_ERROR("could not set MLC_LOCK");
290 return ERROR_NAND_OPERATION_FAILED;
291 }
292
293 /* MLC_TIME_REG */
294 retval = target_write_u32(target, 0x200b8034,
295 (twp & 0xf)
296 | ((twh & 0xf) << 4)
297 | ((trp & 0xf) << 8)
298 | ((treh & 0xf) << 12)
299 | ((trhz & 0x7) << 16)
300 | ((trbwb & 0x1f) << 19)
301 | ((tcea & 0x3) << 24));
302 if (ERROR_OK != retval) {
303 LOG_ERROR("could not set MLC_TIME_REG");
304 return ERROR_NAND_OPERATION_FAILED;
305 }
306
307 retval = lpc32xx_reset(nand);
308 if (ERROR_OK != retval)
309 return ERROR_NAND_OPERATION_FAILED;
310 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
311 float cycle;
312 int r_setup, r_hold, r_width, r_rdy;
313 int w_setup, w_hold, w_width, w_rdy;
314
315 /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
316 retval = target_write_u32(target, 0x400040c8, 0x05);
317 if (ERROR_OK != retval) {
318 LOG_ERROR("could not set FLASHCLK_CTRL");
319 return ERROR_NAND_OPERATION_FAILED;
320 }
321
322 /* after reset set other registers of SLC,
323 * so reset calling is here at the begining
324 */
325 retval = lpc32xx_reset(nand);
326 if (ERROR_OK != retval)
327 return ERROR_NAND_OPERATION_FAILED;
328
329 /* SLC_CFG =
330 Force nCE assert,
331 DMA ECC enabled,
332 ECC enabled,
333 DMA burst enabled,
334 DMA read from SLC,
335 WIDTH = bus_width)
336 */
337 retval = target_write_u32(target, 0x20020014,
338 0x3e | (bus_width == 16) ? 1 : 0);
339 if (ERROR_OK != retval) {
340 LOG_ERROR("could not set SLC_CFG");
341 return ERROR_NAND_OPERATION_FAILED;
342 }
343
344 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
345 retval = target_write_u32(target, 0x20020020, 0x03);
346 if (ERROR_OK != retval) {
347 LOG_ERROR("could not set SLC_IEN");
348 return ERROR_NAND_OPERATION_FAILED;
349 }
350
351 /* DMA configuration */
352
353 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
354 retval = target_write_u32(target, 0x400040e8, 0x01);
355 if (ERROR_OK != retval) {
356 LOG_ERROR("could not set DMACLK_CTRL");
357 return ERROR_NAND_OPERATION_FAILED;
358 }
359
360 /* DMACConfig = DMA enabled*/
361 retval = target_write_u32(target, 0x31000030, 0x01);
362 if (ERROR_OK != retval) {
363 LOG_ERROR("could not set DMACConfig");
364 return ERROR_NAND_OPERATION_FAILED;
365 }
366
367 /* calculate NAND controller timings */
368 cycle = lpc32xx_cycle_time(nand);
369
370 r_setup = w_setup = 0;
371 r_hold = w_hold = 10 / cycle;
372 r_width = 30 / cycle;
373 w_width = 40 / cycle;
374 r_rdy = w_rdy = 100 / cycle;
375
376 /* SLC_TAC: SLC timing arcs register */
377 retval = target_write_u32(target, 0x2002002c,
378 (r_setup & 0xf)
379 | ((r_hold & 0xf) << 4)
380 | ((r_width & 0xf) << 8)
381 | ((r_rdy & 0xf) << 12)
382 | ((w_setup & 0xf) << 16)
383 | ((w_hold & 0xf) << 20)
384 | ((w_width & 0xf) << 24)
385 | ((w_rdy & 0xf) << 28));
386 if (ERROR_OK != retval) {
387 LOG_ERROR("could not set SLC_TAC");
388 return ERROR_NAND_OPERATION_FAILED;
389 }
390 }
391
392 return ERROR_OK;
393 }
394
395 static int lpc32xx_reset(struct nand_device *nand)
396 {
397 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
398 struct target *target = nand->target;
399 int retval;
400
401 if (target->state != TARGET_HALTED) {
402 LOG_ERROR("target must be halted to use "
403 "LPC32xx NAND flash controller");
404 return ERROR_NAND_OPERATION_FAILED;
405 }
406
407 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
408 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
409 return ERROR_NAND_OPERATION_FAILED;
410 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
411 /* MLC_CMD = 0xff (reset controller and NAND device) */
412 retval = target_write_u32(target, 0x200b8000, 0xff);
413 if (ERROR_OK != retval) {
414 LOG_ERROR("could not set MLC_CMD");
415 return ERROR_NAND_OPERATION_FAILED;
416 }
417
418 if (!lpc32xx_controller_ready(nand, 100)) {
419 LOG_ERROR("LPC32xx MLC NAND controller timed out "
420 "after reset");
421 return ERROR_NAND_OPERATION_TIMEOUT;
422 }
423 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
424 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
425 retval = target_write_u32(target, 0x20020010, 0x6);
426 if (ERROR_OK != retval) {
427 LOG_ERROR("could not set SLC_CTRL");
428 return ERROR_NAND_OPERATION_FAILED;
429 }
430
431 if (!lpc32xx_controller_ready(nand, 100))
432 {
433 LOG_ERROR("LPC32xx SLC NAND controller timed out "
434 "after reset");
435 return ERROR_NAND_OPERATION_TIMEOUT;
436 }
437 }
438
439 return ERROR_OK;
440 }
441
442 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
443 {
444 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
445 struct target *target = nand->target;
446 int retval;
447
448 if (target->state != TARGET_HALTED) {
449 LOG_ERROR("target must be halted to use "
450 "LPC32xx NAND flash controller");
451 return ERROR_NAND_OPERATION_FAILED;
452 }
453
454 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
455 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
456 return ERROR_NAND_OPERATION_FAILED;
457 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
458 /* MLC_CMD = command */
459 retval = target_write_u32(target, 0x200b8000, command);
460 if (ERROR_OK != retval) {
461 LOG_ERROR("could not set MLC_CMD");
462 return ERROR_NAND_OPERATION_FAILED;
463 }
464 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
465 /* SLC_CMD = command */
466 retval = target_write_u32(target, 0x20020008, command);
467 if (ERROR_OK != retval) {
468 LOG_ERROR("could not set SLC_CMD");
469 return ERROR_NAND_OPERATION_FAILED;
470 }
471 }
472
473 return ERROR_OK;
474 }
475
476 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
477 {
478 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
479 struct target *target = nand->target;
480 int retval;
481
482 if (target->state != TARGET_HALTED) {
483 LOG_ERROR("target must be halted to use "
484 "LPC32xx NAND flash controller");
485 return ERROR_NAND_OPERATION_FAILED;
486 }
487
488 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
489 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
490 return ERROR_NAND_OPERATION_FAILED;
491 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
492 /* MLC_ADDR = address */
493 retval = target_write_u32(target, 0x200b8004, address);
494 if (ERROR_OK != retval) {
495 LOG_ERROR("could not set MLC_ADDR");
496 return ERROR_NAND_OPERATION_FAILED;
497 }
498 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
499 /* SLC_ADDR = address */
500 retval = target_write_u32(target, 0x20020004, address);
501 if (ERROR_OK != retval) {
502 LOG_ERROR("could not set SLC_ADDR");
503 return ERROR_NAND_OPERATION_FAILED;
504 }
505 }
506
507 return ERROR_OK;
508 }
509
510 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
511 {
512 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
513 struct target *target = nand->target;
514 int retval;
515
516 if (target->state != TARGET_HALTED) {
517 LOG_ERROR("target must be halted to use "
518 "LPC32xx NAND flash controller");
519 return ERROR_NAND_OPERATION_FAILED;
520 }
521
522 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
523 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
524 return ERROR_NAND_OPERATION_FAILED;
525 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
526 /* MLC_DATA = data */
527 retval = target_write_u32(target, 0x200b0000, data);
528 if (ERROR_OK != retval) {
529 LOG_ERROR("could not set MLC_DATA");
530 return ERROR_NAND_OPERATION_FAILED;
531 }
532 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
533 /* SLC_DATA = data */
534 retval = target_write_u32(target, 0x20020000, data);
535 if (ERROR_OK != retval) {
536 LOG_ERROR("could not set SLC_DATA");
537 return ERROR_NAND_OPERATION_FAILED;
538 }
539 }
540
541 return ERROR_OK;
542 }
543
544 static int lpc32xx_read_data(struct nand_device *nand, void *data)
545 {
546 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
547 struct target *target = nand->target;
548 int retval;
549
550 if (target->state != TARGET_HALTED) {
551 LOG_ERROR("target must be halted to use LPC32xx "
552 "NAND flash controller");
553 return ERROR_NAND_OPERATION_FAILED;
554 }
555
556 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
557 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
558 return ERROR_NAND_OPERATION_FAILED;
559 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
560 /* data = MLC_DATA, use sized access */
561 if (nand->bus_width == 8) {
562 uint8_t *data8 = data;
563 retval = target_read_u8(target, 0x200b0000, data8);
564 } else {
565 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
566 return ERROR_NAND_OPERATION_FAILED;
567 }
568 if (ERROR_OK != retval) {
569 LOG_ERROR("could not read MLC_DATA");
570 return ERROR_NAND_OPERATION_FAILED;
571 }
572 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
573 uint32_t data32;
574
575 /* data = SLC_DATA, must use 32-bit access */
576 retval = target_read_u32(target, 0x20020000, &data32);
577 if (ERROR_OK != retval) {
578 LOG_ERROR("could not read SLC_DATA");
579 return ERROR_NAND_OPERATION_FAILED;
580 }
581
582 if (nand->bus_width == 8) {
583 uint8_t *data8 = data;
584 *data8 = data32 & 0xff;
585 } else {
586 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
587 return ERROR_NAND_OPERATION_FAILED;
588 }
589 }
590
591 return ERROR_OK;
592 }
593
594 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
595 uint8_t *data, uint32_t data_size,
596 uint8_t *oob, uint32_t oob_size)
597 {
598 struct target *target = nand->target;
599 int retval;
600 uint8_t status;
601 static uint8_t page_buffer[512];
602 static uint8_t oob_buffer[6];
603 int quarter, num_quarters;
604
605 /* MLC_CMD = sequential input */
606 retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
607 if (ERROR_OK != retval) {
608 LOG_ERROR("could not set MLC_CMD");
609 return ERROR_NAND_OPERATION_FAILED;
610 }
611
612 if (nand->page_size == 512) {
613 /* MLC_ADDR = 0x0 (one column cycle) */
614 retval = target_write_u32(target, 0x200b8004, 0x0);
615 if (ERROR_OK != retval) {
616 LOG_ERROR("could not set MLC_ADDR");
617 return ERROR_NAND_OPERATION_FAILED;
618 }
619
620 /* MLC_ADDR = row */
621 retval = target_write_u32(target, 0x200b8004, page & 0xff);
622 if (ERROR_OK != retval) {
623 LOG_ERROR("could not set MLC_ADDR");
624 return ERROR_NAND_OPERATION_FAILED;
625 }
626 retval = target_write_u32(target, 0x200b8004,
627 (page >> 8) & 0xff);
628 if (ERROR_OK != retval) {
629 LOG_ERROR("could not set MLC_ADDR");
630 return ERROR_NAND_OPERATION_FAILED;
631 }
632
633 if (nand->address_cycles == 4) {
634 retval = target_write_u32(target, 0x200b8004,
635 (page >> 16) & 0xff);
636 if (ERROR_OK != retval) {
637 LOG_ERROR("could not set MLC_ADDR");
638 return ERROR_NAND_OPERATION_FAILED;
639 }
640 }
641 } else {
642 /* MLC_ADDR = 0x0 (two column cycles) */
643 retval = target_write_u32(target, 0x200b8004, 0x0);
644 if (ERROR_OK != retval) {
645 LOG_ERROR("could not set MLC_ADDR");
646 return ERROR_NAND_OPERATION_FAILED;
647 }
648 retval = target_write_u32(target, 0x200b8004, 0x0);
649 if (ERROR_OK != retval) {
650 LOG_ERROR("could not set MLC_ADDR");
651 return ERROR_NAND_OPERATION_FAILED;
652 }
653
654 /* MLC_ADDR = row */
655 retval = target_write_u32(target, 0x200b8004, page & 0xff);
656 if (ERROR_OK != retval) {
657 LOG_ERROR("could not set MLC_ADDR");
658 return ERROR_NAND_OPERATION_FAILED;
659 }
660 retval = target_write_u32(target, 0x200b8004,
661 (page >> 8) & 0xff);
662 if (ERROR_OK != retval) {
663 LOG_ERROR("could not set MLC_ADDR");
664 return ERROR_NAND_OPERATION_FAILED;
665 }
666 }
667
668 /* when using the MLC controller, we have to treat a large page device
669 * as being made out of four quarters, each the size of a small page
670 * device
671 */
672 num_quarters = (nand->page_size == 2048) ? 4 : 1;
673
674 for (quarter = 0; quarter < num_quarters; quarter++) {
675 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
676 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
677
678 memset(page_buffer, 0xff, 512);
679 if (data) {
680 memcpy(page_buffer, data, thisrun_data_size);
681 data_size -= thisrun_data_size;
682 data += thisrun_data_size;
683 }
684
685 memset(oob_buffer, 0xff, 6);
686 if (oob) {
687 memcpy(oob_buffer, oob, thisrun_oob_size);
688 oob_size -= thisrun_oob_size;
689 oob += thisrun_oob_size;
690 }
691
692 /* write MLC_ECC_ENC_REG to start encode cycle */
693 retval = target_write_u32(target, 0x200b8008, 0x0);
694 if (ERROR_OK != retval) {
695 LOG_ERROR("could not set MLC_ECC_ENC_REG");
696 return ERROR_NAND_OPERATION_FAILED;
697 }
698
699 retval = target_write_memory(target, 0x200a8000,
700 4, 128, page_buffer);
701 if (ERROR_OK != retval) {
702 LOG_ERROR("could not set MLC_BUF (data)");
703 return ERROR_NAND_OPERATION_FAILED;
704 }
705 retval = target_write_memory(target, 0x200a8000,
706 1, 6, oob_buffer);
707 if (ERROR_OK != retval) {
708 LOG_ERROR("could not set MLC_BUF (oob)");
709 return ERROR_NAND_OPERATION_FAILED;
710 }
711
712 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
713 retval = target_write_u32(target, 0x200b8010, 0x0);
714 if (ERROR_OK != retval) {
715 LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
716 return ERROR_NAND_OPERATION_FAILED;
717 }
718
719 if (!lpc32xx_controller_ready(nand, 1000)) {
720 LOG_ERROR("timeout while waiting for "
721 "completion of auto encode cycle");
722 return ERROR_NAND_OPERATION_FAILED;
723 }
724 }
725
726 /* MLC_CMD = auto program command */
727 retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
728 if (ERROR_OK != retval) {
729 LOG_ERROR("could not set MLC_CMD");
730 return ERROR_NAND_OPERATION_FAILED;
731 }
732
733 if ((retval = nand_read_status(nand, &status)) != ERROR_OK) {
734 LOG_ERROR("couldn't read status");
735 return ERROR_NAND_OPERATION_FAILED;
736 }
737
738 if (status & NAND_STATUS_FAIL) {
739 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
740 status);
741 return ERROR_NAND_OPERATION_FAILED;
742 }
743
744 return ERROR_OK;
745 }
746
747 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
748 * target internal memory. The transfer to/from flash is done by DMA. This
749 * function sets up the dma linked list in host memory for later transfer to
750 * target.
751 */
752 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
753 int do_read)
754 {
755 uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
756
757 /* DMACCxControl =
758 TransferSize =64,
759 Source burst size =16,
760 Destination burst size = 16,
761 Source transfer width = 32 bit,
762 Destination transfer width = 32 bit,
763 Source AHB master select = M0,
764 Destination AHB master select = M0,
765 Source increment = 0, // set later
766 Destination increment = 0, // set later
767 Terminal count interrupt enable bit = 0 // set on last
768 */ /*
769 * Write Operation Sequence for Small Block NAND
770 * ----------------------------------------------------------
771 * 1. X'fer 256 bytes of data from Memory to Flash.
772 * 2. Copy generated ECC data from Register to Spare Area
773 * 3. X'fer next 256 bytes of data from Memory to Flash.
774 * 4. Copy generated ECC data from Register to Spare Area.
775 * 5. X'fer 16 byets of Spare area from Memory to Flash.
776 * Read Operation Sequence for Small Block NAND
777 * ----------------------------------------------------------
778 * 1. X'fer 256 bytes of data from Flash to Memory.
779 * 2. Copy generated ECC data from Register to ECC calc Buffer.
780 * 3. X'fer next 256 bytes of data from Flash to Memory.
781 * 4. Copy generated ECC data from Register to ECC calc Buffer.
782 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
783 * Write Operation Sequence for Large Block NAND
784 * ----------------------------------------------------------
785 * 1. Steps(1-4) of Write Operations repeate for four times
786 * which generates 16 DMA descriptors to X'fer 2048 bytes of
787 * data & 32 bytes of ECC data.
788 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
789 * Read Operation Sequence for Large Block NAND
790 * ----------------------------------------------------------
791 * 1. Steps(1-4) of Read Operations repeate for four times
792 * which generates 16 DMA descriptors to X'fer 2048 bytes of
793 * data & 32 bytes of ECC data.
794 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
795 */
796
797 ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
798 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
799
800 /* DMACCxControl =
801 TransferSize =1,
802 Source burst size =4,
803 Destination burst size = 4,
804 Source transfer width = 32 bit,
805 Destination transfer width = 32 bit,
806 Source AHB master select = M0,
807 Destination AHB master select = M0,
808 Source increment = 0,
809 Destination increment = 1,
810 Terminal count interrupt enable bit = 0
811 */
812 ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
813 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
814
815 /* DMACCxControl =
816 TransferSize =16 for lp or 4 for sp,
817 Source burst size =16,
818 Destination burst size = 16,
819 Source transfer width = 32 bit,
820 Destination transfer width = 32 bit,
821 Source AHB master select = M0,
822 Destination AHB master select = M0,
823 Source increment = 0, // set later
824 Destination increment = 0, // set later
825 Terminal count interrupt enable bit = 1 // set on last
826 */
827 oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
828 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
829 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
830 if (do_read) {
831 ctrl |= 1 << 27; /* Destination increment = 1 */
832 oob_ctrl |= 1 << 27; /* Destination increment = 1 */
833 dmasrc = 0x20020038; /* SLC_DMA_DATA */
834 dmadst = target_mem_base + DATA_OFFS;
835 } else {
836 ctrl |= 1 << 26; /* Source increment = 1 */
837 oob_ctrl |= 1 << 26; /* Source increment = 1 */
838 dmasrc = target_mem_base + DATA_OFFS;
839 dmadst = 0x20020038; /* SLC_DMA_DATA */
840 }
841 /*
842 * Write Operation Sequence for Small Block NAND
843 * ----------------------------------------------------------
844 * 1. X'fer 256 bytes of data from Memory to Flash.
845 * 2. Copy generated ECC data from Register to Spare Area
846 * 3. X'fer next 256 bytes of data from Memory to Flash.
847 * 4. Copy generated ECC data from Register to Spare Area.
848 * 5. X'fer 16 byets of Spare area from Memory to Flash.
849 * Read Operation Sequence for Small Block NAND
850 * ----------------------------------------------------------
851 * 1. X'fer 256 bytes of data from Flash to Memory.
852 * 2. Copy generated ECC data from Register to ECC calc Buffer.
853 * 3. X'fer next 256 bytes of data from Flash to Memory.
854 * 4. Copy generated ECC data from Register to ECC calc Buffer.
855 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
856 * Write Operation Sequence for Large Block NAND
857 * ----------------------------------------------------------
858 * 1. Steps(1-4) of Write Operations repeate for four times
859 * which generates 16 DMA descriptors to X'fer 2048 bytes of
860 * data & 32 bytes of ECC data.
861 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
862 * Read Operation Sequence for Large Block NAND
863 * ----------------------------------------------------------
864 * 1. Steps(1-4) of Read Operations repeate for four times
865 * which generates 16 DMA descriptors to X'fer 2048 bytes of
866 * data & 32 bytes of ECC data.
867 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
868 */
869 for (i = 0; i < page_size/0x100; i++)
870 {
871 dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
872 dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
873 dmalist[i*2].next_lli =
874 target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
875 dmalist[i*2].next_ctrl = ctrl;
876
877 dmalist[(i*2) + 1].dma_src = 0x20020034; /* SLC_ECC */
878 dmalist[(i*2) + 1].dma_dest =
879 target_mem_base + ECC_OFFS + i * 4;
880 dmalist[(i*2) + 1].next_lli =
881 target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
882 dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
883
884 }
885 if (do_read)
886 {
887 dmadst = target_mem_base + SPARE_OFFS;
888 } else {
889 dmasrc = target_mem_base + SPARE_OFFS;
890 dmalist[(i*2) - 1].next_lli = 0; /* last link = null on write */
891 dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
892 }
893 dmalist[i*2].dma_src = dmasrc;
894 dmalist[i*2].dma_dest = dmadst;
895 dmalist[i*2].next_lli = 0;
896 dmalist[i*2].next_ctrl = oob_ctrl;
897
898 return (i*2 + 1); /* Number of descriptors */
899 }
900
901 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
902 int do_wait)
903 {
904 struct target *target = nand->target;
905 int retval;
906
907 /* DMACIntTCClear = ch0 */
908 retval = target_write_u32(target, 0x31000008, 1);
909 if (ERROR_OK != retval) {
910 LOG_ERROR("Could not set DMACIntTCClear");
911 return retval;
912 }
913
914 /* DMACIntErrClear = ch0 */
915 retval = target_write_u32(target, 0x31000010, 1);
916 if (ERROR_OK != retval) {
917 LOG_ERROR("Could not set DMACIntErrClear");
918 return retval;
919 }
920
921 /* DMACCxConfig=
922 E=1,
923 SrcPeripheral = 1 (SLC),
924 DestPeripheral = 1 (SLC),
925 FlowCntrl = 2 (Pher -> Mem, DMA),
926 IE = 0,
927 ITC = 0,
928 L= 0,
929 H=0
930 */
931 retval = target_write_u32(target, 0x31000110,
932 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
933 | 0<<15 | 0<<16 | 0<<18);
934 if (ERROR_OK != retval) {
935 LOG_ERROR("Could not set DMACC0Config");
936 return retval;
937 }
938
939 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
940 retval = target_write_u32(target, 0x20020010, 0x3);
941 if (ERROR_OK != retval) {
942 LOG_ERROR("Could not set SLC_CTRL");
943 return retval;
944 }
945
946 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
947 retval = target_write_u32(target, 0x20020028, 2);
948 if (ERROR_OK != retval) {
949 LOG_ERROR("Could not set SLC_ICR");
950 return retval;
951 }
952
953 /* SLC_TC */
954 retval = target_write_u32(target, 0x20020030, count);
955 if (ERROR_OK != retval) {
956 LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
957 return retval;
958 }
959
960 /* Wait finish */
961 if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
962 LOG_ERROR("timeout while waiting for completion of DMA");
963 return ERROR_NAND_OPERATION_FAILED;
964 }
965
966 return retval;
967 }
968
969 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
970 {
971 struct target *target = nand->target;
972
973 LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
974
975 do {
976 uint32_t tc_stat;
977 uint32_t err_stat;
978 int retval;
979
980 /* Read DMACRawIntTCStat */
981 retval = target_read_u32(target, 0x31000014, &tc_stat);
982 if (ERROR_OK != retval) {
983 LOG_ERROR("Could not read DMACRawIntTCStat");
984 return 0;
985 }
986 /* Read DMACRawIntErrStat */
987 retval = target_read_u32(target, 0x31000018, &err_stat);
988 if (ERROR_OK != retval) {
989 LOG_ERROR("Could not read DMACRawIntErrStat");
990 return 0;
991 }
992 if ((tc_stat | err_stat) & 1) {
993 LOG_DEBUG("lpc32xx_dma_ready count=%d",
994 timeout);
995 if (err_stat & 1) {
996 LOG_ERROR("lpc32xx_dma_ready "
997 "DMA error, aborted");
998 return 0;
999 } else {
1000 return 1;
1001 }
1002 }
1003
1004 alive_sleep(1);
1005 } while (timeout-- > 0);
1006
1007 return 0;
1008 }
1009
1010 static uint32_t slc_ecc_copy_to_buffer(uint8_t * spare,
1011 const uint32_t * ecc, int count)
1012 {
1013 int i;
1014 for (i = 0; i < (count * 3); i += 3) {
1015 uint32_t ce = ecc[i/3];
1016 ce = ~(ce << 2) & 0xFFFFFF;
1017 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1018 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1019 spare[i] = (uint8_t)(ce & 0xFF);
1020 }
1021 return 0;
1022 }
1023
1024 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1025 {
1026 int addr = 0;
1027 while (oob_size > 0) {
1028 LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1029 oob[0], oob[1], oob[2], oob[3],
1030 oob[4], oob[5], oob[6], oob[7]);
1031 oob += 8;
1032 addr += 8;
1033 oob_size -= 8;
1034 }
1035 }
1036
1037 static int lpc32xx_write_page_slc(struct nand_device *nand,
1038 struct working_area *pworking_area,
1039 uint32_t page, uint8_t *data,
1040 uint32_t data_size, uint8_t *oob,
1041 uint32_t oob_size)
1042 {
1043 struct target *target = nand->target;
1044 int retval;
1045 uint32_t target_mem_base;
1046
1047 LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
1048 "data_size=%d, oob_size=%d",
1049 page, data != 0, oob != 0, data_size, oob_size);
1050
1051 target_mem_base = pworking_area->address;
1052 /*
1053 * Skip writting page which has all 0xFF data as this will
1054 * generate 0x0 value.
1055 */
1056 if (data && !oob) {
1057 uint32_t i, all_ff = 1;
1058 for (i = 0; i < data_size; i++)
1059 if (data[i] != 0xFF) {
1060 all_ff = 0;
1061 break;
1062 }
1063 if (all_ff)
1064 return ERROR_OK;
1065 }
1066 /* Make the dma descriptors in local memory */
1067 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1068 /* Write them to target.
1069 XXX: Assumes host and target have same byte sex.
1070 */
1071 retval = target_write_memory(target, target_mem_base, 4,
1072 nll * sizeof(dmac_ll_t) / 4,
1073 (uint8_t *)dmalist);
1074 if (ERROR_OK != retval) {
1075 LOG_ERROR("Could not write DMA descriptors to IRAM");
1076 return retval;
1077 }
1078
1079 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1080 if (ERROR_OK != retval) {
1081 LOG_ERROR("NAND_CMD_SEQIN failed");
1082 return retval;
1083 }
1084
1085 /* SLC_CFG =
1086 Force nCE assert,
1087 DMA ECC enabled,
1088 ECC enabled,
1089 DMA burst enabled,
1090 DMA write to SLC,
1091 WIDTH = bus_width
1092 */
1093 retval = target_write_u32(target, 0x20020014, 0x3c);
1094 if (ERROR_OK != retval) {
1095 LOG_ERROR("Could not set SLC_CFG");
1096 return retval;
1097 }
1098 if (data) {
1099 /* Write data to target */
1100 static uint8_t fdata[2048];
1101 memset(fdata, 0xFF, nand->page_size);
1102 memcpy(fdata, data, data_size);
1103 retval = target_write_memory(target,
1104 target_mem_base + DATA_OFFS,
1105 4, nand->page_size/4, fdata);
1106 if (ERROR_OK != retval) {
1107 LOG_ERROR("Could not write data to IRAM");
1108 return retval;
1109 }
1110
1111 /* Write first decriptor to DMA controller */
1112 retval = target_write_memory(target, 0x31000100, 4,
1113 sizeof(dmac_ll_t) / 4,
1114 (uint8_t *)dmalist);
1115 if (ERROR_OK != retval) {
1116 LOG_ERROR("Could not write DMA descriptor to DMAC");
1117 return retval;
1118 }
1119
1120 /* Start xfer of data from iram to flash using DMA */
1121 int tot_size = nand->page_size;
1122 tot_size += tot_size == 2048 ? 64 : 16;
1123 retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1124 if (ERROR_OK != retval) {
1125 LOG_ERROR("DMA failed");
1126 return retval;
1127 }
1128
1129 /* Wait for DMA to finish. SLC is not finished at this stage */
1130 if (!lpc32xx_dma_ready(nand, 100)) {
1131 LOG_ERROR("Data DMA failed during write");
1132 return ERROR_FLASH_OPERATION_FAILED;
1133 }
1134 } /* data xfer */
1135
1136 /* Copy OOB to iram */
1137 static uint8_t foob[64];
1138 int foob_size = nand->page_size == 2048 ? 64 : 16;
1139 memset(foob, 0xFF, foob_size);
1140 if (oob) { /* Raw mode */
1141 memcpy(foob, oob, oob_size);
1142 } else {
1143 /* Get HW generated ECC, made while writing data */
1144 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1145 static uint32_t hw_ecc[8];
1146 retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1147 4, ecc_count, (uint8_t *)hw_ecc);
1148 if (ERROR_OK != retval) {
1149 LOG_ERROR("Reading hw generated ECC from IRAM failed");
1150 return retval;
1151 }
1152 /* Copy to oob, at correct offsets */
1153 static uint8_t ecc[24];
1154 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1155 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1156 int i;
1157 for (i = 0; i < ecc_count * 3; i++)
1158 foob[layout[i]] = ecc[i];
1159 lpc32xx_dump_oob(foob, foob_size);
1160 }
1161 retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1162 foob_size / 4, foob);
1163 if (ERROR_OK != retval) {
1164 LOG_ERROR("Writing OOB to IRAM failed");
1165 return retval;
1166 }
1167
1168 /* Write OOB decriptor to DMA controller */
1169 retval = target_write_memory(target, 0x31000100, 4,
1170 sizeof(dmac_ll_t) / 4,
1171 (uint8_t *)(&dmalist[nll-1]));
1172 if (ERROR_OK != retval) {
1173 LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1174 return retval;
1175 }
1176 if (data) {
1177 /* Only restart DMA with last descriptor,
1178 * don't setup SLC again */
1179
1180 /* DMACIntTCClear = ch0 */
1181 retval = target_write_u32(target, 0x31000008, 1);
1182 if (ERROR_OK != retval) {
1183 LOG_ERROR("Could not set DMACIntTCClear");
1184 return retval;
1185 }
1186 /* DMACCxConfig=
1187 E=1,
1188 SrcPeripheral = 1 (SLC),
1189 DestPeripheral = 1 (SLC),
1190 FlowCntrl = 2 (Pher -> Mem, DMA),
1191 IE = 0,
1192 ITC = 0,
1193 L= 0,
1194 H=0
1195 */
1196 retval = target_write_u32(target, 0x31000110,
1197 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1198 | 0<<15 | 0<<16 | 0<<18);
1199 if (ERROR_OK != retval) {
1200 LOG_ERROR("Could not set DMACC0Config");
1201 return retval;
1202 }
1203 /* Wait finish */
1204 if (!lpc32xx_tc_ready(nand, 100)) {
1205 LOG_ERROR("timeout while waiting for "
1206 "completion of DMA");
1207 return ERROR_NAND_OPERATION_FAILED;
1208 }
1209 } else {
1210 /* Start xfer of data from iram to flash using DMA */
1211 retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1212 if (ERROR_OK != retval) {
1213 LOG_ERROR("DMA OOB failed");
1214 return retval;
1215 }
1216 }
1217
1218 /* Let NAND start actual writing */
1219 retval = nand_write_finish(nand);
1220 if (ERROR_OK != retval) {
1221 LOG_ERROR("nand_write_finish failed");
1222 return retval;
1223 }
1224
1225 return ERROR_OK;
1226 }
1227
1228 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1229 uint8_t *data, uint32_t data_size,
1230 uint8_t *oob, uint32_t oob_size)
1231 {
1232 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1233 struct target *target = nand->target;
1234 int retval = ERROR_OK;
1235
1236 if (target->state != TARGET_HALTED) {
1237 LOG_ERROR("target must be halted to use LPC32xx "
1238 "NAND flash controller");
1239 return ERROR_NAND_OPERATION_FAILED;
1240 }
1241
1242 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1243 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1244 return ERROR_NAND_OPERATION_FAILED;
1245 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1246 if (!data && oob) {
1247 LOG_ERROR("LPC32xx MLC controller can't write "
1248 "OOB data only");
1249 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1250 }
1251
1252 if (oob && (oob_size > 24)) {
1253 LOG_ERROR("LPC32xx MLC controller can't write more "
1254 "than 6 bytes for each quarter's OOB data");
1255 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1256 }
1257
1258 if (data_size > (uint32_t)nand->page_size) {
1259 LOG_ERROR("data size exceeds page size");
1260 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1261 }
1262
1263 retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1264 oob, oob_size);
1265 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1266 struct working_area *pworking_area;
1267 if (!data && oob) {
1268 /*
1269 * if oob only mode is active original method is used
1270 * as SLC controller hangs during DMA interworking. (?)
1271 * Anyway the code supports the oob only mode below.
1272 */
1273 return nand_write_page_raw(nand, page, data,
1274 data_size, oob, oob_size);
1275 }
1276 retval = target_alloc_working_area(target,
1277 nand->page_size + DATA_OFFS,
1278 &pworking_area);
1279 if (retval != ERROR_OK) {
1280 LOG_ERROR("Can't allocate working area in "
1281 "LPC internal RAM");
1282 return ERROR_FLASH_OPERATION_FAILED;
1283 }
1284 retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1285 data, data_size, oob, oob_size);
1286 target_free_working_area(target, pworking_area);
1287 }
1288
1289 return retval;
1290 }
1291
1292 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1293 uint8_t *data, uint32_t data_size,
1294 uint8_t *oob, uint32_t oob_size)
1295 {
1296 struct target *target = nand->target;
1297 static uint8_t page_buffer[2048];
1298 static uint8_t oob_buffer[64];
1299 uint32_t page_bytes_done = 0;
1300 uint32_t oob_bytes_done = 0;
1301 uint32_t mlc_isr;
1302 int retval;
1303
1304 if (!data && oob) {
1305 /* MLC_CMD = Read OOB
1306 * we can use the READOOB command on both small and large page
1307 * devices, as the controller translates the 0x50 command to
1308 * a 0x0 with appropriate positioning of the serial buffer
1309 * read pointer
1310 */
1311 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1312 } else {
1313 /* MLC_CMD = Read0 */
1314 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1315 }
1316 if (ERROR_OK != retval) {
1317 LOG_ERROR("could not set MLC_CMD");
1318 return ERROR_NAND_OPERATION_FAILED;
1319 }
1320 if (nand->page_size == 512) {
1321 /* small page device */
1322 /* MLC_ADDR = 0x0 (one column cycle) */
1323 retval = target_write_u32(target, 0x200b8004, 0x0);
1324 if (ERROR_OK != retval) {
1325 LOG_ERROR("could not set MLC_ADDR");
1326 return ERROR_NAND_OPERATION_FAILED;
1327 }
1328
1329 /* MLC_ADDR = row */
1330 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1331 if (ERROR_OK != retval) {
1332 LOG_ERROR("could not set MLC_ADDR");
1333 return ERROR_NAND_OPERATION_FAILED;
1334 }
1335 retval = target_write_u32(target, 0x200b8004,
1336 (page >> 8) & 0xff);
1337 if (ERROR_OK != retval) {
1338 LOG_ERROR("could not set MLC_ADDR");
1339 return ERROR_NAND_OPERATION_FAILED;
1340 }
1341
1342 if (nand->address_cycles == 4) {
1343 retval = target_write_u32(target, 0x200b8004,
1344 (page >> 16) & 0xff);
1345 if (ERROR_OK != retval) {
1346 LOG_ERROR("could not set MLC_ADDR");
1347 return ERROR_NAND_OPERATION_FAILED;
1348 }
1349 }
1350 } else {
1351 /* large page device */
1352 /* MLC_ADDR = 0x0 (two column cycles) */
1353 retval = target_write_u32(target, 0x200b8004, 0x0);
1354 if (ERROR_OK != retval) {
1355 LOG_ERROR("could not set MLC_ADDR");
1356 return ERROR_NAND_OPERATION_FAILED;
1357 }
1358 retval = target_write_u32(target, 0x200b8004, 0x0);
1359 if (ERROR_OK != retval) {
1360 LOG_ERROR("could not set MLC_ADDR");
1361 return ERROR_NAND_OPERATION_FAILED;
1362 }
1363
1364 /* MLC_ADDR = row */
1365 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1366 if (ERROR_OK != retval) {
1367 LOG_ERROR("could not set MLC_ADDR");
1368 return ERROR_NAND_OPERATION_FAILED;
1369 }
1370 retval = target_write_u32(target, 0x200b8004,
1371 (page >> 8) & 0xff);
1372 if (ERROR_OK != retval) {
1373 LOG_ERROR("could not set MLC_ADDR");
1374 return ERROR_NAND_OPERATION_FAILED;
1375 }
1376
1377 /* MLC_CMD = Read Start */
1378 retval = target_write_u32(target, 0x200b8000,
1379 NAND_CMD_READSTART);
1380 if (ERROR_OK != retval) {
1381 LOG_ERROR("could not set MLC_CMD");
1382 return ERROR_NAND_OPERATION_FAILED;
1383 }
1384 }
1385
1386 while (page_bytes_done < (uint32_t)nand->page_size) {
1387 /* MLC_ECC_AUTO_DEC_REG = dummy */
1388 retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1389 if (ERROR_OK != retval) {
1390 LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1391 return ERROR_NAND_OPERATION_FAILED;
1392 }
1393
1394 if (!lpc32xx_controller_ready(nand, 1000)) {
1395 LOG_ERROR("timeout while waiting for "
1396 "completion of auto decode cycle");
1397 return ERROR_NAND_OPERATION_FAILED;
1398 }
1399
1400 retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1401 if (ERROR_OK != retval) {
1402 LOG_ERROR("could not read MLC_ISR");
1403 return ERROR_NAND_OPERATION_FAILED;
1404 }
1405
1406 if (mlc_isr & 0x8) {
1407 if (mlc_isr & 0x40) {
1408 LOG_ERROR("uncorrectable error detected: "
1409 "0x%2.2x", (unsigned)mlc_isr);
1410 return ERROR_NAND_OPERATION_FAILED;
1411 }
1412
1413 LOG_WARNING("%i symbol error detected and corrected",
1414 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1415 }
1416
1417 if (data) {
1418 retval = target_read_memory(target, 0x200a8000, 4, 128,
1419 page_buffer + page_bytes_done);
1420 if (ERROR_OK != retval) {
1421 LOG_ERROR("could not read MLC_BUF (data)");
1422 return ERROR_NAND_OPERATION_FAILED;
1423 }
1424 }
1425
1426 if (oob) {
1427 retval = target_read_memory(target, 0x200a8000, 4, 4,
1428 oob_buffer + oob_bytes_done);
1429 if (ERROR_OK != retval) {
1430 LOG_ERROR("could not read MLC_BUF (oob)");
1431 return ERROR_NAND_OPERATION_FAILED;
1432 }
1433 }
1434
1435 page_bytes_done += 512;
1436 oob_bytes_done += 16;
1437 }
1438
1439 if (data)
1440 memcpy(data, page_buffer, data_size);
1441
1442 if (oob)
1443 memcpy(oob, oob_buffer, oob_size);
1444
1445 return ERROR_OK;
1446 }
1447
1448 static int lpc32xx_read_page_slc(struct nand_device *nand,
1449 struct working_area *pworking_area,
1450 uint32_t page, uint8_t *data,
1451 uint32_t data_size, uint8_t *oob,
1452 uint32_t oob_size)
1453 {
1454 struct target *target = nand->target;
1455 int retval;
1456 uint32_t target_mem_base;
1457
1458 LOG_DEBUG("SLC read page %x data=%d, oob=%d",
1459 page, data_size, oob_size);
1460
1461 target_mem_base = pworking_area->address;
1462
1463 /* Make the dma descriptors in local memory */
1464 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1465 /* Write them to target.
1466 XXX: Assumes host and target have same byte sex.
1467 */
1468 retval = target_write_memory(target, target_mem_base, 4,
1469 nll * sizeof(dmac_ll_t) / 4,
1470 (uint8_t *)dmalist);
1471 if (ERROR_OK != retval) {
1472 LOG_ERROR("Could not write DMA descriptors to IRAM");
1473 return retval;
1474 }
1475
1476 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1477 if (ERROR_OK != retval) {
1478 LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1479 return retval;
1480 }
1481
1482 /* SLC_CFG =
1483 Force nCE assert,
1484 DMA ECC enabled,
1485 ECC enabled,
1486 DMA burst enabled,
1487 DMA read from SLC,
1488 WIDTH = bus_width
1489 */
1490 retval = target_write_u32(target, 0x20020014, 0x3e);
1491 if (ERROR_OK != retval) {
1492 LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1493 return retval;
1494 }
1495
1496 /* Write first decriptor to DMA controller */
1497 retval = target_write_memory(target, 0x31000100, 4,
1498 sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
1499 if (ERROR_OK != retval) {
1500 LOG_ERROR("Could not write DMA descriptor to DMAC");
1501 return retval;
1502 }
1503
1504 /* Start xfer of data from flash to iram using DMA */
1505 int tot_size = nand->page_size;
1506 tot_size += nand->page_size == 2048 ? 64 : 16;
1507 retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1508 if (ERROR_OK != retval) {
1509 LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1510 return retval;
1511 }
1512
1513 /* Copy data from iram */
1514 if (data) {
1515 retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1516 4, data_size/4, data);
1517 if (ERROR_OK != retval) {
1518 LOG_ERROR("Could not read data from IRAM");
1519 return retval;
1520 }
1521 }
1522 if (oob) {
1523 /* No error correction, just return data as read from flash */
1524 retval = target_read_memory(target,
1525 target_mem_base + SPARE_OFFS, 4,
1526 oob_size/4, oob);
1527 if (ERROR_OK != retval) {
1528 LOG_ERROR("Could not read OOB from IRAM");
1529 return retval;
1530 }
1531 return ERROR_OK;
1532 }
1533
1534 /* Copy OOB from flash, stored in IRAM */
1535 static uint8_t foob[64];
1536 retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1537 4, nand->page_size == 2048 ? 16 : 4, foob);
1538 lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1539 if (ERROR_OK != retval) {
1540 LOG_ERROR("Could not read OOB from IRAM");
1541 return retval;
1542 }
1543 /* Copy ECC from HW, generated while reading */
1544 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1545 static uint32_t hw_ecc[8]; /* max size */
1546 retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1547 ecc_count, (uint8_t *)hw_ecc);
1548 if (ERROR_OK != retval) {
1549 LOG_ERROR("Could not read hw generated ECC from IRAM");
1550 return retval;
1551 }
1552 static uint8_t ecc[24];
1553 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1554 /* Copy ECC from flash using correct layout */
1555 static uint8_t fecc[24]; /* max size */
1556 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1557 int i;
1558 for (i = 0; i < ecc_count * 3; i++)
1559 fecc[i] = foob[layout[i]];
1560 /* Compare ECC and possibly correct data */
1561 for (i = 0; i < ecc_count; i++) {
1562 retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1563 &ecc[i * 3]);
1564 if (retval > 0)
1565 LOG_WARNING("error detected and corrected: %d/%d",
1566 page, i);
1567 if (retval < 0)
1568 break;
1569 }
1570 if (i == ecc_count)
1571 retval = ERROR_OK;
1572 else {
1573 LOG_ERROR("uncorrectable error detected: %d/%d", page, i);
1574 retval = ERROR_NAND_OPERATION_FAILED;
1575 }
1576 return retval;
1577 }
1578
1579 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1580 uint8_t *data, uint32_t data_size,
1581 uint8_t *oob, uint32_t oob_size)
1582 {
1583 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1584 struct target *target = nand->target;
1585 int retval = ERROR_OK;
1586
1587 if (target->state != TARGET_HALTED) {
1588 LOG_ERROR("target must be halted to use LPC32xx "
1589 "NAND flash controller");
1590 return ERROR_NAND_OPERATION_FAILED;
1591 }
1592
1593 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1594 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1595 return ERROR_NAND_OPERATION_FAILED;
1596 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1597 if (data_size > (uint32_t)nand->page_size) {
1598 LOG_ERROR("data size exceeds page size");
1599 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1600 }
1601 retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1602 oob, oob_size);
1603 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1604 struct working_area *pworking_area;
1605
1606 retval = target_alloc_working_area(target,
1607 nand->page_size + 0x200,
1608 &pworking_area);
1609 if (retval != ERROR_OK) {
1610 LOG_ERROR("Can't allocate working area in "
1611 "LPC internal RAM");
1612 return ERROR_FLASH_OPERATION_FAILED;
1613 }
1614 retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1615 data, data_size, oob, oob_size);
1616 target_free_working_area(target, pworking_area);
1617 }
1618
1619 return retval;
1620 }
1621
1622 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1623 {
1624 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1625 struct target *target = nand->target;
1626 int retval;
1627
1628 if (target->state != TARGET_HALTED) {
1629 LOG_ERROR("target must be halted to use LPC32xx "
1630 "NAND flash controller");
1631 return ERROR_NAND_OPERATION_FAILED;
1632 }
1633
1634 LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1635
1636 do {
1637 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1638 uint8_t status;
1639
1640 /* Read MLC_ISR, wait for controller to become ready */
1641 retval = target_read_u8(target, 0x200b8048, &status);
1642 if (ERROR_OK != retval) {
1643 LOG_ERROR("could not set MLC_STAT");
1644 return ERROR_NAND_OPERATION_FAILED;
1645 }
1646
1647 if (status & 2) {
1648 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1649 timeout);
1650 return 1;
1651 }
1652 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1653 uint32_t status;
1654
1655 /* Read SLC_STAT and check READY bit */
1656 retval = target_read_u32(target, 0x20020018, &status);
1657 if (ERROR_OK != retval) {
1658 LOG_ERROR("could not set SLC_STAT");
1659 return ERROR_NAND_OPERATION_FAILED;
1660 }
1661
1662 if (status & 1) {
1663 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1664 timeout);
1665 return 1;
1666 }
1667 }
1668
1669 alive_sleep(1);
1670 } while (timeout-- > 0);
1671
1672 return 0;
1673 }
1674
1675 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1676 {
1677 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1678 struct target *target = nand->target;
1679 int retval;
1680
1681 if (target->state != TARGET_HALTED) {
1682 LOG_ERROR("target must be halted to use LPC32xx "
1683 "NAND flash controller");
1684 return ERROR_NAND_OPERATION_FAILED;
1685 }
1686
1687 LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1688
1689 do {
1690 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1691 uint8_t status = 0x0;
1692
1693 /* Read MLC_ISR, wait for NAND flash device to
1694 * become ready */
1695 retval = target_read_u8(target, 0x200b8048, &status);
1696 if (ERROR_OK != retval) {
1697 LOG_ERROR("could not read MLC_ISR");
1698 return ERROR_NAND_OPERATION_FAILED;
1699 }
1700
1701 if (status & 1) {
1702 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1703 timeout);
1704 return 1;
1705 }
1706 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1707 uint32_t status = 0x0;
1708
1709 /* Read SLC_STAT and check READY bit */
1710 retval = target_read_u32(target, 0x20020018, &status);
1711 if (ERROR_OK != retval) {
1712 LOG_ERROR("could not read SLC_STAT");
1713 return ERROR_NAND_OPERATION_FAILED;
1714 }
1715
1716 if (status & 1) {
1717 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1718 timeout);
1719 return 1;
1720 }
1721 }
1722
1723 alive_sleep(1);
1724 } while (timeout-- > 0);
1725
1726 return 0;
1727 }
1728
1729 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1730 {
1731 struct target *target = nand->target;
1732
1733 LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1734
1735 do {
1736 uint32_t status = 0x0;
1737 int retval;
1738 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1739 retval = target_read_u32(target, 0x2002001c, &status);
1740 if (ERROR_OK != retval) {
1741 LOG_ERROR("Could not read SLC_INT_STAT");
1742 return 0;
1743 }
1744 if (status & 2){
1745 LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1746 return 1;
1747 }
1748
1749 alive_sleep(1);
1750 } while (timeout-- > 0);
1751
1752 return 0;
1753 }
1754
1755 COMMAND_HANDLER(handle_lpc32xx_select_command)
1756 {
1757 struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1758 char *selected[] = {
1759 "no", "mlc", "slc"
1760 };
1761
1762 if ((CMD_ARGC < 1) || (CMD_ARGC > 3)) {
1763 return ERROR_COMMAND_SYNTAX_ERROR;
1764 }
1765
1766 unsigned num;
1767 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1768 struct nand_device *nand = get_nand_device_by_num(num);
1769 if (!nand) {
1770 command_print(CMD_CTX, "nand device '#%s' is out of bounds",
1771 CMD_ARGV[0]);
1772 return ERROR_OK;
1773 }
1774
1775 lpc32xx_info = nand->controller_priv;
1776
1777 if (CMD_ARGC >= 2) {
1778 if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1779 lpc32xx_info->selected_controller =
1780 LPC32xx_MLC_CONTROLLER;
1781 } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1782 lpc32xx_info->selected_controller =
1783 LPC32xx_SLC_CONTROLLER;
1784 } else {
1785 return ERROR_COMMAND_SYNTAX_ERROR;
1786 }
1787 }
1788
1789 command_print(CMD_CTX, "%s controller selected",
1790 selected[lpc32xx_info->selected_controller]);
1791
1792 return ERROR_OK;
1793 }
1794
1795 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1796 {
1797 .name = "select",
1798 .handler = handle_lpc32xx_select_command,
1799 .mode = COMMAND_EXEC,
1800 .help = "select MLC or SLC controller (default is MLC)",
1801 .usage = "bank_id ['mlc'|'slc' ]",
1802 },
1803 COMMAND_REGISTRATION_DONE
1804 };
1805 static const struct command_registration lpc32xx_command_handler[] = {
1806 {
1807 .name = "lpc32xx",
1808 .mode = COMMAND_ANY,
1809 .help = "LPC32xx NAND flash controller commands",
1810 .chain = lpc32xx_exec_command_handlers,
1811 },
1812 COMMAND_REGISTRATION_DONE
1813 };
1814
1815 struct nand_flash_controller lpc32xx_nand_controller = {
1816 .name = "lpc32xx",
1817 .commands = lpc32xx_command_handler,
1818 .nand_device_command = lpc32xx_nand_device_command,
1819 .init = lpc32xx_init,
1820 .reset = lpc32xx_reset,
1821 .command = lpc32xx_command,
1822 .address = lpc32xx_address,
1823 .write_data = lpc32xx_write_data,
1824 .read_data = lpc32xx_read_data,
1825 .write_page = lpc32xx_write_page,
1826 .read_page = lpc32xx_read_page,
1827 .nand_ready = lpc32xx_nand_ready,
1828 };